1
2 #ifndef B43_RADIO_2055_H_
3 #define B43_RADIO_2055_H_
4
5 #include <linux/types.h>
6
7 #include "tables_nphy.h"
8
9 #define B2055_GEN_SPARE 0x00
10 #define B2055_SP_PINPD 0x02
11 #define B2055_C1_SP_RSSI 0x03
12 #define B2055_C1_SP_PDMISC 0x04
13 #define B2055_C2_SP_RSSI 0x05
14 #define B2055_C2_SP_PDMISC 0x06
15 #define B2055_C1_SP_RXGC1 0x07
16 #define B2055_C1_SP_RXGC2 0x08
17 #define B2055_C2_SP_RXGC1 0x09
18 #define B2055_C2_SP_RXGC2 0x0A
19 #define B2055_C1_SP_LPFBWSEL 0x0B
20 #define B2055_C2_SP_LPFBWSEL 0x0C
21 #define B2055_C1_SP_TXGC1 0x0D
22 #define B2055_C1_SP_TXGC2 0x0E
23 #define B2055_C2_SP_TXGC1 0x0F
24 #define B2055_C2_SP_TXGC2 0x10
25 #define B2055_MASTER1 0x11
26 #define B2055_MASTER2 0x12
27 #define B2055_PD_LGEN 0x13
28 #define B2055_PD_PLLTS 0x14
29 #define B2055_C1_PD_LGBUF 0x15
30 #define B2055_C1_PD_TX 0x16
31 #define B2055_C1_PD_RXTX 0x17
32 #define B2055_C1_PD_RSSIMISC 0x18
33 #define B2055_C2_PD_LGBUF 0x19
34 #define B2055_C2_PD_TX 0x1A
35 #define B2055_C2_PD_RXTX 0x1B
36 #define B2055_C2_PD_RSSIMISC 0x1C
37 #define B2055_PWRDET_LGEN 0x1D
38 #define B2055_C1_PWRDET_LGBUF 0x1E
39 #define B2055_C1_PWRDET_RXTX 0x1F
40 #define B2055_C2_PWRDET_LGBUF 0x20
41 #define B2055_C2_PWRDET_RXTX 0x21
42 #define B2055_RRCCAL_CS 0x22
43 #define B2055_RRCCAL_NOPTSEL 0x23
44 #define B2055_CAL_MISC 0x24
45 #define B2055_CAL_COUT 0x25
46 #define B2055_CAL_COUT2 0x26
47 #define B2055_CAL_CVARCTL 0x27
48 #define B2055_CAL_RVARCTL 0x28
49 #define B2055_CAL_LPOCTL 0x29
50 #define B2055_CAL_TS 0x2A
51 #define B2055_CAL_RCCALRTS 0x2B
52 #define B2055_CAL_RCALRTS 0x2C
53 #define B2055_PADDRV 0x2D
54 #define B2055_XOCTL1 0x2E
55 #define B2055_XOCTL2 0x2F
56 #define B2055_XOREGUL 0x30
57 #define B2055_XOMISC 0x31
58 #define B2055_PLL_LFC1 0x32
59 #define B2055_PLL_CALVTH 0x33
60 #define B2055_PLL_LFC2 0x34
61 #define B2055_PLL_REF 0x35
62 #define B2055_PLL_LFR1 0x36
63 #define B2055_PLL_PFDCP 0x37
64 #define B2055_PLL_IDAC_CPOPAMP 0x38
65 #define B2055_PLL_CPREG 0x39
66 #define B2055_PLL_RCAL 0x3A
67 #define B2055_RF_PLLMOD0 0x3B
68 #define B2055_RF_PLLMOD1 0x3C
69 #define B2055_RF_MMDIDAC1 0x3D
70 #define B2055_RF_MMDIDAC0 0x3E
71 #define B2055_RF_MMDSP 0x3F
72 #define B2055_VCO_CAL1 0x40
73 #define B2055_VCO_CAL2 0x41
74 #define B2055_VCO_CAL3 0x42
75 #define B2055_VCO_CAL4 0x43
76 #define B2055_VCO_CAL5 0x44
77 #define B2055_VCO_CAL6 0x45
78 #define B2055_VCO_CAL7 0x46
79 #define B2055_VCO_CAL8 0x47
80 #define B2055_VCO_CAL9 0x48
81 #define B2055_VCO_CAL10 0x49
82 #define B2055_VCO_CAL11 0x4A
83 #define B2055_VCO_CAL12 0x4B
84 #define B2055_VCO_CAL13 0x4C
85 #define B2055_VCO_CAL14 0x4D
86 #define B2055_VCO_CAL15 0x4E
87 #define B2055_VCO_CAL16 0x4F
88 #define B2055_VCO_KVCO 0x50
89 #define B2055_VCO_CAPTAIL 0x51
90 #define B2055_VCO_IDACVCO 0x52
91 #define B2055_VCO_REG 0x53
92 #define B2055_PLL_RFVTH 0x54
93 #define B2055_LGBUF_CENBUF 0x55
94 #define B2055_LGEN_TUNE1 0x56
95 #define B2055_LGEN_TUNE2 0x57
96 #define B2055_LGEN_IDAC1 0x58
97 #define B2055_LGEN_IDAC2 0x59
98 #define B2055_LGEN_BIASC 0x5A
99 #define B2055_LGEN_BIASIDAC 0x5B
100 #define B2055_LGEN_RCAL 0x5C
101 #define B2055_LGEN_DIV 0x5D
102 #define B2055_LGEN_SPARE2 0x5E
103 #define B2055_C1_LGBUF_ATUNE 0x5F
104 #define B2055_C1_LGBUF_GTUNE 0x60
105 #define B2055_C1_LGBUF_DIV 0x61
106 #define B2055_C1_LGBUF_AIDAC 0x62
107 #define B2055_C1_LGBUF_GIDAC 0x63
108 #define B2055_C1_LGBUF_IDACFO 0x64
109 #define B2055_C1_LGBUF_SPARE 0x65
110 #define B2055_C1_RX_RFSPC1 0x66
111 #define B2055_C1_RX_RFR1 0x67
112 #define B2055_C1_RX_RFR2 0x68
113 #define B2055_C1_RX_RFRCAL 0x69
114 #define B2055_C1_RX_BB_BLCMP 0x6A
115 #define B2055_C1_RX_BB_LPF 0x6B
116 #define B2055_C1_RX_BB_MIDACHP 0x6C
117 #define B2055_C1_RX_BB_VGA1IDAC 0x6D
118 #define B2055_C1_RX_BB_VGA2IDAC 0x6E
119 #define B2055_C1_RX_BB_VGA3IDAC 0x6F
120 #define B2055_C1_RX_BB_BUFOCTL 0x70
121 #define B2055_C1_RX_BB_RCCALCTL 0x71
122 #define B2055_C1_RX_BB_RSSICTL1 0x72
123 #define B2055_C1_RX_BB_RSSICTL2 0x73
124 #define B2055_C1_RX_BB_RSSICTL3 0x74
125 #define B2055_C1_RX_BB_RSSICTL4 0x75
126 #define B2055_C1_RX_BB_RSSICTL5 0x76
127 #define B2055_C1_RX_BB_REG 0x77
128 #define B2055_C1_RX_BB_SPARE1 0x78
129 #define B2055_C1_RX_TXBBRCAL 0x79
130 #define B2055_C1_TX_RF_SPGA 0x7A
131 #define B2055_C1_TX_RF_SPAD 0x7B
132 #define B2055_C1_TX_RF_CNTPGA1 0x7C
133 #define B2055_C1_TX_RF_CNTPAD1 0x7D
134 #define B2055_C1_TX_RF_PGAIDAC 0x7E
135 #define B2055_C1_TX_PGAPADTN 0x7F
136 #define B2055_C1_TX_PADIDAC1 0x80
137 #define B2055_C1_TX_PADIDAC2 0x81
138 #define B2055_C1_TX_MXBGTRIM 0x82
139 #define B2055_C1_TX_RF_RCAL 0x83
140 #define B2055_C1_TX_RF_PADTSSI1 0x84
141 #define B2055_C1_TX_RF_PADTSSI2 0x85
142 #define B2055_C1_TX_RF_SPARE 0x86
143 #define B2055_C1_TX_RF_IQCAL1 0x87
144 #define B2055_C1_TX_RF_IQCAL2 0x88
145 #define B2055_C1_TXBB_RCCAL 0x89
146 #define B2055_C1_TXBB_LPF1 0x8A
147 #define B2055_C1_TX_VOSCNCL 0x8B
148 #define B2055_C1_TX_LPF_MXGMIDAC 0x8C
149 #define B2055_C1_TX_BB_MXGM 0x8D
150 #define B2055_C2_LGBUF_ATUNE 0x8E
151 #define B2055_C2_LGBUF_GTUNE 0x8F
152 #define B2055_C2_LGBUF_DIV 0x90
153 #define B2055_C2_LGBUF_AIDAC 0x91
154 #define B2055_C2_LGBUF_GIDAC 0x92
155 #define B2055_C2_LGBUF_IDACFO 0x93
156 #define B2055_C2_LGBUF_SPARE 0x94
157 #define B2055_C2_RX_RFSPC1 0x95
158 #define B2055_C2_RX_RFR1 0x96
159 #define B2055_C2_RX_RFR2 0x97
160 #define B2055_C2_RX_RFRCAL 0x98
161 #define B2055_C2_RX_BB_BLCMP 0x99
162 #define B2055_C2_RX_BB_LPF 0x9A
163 #define B2055_C2_RX_BB_MIDACHP 0x9B
164 #define B2055_C2_RX_BB_VGA1IDAC 0x9C
165 #define B2055_C2_RX_BB_VGA2IDAC 0x9D
166 #define B2055_C2_RX_BB_VGA3IDAC 0x9E
167 #define B2055_C2_RX_BB_BUFOCTL 0x9F
168 #define B2055_C2_RX_BB_RCCALCTL 0xA0
169 #define B2055_C2_RX_BB_RSSICTL1 0xA1
170 #define B2055_C2_RX_BB_RSSICTL2 0xA2
171 #define B2055_C2_RX_BB_RSSICTL3 0xA3
172 #define B2055_C2_RX_BB_RSSICTL4 0xA4
173 #define B2055_C2_RX_BB_RSSICTL5 0xA5
174 #define B2055_C2_RX_BB_REG 0xA6
175 #define B2055_C2_RX_BB_SPARE1 0xA7
176 #define B2055_C2_RX_TXBBRCAL 0xA8
177 #define B2055_C2_TX_RF_SPGA 0xA9
178 #define B2055_C2_TX_RF_SPAD 0xAA
179 #define B2055_C2_TX_RF_CNTPGA1 0xAB
180 #define B2055_C2_TX_RF_CNTPAD1 0xAC
181 #define B2055_C2_TX_RF_PGAIDAC 0xAD
182 #define B2055_C2_TX_PGAPADTN 0xAE
183 #define B2055_C2_TX_PADIDAC1 0xAF
184 #define B2055_C2_TX_PADIDAC2 0xB0
185 #define B2055_C2_TX_MXBGTRIM 0xB1
186 #define B2055_C2_TX_RF_RCAL 0xB2
187 #define B2055_C2_TX_RF_PADTSSI1 0xB3
188 #define B2055_C2_TX_RF_PADTSSI2 0xB4
189 #define B2055_C2_TX_RF_SPARE 0xB5
190 #define B2055_C2_TX_RF_IQCAL1 0xB6
191 #define B2055_C2_TX_RF_IQCAL2 0xB7
192 #define B2055_C2_TXBB_RCCAL 0xB8
193 #define B2055_C2_TXBB_LPF1 0xB9
194 #define B2055_C2_TX_VOSCNCL 0xBA
195 #define B2055_C2_TX_LPF_MXGMIDAC 0xBB
196 #define B2055_C2_TX_BB_MXGM 0xBC
197 #define B2055_PRG_GCHP21 0xBD
198 #define B2055_PRG_GCHP22 0xBE
199 #define B2055_PRG_GCHP23 0xBF
200 #define B2055_PRG_GCHP24 0xC0
201 #define B2055_PRG_GCHP25 0xC1
202 #define B2055_PRG_GCHP26 0xC2
203 #define B2055_PRG_GCHP27 0xC3
204 #define B2055_PRG_GCHP28 0xC4
205 #define B2055_PRG_GCHP29 0xC5
206 #define B2055_PRG_GCHP30 0xC6
207 #define B2055_C1_LNA_GAINBST 0xCD
208 #define B2055_C1_B0NB_RSSIVCM 0xD2
209 #define B2055_C1_GENSPARE2 0xD6
210 #define B2055_C2_LNA_GAINBST 0xD9
211 #define B2055_C2_B0NB_RSSIVCM 0xDE
212 #define B2055_C2_GENSPARE2 0xE2
213
214 struct b43_nphy_channeltab_entry_rev2 {
215
216 u8 channel;
217
218 u16 freq;
219
220 u16 unk2;
221
222 u8 radio_pll_ref;
223 u8 radio_rf_pllmod0;
224 u8 radio_rf_pllmod1;
225 u8 radio_vco_captail;
226 u8 radio_vco_cal1;
227 u8 radio_vco_cal2;
228 u8 radio_pll_lfc1;
229 u8 radio_pll_lfr1;
230 u8 radio_pll_lfc2;
231 u8 radio_lgbuf_cenbuf;
232 u8 radio_lgen_tune1;
233 u8 radio_lgen_tune2;
234 u8 radio_c1_lgbuf_atune;
235 u8 radio_c1_lgbuf_gtune;
236 u8 radio_c1_rx_rfr1;
237 u8 radio_c1_tx_pgapadtn;
238 u8 radio_c1_tx_mxbgtrim;
239 u8 radio_c2_lgbuf_atune;
240 u8 radio_c2_lgbuf_gtune;
241 u8 radio_c2_rx_rfr1;
242 u8 radio_c2_tx_pgapadtn;
243 u8 radio_c2_tx_mxbgtrim;
244
245 struct b43_phy_n_sfo_cfg phy_regs;
246 };
247
248
249
250
251
252 void b2055_upload_inittab(struct b43_wldev *dev,
253 bool ghz5, bool ignore_uploadflag);
254
255
256
257 const struct b43_nphy_channeltab_entry_rev2 *
258 b43_nphy_get_chantabent_rev2(struct b43_wldev *dev, u8 channel);
259
260 #endif