root/drivers/net/wireless/realtek/rtlwifi/rtl8723be/fw.h

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INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright(c) 2009-2014  Realtek Corporation.*/
   3 
   4 #ifndef __RTL8723BE__FW__H__
   5 #define __RTL8723BE__FW__H__
   6 
   7 #define FW_8192C_SIZE                           0x8000
   8 #define FW_8192C_START_ADDRESS                  0x1000
   9 #define FW_8192C_END_ADDRESS                    0x5FFF
  10 #define FW_8192C_PAGE_SIZE                      4096
  11 #define FW_8192C_POLLING_DELAY                  5
  12 
  13 #define USE_OLD_WOWLAN_DEBUG_FW                 0
  14 
  15 #define H2C_PWEMODE_LENGTH                      7
  16 
  17 /* Fw PS state for RPWM.
  18 *BIT[2:0] = HW state
  19 *BIT[3] = Protocol PS state, 1: register active state , 0: register sleep state
  20 *BIT[4] = sub-state
  21 */
  22 #define FW_PS_RF_ON             BIT(2)
  23 #define FW_PS_REGISTER_ACTIVE   BIT(3)
  24 
  25 #define FW_PS_ACK               BIT(6)
  26 #define FW_PS_TOGGLE            BIT(7)
  27 
  28  /* 8723BE RPWM value*/
  29  /* BIT[0] = 1: 32k, 0: 40M*/
  30 #define FW_PS_CLOCK_OFF         BIT(0)          /* 32k*/
  31 #define FW_PS_CLOCK_ON          0               /*40M*/
  32 
  33 #define FW_PS_STATE_MASK        (0x0F)
  34 #define FW_PS_STATE_HW_MASK     (0x07)
  35 /*ISR_ENABLE, IMR_ENABLE, and PS mode should be inherited.*/
  36 #define FW_PS_STATE_INT_MASK    (0x3F)
  37 
  38 #define FW_PS_STATE(x)          (FW_PS_STATE_MASK & (x))
  39 
  40 /* ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))*/
  41 #define FW_PS_STATE_ALL_ON      (FW_PS_CLOCK_ON)
  42 /* (FW_PS_RF_ON)*/
  43 #define FW_PS_STATE_RF_ON       (FW_PS_CLOCK_ON)
  44 /* 0x0*/
  45 #define FW_PS_STATE_RF_OFF      (FW_PS_CLOCK_ON)
  46 /* (FW_PS_STATE_RF_OFF)*/
  47 #define FW_PS_STATE_RF_OFF_LOW_PWR      (FW_PS_CLOCK_OFF)
  48 
  49 
  50 /* For 8723BE H2C PwrMode Cmd ID 5.*/
  51 #define FW_PWR_STATE_ACTIVE     ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))
  52 #define FW_PWR_STATE_RF_OFF     0
  53 
  54 #define FW_PS_IS_ACK(x)         ((x) & FW_PS_ACK)
  55 
  56 #define IS_IN_LOW_POWER_STATE(__fwpsstate)      \
  57         (FW_PS_STATE(__fwpsstate) == FW_PS_CLOCK_OFF)
  58 
  59 #define FW_PWR_STATE_ACTIVE     ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))
  60 #define FW_PWR_STATE_RF_OFF     0
  61 
  62 enum rtl8723b_h2c_cmd {
  63         H2C_8723B_RSVDPAGE = 0,
  64         H2C_8723B_MSRRPT = 1,
  65         H2C_8723B_SCAN = 2,
  66         H2C_8723B_KEEP_ALIVE_CTRL = 3,
  67         H2C_8723B_DISCONNECT_DECISION = 4,
  68         H2C_8723B_BCN_RSVDPAGE = 9,
  69         H2C_8723B_PROBERSP_RSVDPAGE = 10,
  70 
  71         H2C_8723B_SETPWRMODE = 0x20,
  72         H2C_8723B_PS_LPS_PARA = 0x23,
  73         H2C_8723B_P2P_PS_OFFLOAD = 0x24,
  74 
  75         H2C_8723B_RA_MASK = 0x40,
  76         H2C_RSSIBE_REPORT = 0x42,
  77         /*Not defined CTW CMD for P2P yet*/
  78         H2C_8723B_P2P_PS_CTW_CMD,
  79         MAX_8723B_H2CCMD
  80 };
  81 
  82 #define pagenum_128(_len) (u32)(((_len)>>7) + ((_len)&0x7F ? 1 : 0))
  83 
  84 
  85 #define SET_H2CCMD_PWRMODE_PARM_MODE(__ph2ccmd, __val)                  \
  86         SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
  87 #define SET_H2CCMD_PWRMODE_PARM_RLBM(__ph2ccmd, __val)                  \
  88         SET_BITS_TO_LE_1BYTE((__ph2ccmd)+1, 0, 4, __val)
  89 #define SET_H2CCMD_PWRMODE_PARM_SMART_PS(__ph2ccmd, __val)              \
  90         SET_BITS_TO_LE_1BYTE((__ph2ccmd)+1, 4, 4, __val)
  91 #define SET_H2CCMD_PWRMODE_PARM_AWAKE_INTERVAL(__ph2ccmd, __val)        \
  92         SET_BITS_TO_LE_1BYTE((__ph2ccmd)+2, 0, 8, __val)
  93 #define SET_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__ph2ccmd, __val)       \
  94         SET_BITS_TO_LE_1BYTE((__ph2ccmd)+3, 0, 8, __val)
  95 #define SET_H2CCMD_PWRMODE_PARM_PWR_STATE(__ph2ccmd, __val)             \
  96         SET_BITS_TO_LE_1BYTE((__ph2ccmd)+4, 0, 8, __val)
  97 #define SET_H2CCMD_PWRMODE_PARM_BYTE5(__ph2ccmd, __val)                 \
  98         SET_BITS_TO_LE_1BYTE((__ph2ccmd) + 5, 0, 8, __val)
  99 #define GET_88E_H2CCMD_PWRMODE_PARM_MODE(__ph2ccmd)                     \
 100         LE_BITS_TO_1BYTE(__ph2ccmd, 0, 8)
 101 
 102 #define SET_H2CCMD_MSRRPT_PARM_OPMODE(__ph2ccmd, __val)         \
 103         SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 1, __val)
 104 #define SET_H2CCMD_MSRRPT_PARM_MACID_IND(__ph2ccmd, __val)      \
 105         SET_BITS_TO_LE_1BYTE(__ph2ccmd, 1, 1, __val)
 106 
 107 #define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__ph2ccmd, __val)             \
 108         SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
 109 #define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__ph2ccmd, __val)                \
 110         SET_BITS_TO_LE_1BYTE((__ph2ccmd)+1, 0, 8, __val)
 111 #define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__ph2ccmd, __val)             \
 112         SET_BITS_TO_LE_1BYTE((__ph2ccmd)+2, 0, 8, __val)
 113 #define SET_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__ph2ccmd, __val) \
 114         SET_BITS_TO_LE_1BYTE((__ph2ccmd) + 3, 0, 8, __val)
 115 #define SET_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__ph2ccmd, __val)      \
 116         SET_BITS_TO_LE_1BYTE((__ph2ccmd) + 4, 0, 8, __val)
 117 
 118 
 119 void rtl8723be_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id,
 120                             u32 cmd_len, u8 *p_cmdbuffer);
 121 void rtl8723be_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode);
 122 void rtl8723be_set_fw_media_status_rpt_cmd(struct ieee80211_hw *hw, u8 mstatus);
 123 void rtl8723be_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished);
 124 void rtl8723be_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state);
 125 #endif
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