1
2
3
4 #ifndef __RTL92D_REG_H__
5 #define __RTL92D_REG_H__
6
7
8
9
10 #define REG_SYS_ISO_CTRL 0x0000
11 #define REG_SYS_FUNC_EN 0x0002
12 #define REG_APS_FSMCO 0x0004
13 #define REG_SYS_CLKR 0x0008
14 #define REG_9346CR 0x000A
15 #define REG_EE_VPD 0x000C
16 #define REG_AFE_MISC 0x0010
17 #define REG_SPS0_CTRL 0x0011
18 #define REG_POWER_OFF_IN_PROCESS 0x0017
19 #define REG_SPS_OCP_CFG 0x0018
20 #define REG_RSV_CTRL 0x001C
21 #define REG_RF_CTRL 0x001F
22 #define REG_LDOA15_CTRL 0x0020
23 #define REG_LDOV12D_CTRL 0x0021
24 #define REG_LDOHCI12_CTRL 0x0022
25 #define REG_LPLDO_CTRL 0x0023
26 #define REG_AFE_XTAL_CTRL 0x0024
27 #define REG_AFE_PLL_CTRL 0x0028
28
29 #define REG_MAC_PHY_CTRL 0x002c
30 #define REG_EFUSE_CTRL 0x0030
31 #define REG_EFUSE_TEST 0x0034
32 #define REG_PWR_DATA 0x0038
33 #define REG_CAL_TIMER 0x003C
34 #define REG_ACLK_MON 0x003E
35 #define REG_GPIO_MUXCFG 0x0040
36 #define REG_GPIO_IO_SEL 0x0042
37 #define REG_MAC_PINMUX_CFG 0x0043
38 #define REG_GPIO_PIN_CTRL 0x0044
39 #define REG_GPIO_INTM 0x0048
40 #define REG_LEDCFG0 0x004C
41 #define REG_LEDCFG1 0x004D
42 #define REG_LEDCFG2 0x004E
43 #define REG_LEDCFG3 0x004F
44 #define REG_FSIMR 0x0050
45 #define REG_FSISR 0x0054
46
47 #define REG_MCUFWDL 0x0080
48
49 #define REG_HMEBOX_EXT_0 0x0088
50 #define REG_HMEBOX_EXT_1 0x008A
51 #define REG_HMEBOX_EXT_2 0x008C
52 #define REG_HMEBOX_EXT_3 0x008E
53
54 #define REG_BIST_SCAN 0x00D0
55 #define REG_BIST_RPT 0x00D4
56 #define REG_BIST_ROM_RPT 0x00D8
57 #define REG_USB_SIE_INTF 0x00E0
58 #define REG_PCIE_MIO_INTF 0x00E4
59 #define REG_PCIE_MIO_INTD 0x00E8
60 #define REG_HPON_FSM 0x00EC
61 #define REG_SYS_CFG 0x00F0
62 #define REG_MAC_PHY_CTRL_NORMAL 0x00f8
63
64 #define REG_MAC0 0x0081
65 #define REG_MAC1 0x0053
66 #define FW_MAC0_READY 0x18
67 #define FW_MAC1_READY 0x1A
68 #define MAC0_ON BIT(7)
69 #define MAC1_ON BIT(0)
70 #define MAC0_READY BIT(0)
71 #define MAC1_READY BIT(0)
72
73
74
75
76 #define REG_CR 0x0100
77 #define REG_PBP 0x0104
78 #define REG_TRXDMA_CTRL 0x010C
79 #define REG_TRXFF_BNDY 0x0114
80 #define REG_TRXFF_STATUS 0x0118
81 #define REG_RXFF_PTR 0x011C
82 #define REG_HIMR 0x0120
83 #define REG_HISR 0x0124
84 #define REG_HIMRE 0x0128
85 #define REG_HISRE 0x012C
86 #define REG_CPWM 0x012F
87 #define REG_FWIMR 0x0130
88 #define REG_FWISR 0x0134
89 #define REG_PKTBUF_DBG_CTRL 0x0140
90 #define REG_PKTBUF_DBG_DATA_L 0x0144
91 #define REG_PKTBUF_DBG_DATA_H 0x0148
92
93 #define REG_TC0_CTRL 0x0150
94 #define REG_TC1_CTRL 0x0154
95 #define REG_TC2_CTRL 0x0158
96 #define REG_TC3_CTRL 0x015C
97 #define REG_TC4_CTRL 0x0160
98 #define REG_TCUNIT_BASE 0x0164
99 #define REG_MBIST_START 0x0174
100 #define REG_MBIST_DONE 0x0178
101 #define REG_MBIST_FAIL 0x017C
102 #define REG_C2HEVT_MSG_NORMAL 0x01A0
103 #define REG_C2HEVT_MSG_TEST 0x01B8
104 #define REG_C2HEVT_CLEAR 0x01BF
105 #define REG_MCUTST_1 0x01c0
106 #define REG_FMETHR 0x01C8
107 #define REG_HMETFR 0x01CC
108 #define REG_HMEBOX_0 0x01D0
109 #define REG_HMEBOX_1 0x01D4
110 #define REG_HMEBOX_2 0x01D8
111 #define REG_HMEBOX_3 0x01DC
112
113 #define REG_LLT_INIT 0x01E0
114 #define REG_BB_ACCEESS_CTRL 0x01E8
115 #define REG_BB_ACCESS_DATA 0x01EC
116
117
118
119
120
121 #define REG_RQPN 0x0200
122 #define REG_FIFOPAGE 0x0204
123 #define REG_TDECTRL 0x0208
124 #define REG_TXDMA_OFFSET_CHK 0x020C
125 #define REG_TXDMA_STATUS 0x0210
126 #define REG_RQPN_NPQ 0x0214
127
128
129
130
131 #define REG_RXDMA_AGG_PG_TH 0x0280
132 #define REG_RXPKT_NUM 0x0284
133 #define REG_RXDMA_STATUS 0x0288
134
135
136
137
138 #define REG_PCIE_CTRL_REG 0x0300
139 #define REG_INT_MIG 0x0304
140 #define REG_BCNQ_DESA 0x0308
141 #define REG_HQ_DESA 0x0310
142 #define REG_MGQ_DESA 0x0318
143 #define REG_VOQ_DESA 0x0320
144 #define REG_VIQ_DESA 0x0328
145 #define REG_BEQ_DESA 0x0330
146 #define REG_BKQ_DESA 0x0338
147 #define REG_RX_DESA 0x0340
148 #define REG_DBI 0x0348
149 #define REG_DBI_WDATA 0x0348
150 #define REG_DBI_RDATA 0x034C
151 #define REG_DBI_CTRL 0x0350
152 #define REG_DBI_FLAG 0x0352
153 #define REG_MDIO 0x0354
154 #define REG_DBG_SEL 0x0360
155 #define REG_PCIE_HRPWM 0x0361
156 #define REG_PCIE_HCPWM 0x0363
157 #define REG_UART_CTRL 0x0364
158 #define REG_UART_TX_DESA 0x0370
159 #define REG_UART_RX_DESA 0x0378
160
161
162
163
164 #define REG_VOQ_INFORMATION 0x0400
165 #define REG_VIQ_INFORMATION 0x0404
166 #define REG_BEQ_INFORMATION 0x0408
167 #define REG_BKQ_INFORMATION 0x040C
168 #define REG_MGQ_INFORMATION 0x0410
169 #define REG_HGQ_INFORMATION 0x0414
170 #define REG_BCNQ_INFORMATION 0x0418
171
172
173 #define REG_CPU_MGQ_INFORMATION 0x041C
174 #define REG_FWHW_TXQ_CTRL 0x0420
175 #define REG_HWSEQ_CTRL 0x0423
176 #define REG_TXPKTBUF_BCNQ_BDNY 0x0424
177 #define REG_TXPKTBUF_MGQ_BDNY 0x0425
178 #define REG_MULTI_BCNQ_EN 0x0426
179 #define REG_MULTI_BCNQ_OFFSET 0x0427
180 #define REG_SPEC_SIFS 0x0428
181 #define REG_RL 0x042A
182 #define REG_DARFRC 0x0430
183 #define REG_RARFRC 0x0438
184 #define REG_RRSR 0x0440
185 #define REG_ARFR0 0x0444
186 #define REG_ARFR1 0x0448
187 #define REG_ARFR2 0x044C
188 #define REG_ARFR3 0x0450
189 #define REG_AGGLEN_LMT 0x0458
190 #define REG_AMPDU_MIN_SPACE 0x045C
191 #define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D
192 #define REG_FAST_EDCA_CTRL 0x0460
193 #define REG_RD_RESP_PKT_TH 0x0463
194 #define REG_INIRTS_RATE_SEL 0x0480
195 #define REG_INIDATA_RATE_SEL 0x0484
196 #define REG_POWER_STATUS 0x04A4
197 #define REG_POWER_STAGE1 0x04B4
198 #define REG_POWER_STAGE2 0x04B8
199 #define REG_PKT_LIFE_TIME 0x04C0
200 #define REG_STBC_SETTING 0x04C4
201 #define REG_PROT_MODE_CTRL 0x04C8
202 #define REG_MAX_AGGR_NUM 0x04CA
203 #define REG_RTS_MAX_AGGR_NUM 0x04CB
204 #define REG_BAR_MODE_CTRL 0x04CC
205 #define REG_RA_TRY_RATE_AGG_LMT 0x04CF
206 #define REG_EARLY_MODE_CONTROL 0x4D0
207 #define REG_NQOS_SEQ 0x04DC
208 #define REG_QOS_SEQ 0x04DE
209 #define REG_NEED_CPU_HANDLE 0x04E0
210 #define REG_PKT_LOSE_RPT 0x04E1
211 #define REG_PTCL_ERR_STATUS 0x04E2
212 #define REG_DUMMY 0x04FC
213
214
215
216
217 #define REG_EDCA_VO_PARAM 0x0500
218 #define REG_EDCA_VI_PARAM 0x0504
219 #define REG_EDCA_BE_PARAM 0x0508
220 #define REG_EDCA_BK_PARAM 0x050C
221 #define REG_BCNTCFG 0x0510
222 #define REG_PIFS 0x0512
223 #define REG_RDG_PIFS 0x0513
224 #define REG_SIFS_CTX 0x0514
225 #define REG_SIFS_TRX 0x0516
226 #define REG_AGGR_BREAK_TIME 0x051A
227 #define REG_SLOT 0x051B
228 #define REG_TX_PTCL_CTRL 0x0520
229 #define REG_TXPAUSE 0x0522
230 #define REG_DIS_TXREQ_CLR 0x0523
231 #define REG_RD_CTRL 0x0524
232 #define REG_TBTT_PROHIBIT 0x0540
233 #define REG_RD_NAV_NXT 0x0544
234 #define REG_NAV_PROT_LEN 0x0546
235 #define REG_BCN_CTRL 0x0550
236 #define REG_MBID_NUM 0x0552
237 #define REG_DUAL_TSF_RST 0x0553
238 #define REG_BCN_INTERVAL 0x0554
239 #define REG_MBSSID_BCN_SPACE 0x0554
240 #define REG_DRVERLYINT 0x0558
241 #define REG_BCNDMATIM 0x0559
242 #define REG_ATIMWND 0x055A
243 #define REG_USTIME_TSF 0x055C
244 #define REG_BCN_MAX_ERR 0x055D
245 #define REG_RXTSF_OFFSET_CCK 0x055E
246 #define REG_RXTSF_OFFSET_OFDM 0x055F
247 #define REG_TSFTR 0x0560
248 #define REG_INIT_TSFTR 0x0564
249 #define REG_PSTIMER 0x0580
250 #define REG_TIMER0 0x0584
251 #define REG_TIMER1 0x0588
252 #define REG_ACMHWCTRL 0x05C0
253 #define REG_ACMRSTCTRL 0x05C1
254 #define REG_ACMAVG 0x05C2
255 #define REG_VO_ADMTIME 0x05C4
256 #define REG_VI_ADMTIME 0x05C6
257 #define REG_BE_ADMTIME 0x05C8
258 #define REG_EDCA_RANDOM_GEN 0x05CC
259 #define REG_SCH_TXCMD 0x05D0
260
261
262 #define REG_DMC 0x05F0
263
264
265
266
267 #define REG_APSD_CTRL 0x0600
268 #define REG_BWOPMODE 0x0603
269 #define REG_TCR 0x0604
270 #define REG_RCR 0x0608
271 #define REG_RX_PKT_LIMIT 0x060C
272 #define REG_RX_DLK_TIME 0x060D
273 #define REG_RX_DRVINFO_SZ 0x060F
274
275 #define REG_MACID 0x0610
276 #define REG_BSSID 0x0618
277 #define REG_MAR 0x0620
278 #define REG_MBIDCAMCFG 0x0628
279
280 #define REG_USTIME_EDCA 0x0638
281 #define REG_MAC_SPEC_SIFS 0x063A
282 #define REG_RESP_SIFS_CCK 0x063C
283 #define REG_RESP_SIFS_OFDM 0x063E
284 #define REG_ACKTO 0x0640
285 #define REG_CTS2TO 0x0641
286 #define REG_EIFS 0x0642
287
288
289
290 #define REG_NAV_CTRL 0x0650
291 #define REG_BACAMCMD 0x0654
292 #define REG_BACAMCONTENT 0x0658
293 #define REG_LBDLY 0x0660
294 #define REG_FWDLY 0x0661
295 #define REG_RXERR_RPT 0x0664
296 #define REG_WMAC_TRXPTCL_CTL 0x0668
297
298
299
300 #define REG_CAMCMD 0x0670
301 #define REG_CAMWRITE 0x0674
302 #define REG_CAMREAD 0x0678
303 #define REG_CAMDBG 0x067C
304 #define REG_SECCFG 0x0680
305
306
307 #define REG_WOW_CTRL 0x0690
308 #define REG_PSSTATUS 0x0691
309 #define REG_PS_RX_INFO 0x0692
310 #define REG_LPNAV_CTRL 0x0694
311 #define REG_WKFMCAM_CMD 0x0698
312 #define REG_WKFMCAM_RWD 0x069C
313 #define REG_RXFLTMAP0 0x06A0
314 #define REG_RXFLTMAP1 0x06A2
315 #define REG_RXFLTMAP2 0x06A4
316 #define REG_BCN_PSR_RPT 0x06A8
317 #define REG_CALB32K_CTRL 0x06AC
318 #define REG_PKT_MON_CTRL 0x06B4
319 #define REG_BT_COEX_TABLE 0x06C0
320 #define REG_WMAC_RESP_TXINFO 0x06D8
321
322
323
324
325
326 #define CR9346 REG_9346CR
327 #define MSR (REG_CR + 2)
328 #define ISR REG_HISR
329 #define TSFR REG_TSFTR
330
331 #define MACIDR0 REG_MACID
332 #define MACIDR4 (REG_MACID + 4)
333
334 #define PBP REG_PBP
335
336 #define IDR0 MACIDR0
337 #define IDR4 MACIDR4
338
339
340
341
342 #define MSR_NOLINK 0x00
343 #define MSR_ADHOC 0x01
344 #define MSR_INFRA 0x02
345 #define MSR_AP 0x03
346 #define MSR_MASK 0x03
347
348
349
350
351
352 #define RRSR_RSC_OFFSET 21
353 #define RRSR_SHORT_OFFSET 23
354 #define RRSR_RSC_BW_40M 0x600000
355 #define RRSR_RSC_UPSUBCHNL 0x400000
356 #define RRSR_RSC_LOWSUBCHNL 0x200000
357 #define RRSR_SHORT 0x800000
358 #define RRSR_1M BIT0
359 #define RRSR_2M BIT1
360 #define RRSR_5_5M BIT2
361 #define RRSR_11M BIT3
362 #define RRSR_6M BIT4
363 #define RRSR_9M BIT5
364 #define RRSR_12M BIT6
365 #define RRSR_18M BIT7
366 #define RRSR_24M BIT8
367 #define RRSR_36M BIT9
368 #define RRSR_48M BIT10
369 #define RRSR_54M BIT11
370 #define RRSR_MCS0 BIT12
371 #define RRSR_MCS1 BIT13
372 #define RRSR_MCS2 BIT14
373 #define RRSR_MCS3 BIT15
374 #define RRSR_MCS4 BIT16
375 #define RRSR_MCS5 BIT17
376 #define RRSR_MCS6 BIT18
377 #define RRSR_MCS7 BIT19
378 #define BRSR_ACKSHORTPMB BIT23
379
380
381
382
383
384 #define RATR_1M 0x00000001
385 #define RATR_2M 0x00000002
386 #define RATR_55M 0x00000004
387 #define RATR_11M 0x00000008
388
389 #define RATR_6M 0x00000010
390 #define RATR_9M 0x00000020
391 #define RATR_12M 0x00000040
392 #define RATR_18M 0x00000080
393 #define RATR_24M 0x00000100
394 #define RATR_36M 0x00000200
395 #define RATR_48M 0x00000400
396 #define RATR_54M 0x00000800
397
398 #define RATR_MCS0 0x00001000
399 #define RATR_MCS1 0x00002000
400 #define RATR_MCS2 0x00004000
401 #define RATR_MCS3 0x00008000
402 #define RATR_MCS4 0x00010000
403 #define RATR_MCS5 0x00020000
404 #define RATR_MCS6 0x00040000
405 #define RATR_MCS7 0x00080000
406
407 #define RATR_MCS8 0x00100000
408 #define RATR_MCS9 0x00200000
409 #define RATR_MCS10 0x00400000
410 #define RATR_MCS11 0x00800000
411 #define RATR_MCS12 0x01000000
412 #define RATR_MCS13 0x02000000
413 #define RATR_MCS14 0x04000000
414 #define RATR_MCS15 0x08000000
415
416
417 #define RATE_1M BIT(0)
418 #define RATE_2M BIT(1)
419 #define RATE_5_5M BIT(2)
420 #define RATE_11M BIT(3)
421
422 #define RATE_6M BIT(4)
423 #define RATE_9M BIT(5)
424 #define RATE_12M BIT(6)
425 #define RATE_18M BIT(7)
426 #define RATE_24M BIT(8)
427 #define RATE_36M BIT(9)
428 #define RATE_48M BIT(10)
429 #define RATE_54M BIT(11)
430
431 #define RATE_MCS0 BIT(12)
432 #define RATE_MCS1 BIT(13)
433 #define RATE_MCS2 BIT(14)
434 #define RATE_MCS3 BIT(15)
435 #define RATE_MCS4 BIT(16)
436 #define RATE_MCS5 BIT(17)
437 #define RATE_MCS6 BIT(18)
438 #define RATE_MCS7 BIT(19)
439
440 #define RATE_MCS8 BIT(20)
441 #define RATE_MCS9 BIT(21)
442 #define RATE_MCS10 BIT(22)
443 #define RATE_MCS11 BIT(23)
444 #define RATE_MCS12 BIT(24)
445 #define RATE_MCS13 BIT(25)
446 #define RATE_MCS14 BIT(26)
447 #define RATE_MCS15 BIT(27)
448
449
450 #define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | \
451 RATR_11M)
452 #define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | \
453 RATR_18M | RATR_24M | \
454 RATR_36M | RATR_48M | RATR_54M)
455 #define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | \
456 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 | \
457 RATR_MCS6 | RATR_MCS7)
458 #define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | \
459 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 | \
460 RATR_MCS14 | RATR_MCS15)
461
462
463
464
465 #define BW_OPMODE_20MHZ BIT(2)
466 #define BW_OPMODE_5G BIT(1)
467 #define BW_OPMODE_11J BIT(0)
468
469
470
471
472
473 #define CAM_VALID BIT(15)
474 #define CAM_NOTVALID 0x0000
475 #define CAM_USEDK BIT(5)
476
477 #define CAM_NONE 0x0
478 #define CAM_WEP40 0x01
479 #define CAM_TKIP 0x02
480 #define CAM_AES 0x04
481 #define CAM_WEP104 0x05
482 #define CAM_SMS4 0x6
483
484
485 #define TOTAL_CAM_ENTRY 32
486 #define HALF_CAM_ENTRY 16
487
488 #define CAM_WRITE BIT(16)
489 #define CAM_READ 0x00000000
490 #define CAM_POLLINIG BIT(31)
491
492
493 #define WOW_PMEN BIT0
494 #define WOW_WOMEN BIT1
495 #define WOW_MAGIC BIT2
496 #define WOW_UWF BIT3
497
498
499
500
501
502 #define IMR8190_DISABLED 0x0
503 #define IMR_BCNDMAINT6 BIT(31)
504 #define IMR_BCNDMAINT5 BIT(30)
505 #define IMR_BCNDMAINT4 BIT(29)
506 #define IMR_BCNDMAINT3 BIT(28)
507 #define IMR_BCNDMAINT2 BIT(27)
508 #define IMR_BCNDMAINT1 BIT(26)
509 #define IMR_BCNDOK8 BIT(25)
510 #define IMR_BCNDOK7 BIT(24)
511 #define IMR_BCNDOK6 BIT(23)
512 #define IMR_BCNDOK5 BIT(22)
513 #define IMR_BCNDOK4 BIT(21)
514 #define IMR_BCNDOK3 BIT(20)
515 #define IMR_BCNDOK2 BIT(19)
516 #define IMR_BCNDOK1 BIT(18)
517 #define IMR_TIMEOUT2 BIT(17)
518 #define IMR_TIMEOUT1 BIT(16)
519 #define IMR_TXFOVW BIT(15)
520 #define IMR_PSTIMEOUT BIT(14)
521 #define IMR_BCNINT BIT(13)
522 #define IMR_RXFOVW BIT(12)
523 #define IMR_RDU BIT(11)
524 #define IMR_ATIMEND BIT(10)
525 #define IMR_BDOK BIT(9)
526 #define IMR_HIGHDOK BIT(8)
527 #define IMR_TBDOK BIT(7)
528 #define IMR_MGNTDOK BIT(6)
529 #define IMR_TBDER BIT(5)
530 #define IMR_BKDOK BIT(4)
531 #define IMR_BEDOK BIT(3)
532 #define IMR_VIDOK BIT(2)
533 #define IMR_VODOK BIT(1)
534 #define IMR_ROK BIT(0)
535
536 #define IMR_TXERR BIT(11)
537 #define IMR_RXERR BIT(10)
538 #define IMR_C2HCMD BIT(9)
539 #define IMR_CPWM BIT(8)
540 #define IMR_OCPINT BIT(1)
541 #define IMR_WLANOFF BIT(0)
542
543
544
545
546 #define HWSET_MAX_SIZE 256
547 #define EFUSE_MAX_SECTION 32
548 #define EFUSE_REAL_CONTENT_LEN 512
549
550
551
552
553 #define EEPROM_DEFAULT_TSSI 0x0
554 #define EEPROM_DEFAULT_CRYSTALCAP 0x0
555 #define EEPROM_DEFAULT_THERMALMETER 0x12
556
557 #define EEPROM_DEFAULT_TXPOWERLEVEL_2G 0x2C
558 #define EEPROM_DEFAULT_TXPOWERLEVEL_5G 0x22
559
560 #define EEPROM_DEFAULT_HT40_2SDIFF 0x0
561
562 #define EEPROM_DEFAULT_HT20_DIFF 2
563
564 #define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x4
565 #define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0
566 #define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0
567
568 #define EEPROM_CHANNEL_PLAN_FCC 0x0
569 #define EEPROM_CHANNEL_PLAN_IC 0x1
570 #define EEPROM_CHANNEL_PLAN_ETSI 0x2
571 #define EEPROM_CHANNEL_PLAN_SPAIN 0x3
572 #define EEPROM_CHANNEL_PLAN_FRANCE 0x4
573 #define EEPROM_CHANNEL_PLAN_MKK 0x5
574 #define EEPROM_CHANNEL_PLAN_MKK1 0x6
575 #define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
576 #define EEPROM_CHANNEL_PLAN_TELEC 0x8
577 #define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
578 #define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
579 #define EEPROM_CHANNEL_PLAN_NCC 0xB
580 #define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
581
582 #define EEPROM_CID_DEFAULT 0x0
583 #define EEPROM_CID_TOSHIBA 0x4
584 #define EEPROM_CID_CCX 0x10
585 #define EEPROM_CID_QMI 0x0D
586 #define EEPROM_CID_WHQL 0xFE
587
588
589 #define RTL8192_EEPROM_ID 0x8129
590 #define EEPROM_WAPI_SUPPORT 0x78
591
592
593 #define RTL8190_EEPROM_ID 0x8129
594 #define EEPROM_HPON 0x02
595 #define EEPROM_CLK 0x06
596 #define EEPROM_MAC_FUNCTION 0x08
597
598 #define EEPROM_VID 0x28
599 #define EEPROM_DID 0x2A
600 #define EEPROM_SVID 0x2C
601 #define EEPROM_SMID 0x2E
602
603 #define EEPROM_MAC_ADDR 0x16
604 #define EEPROM_MAC_ADDR_MAC0_92D 0x55
605 #define EEPROM_MAC_ADDR_MAC1_92D 0x5B
606
607
608 #define EEPROM_CCK_TX_PWR_INX_2G 0x61
609 #define EEPROM_HT40_1S_TX_PWR_INX_2G 0x67
610 #define EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G 0x6D
611 #define EEPROM_HT20_TX_PWR_INX_DIFF_2G 0x70
612 #define EEPROM_OFDM_TX_PWR_INX_DIFF_2G 0x73
613 #define EEPROM_HT40_MAX_PWR_OFFSET_2G 0x76
614 #define EEPROM_HT20_MAX_PWR_OFFSET_2G 0x79
615
616
617 #define EEPROM_HT40_1S_TX_PWR_INX_5GL 0x7C
618 #define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GL 0x82
619 #define EEPROM_HT20_TX_PWR_INX_DIFF_5GL 0x85
620 #define EEPROM_OFDM_TX_PWR_INX_DIFF_5GL 0x88
621 #define EEPROM_HT40_MAX_PWR_OFFSET_5GL 0x8B
622 #define EEPROM_HT20_MAX_PWR_OFFSET_5GL 0x8E
623
624
625 #define EEPROM_HT40_1S_TX_PWR_INX_5GM 0x91
626 #define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GM 0x97
627 #define EEPROM_HT20_TX_PWR_INX_DIFF_5GM 0x9A
628 #define EEPROM_OFDM_TX_PWR_INX_DIFF_5GM 0x9D
629 #define EEPROM_HT40_MAX_PWR_OFFSET_5GM 0xA0
630 #define EEPROM_HT20_MAX_PWR_OFFSET_5GM 0xA3
631
632
633 #define EEPROM_HT40_1S_TX_PWR_INX_5GH 0xA6
634 #define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GH 0xAC
635 #define EEPROM_HT20_TX_PWR_INX_DIFF_5GH 0xAF
636 #define EEPROM_OFDM_TX_PWR_INX_DIFF_5GH 0xB2
637 #define EEPROM_HT40_MAX_PWR_OFFSET_5GH 0xB5
638 #define EEPROM_HT20_MAX_PWR_OFFSET_5GH 0xB8
639
640
641 #define EEPROM_CHANNEL_PLAN 0xBB
642 #define EEPROM_IQK_DELTA 0xBC
643 #define EEPROM_LCK_DELTA 0xBC
644 #define EEPROM_XTAL_K 0xBD
645 #define EEPROM_TSSI_A_5G 0xBE
646 #define EEPROM_TSSI_B_5G 0xBF
647 #define EEPROM_TSSI_AB_5G 0xC0
648 #define EEPROM_THERMAL_METER 0xC3
649 #define EEPROM_RF_OPT1 0xC4
650 #define EEPROM_RF_OPT2 0xC5
651 #define EEPROM_RF_OPT3 0xC6
652 #define EEPROM_RF_OPT4 0xC7
653 #define EEPROM_RF_OPT5 0xC8
654 #define EEPROM_RF_OPT6 0xC9
655 #define EEPROM_VERSION 0xCA
656 #define EEPROM_CUSTOMER_ID 0xCB
657 #define EEPROM_RF_OPT7 0xCC
658
659 #define EEPROM_DEF_PART_NO 0x3FD
660 #define EEPROME_CHIP_VERSION_L 0x3FF
661 #define EEPROME_CHIP_VERSION_H 0x3FE
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679 #define RCR_APPFCS BIT(31)
680 #define RCR_APP_MIC BIT(30)
681 #define RCR_APP_ICV BIT(29)
682 #define RCR_APP_PHYST_RXFF BIT(28)
683 #define RCR_APP_BA_SSN BIT(27)
684 #define RCR_ENMBID BIT(24)
685 #define RCR_LSIGEN BIT(23)
686 #define RCR_MFBEN BIT(22)
687 #define RCR_HTC_LOC_CTRL BIT(14)
688 #define RCR_AMF BIT(13)
689 #define RCR_ACF BIT(12)
690 #define RCR_ADF BIT(11)
691 #define RCR_AICV BIT(9)
692 #define RCR_ACRC32 BIT(8)
693 #define RCR_CBSSID_BCN BIT(7)
694 #define RCR_CBSSID_DATA BIT(6)
695 #define RCR_APWRMGT BIT(5)
696 #define RCR_ADD3 BIT(4)
697 #define RCR_AB BIT(3)
698 #define RCR_AM BIT(2)
699 #define RCR_APM BIT(1)
700 #define RCR_AAP BIT(0)
701 #define RCR_MXDMA_OFFSET 8
702 #define RCR_FIFO_OFFSET 13
703
704
705
706
707
708
709
710
711
712 #define SW18_FPWM BIT(3)
713
714
715
716 #define ISO_MD2PP BIT(0)
717 #define ISO_UA2USB BIT(1)
718 #define ISO_UD2CORE BIT(2)
719 #define ISO_PA2PCIE BIT(3)
720 #define ISO_PD2CORE BIT(4)
721 #define ISO_IP2MAC BIT(5)
722 #define ISO_DIOP BIT(6)
723 #define ISO_DIOE BIT(7)
724 #define ISO_EB2CORE BIT(8)
725 #define ISO_DIOR BIT(9)
726
727 #define PWC_EV25V BIT(14)
728 #define PWC_EV12V BIT(15)
729
730
731
732 #define FEN_BBRSTB BIT(0)
733 #define FEN_BB_GLB_RSTN BIT(1)
734 #define FEN_USBA BIT(2)
735 #define FEN_UPLL BIT(3)
736 #define FEN_USBD BIT(4)
737 #define FEN_DIO_PCIE BIT(5)
738 #define FEN_PCIEA BIT(6)
739 #define FEN_PPLL BIT(7)
740 #define FEN_PCIED BIT(8)
741 #define FEN_DIOE BIT(9)
742 #define FEN_CPUEN BIT(10)
743 #define FEN_DCORE BIT(11)
744 #define FEN_ELDR BIT(12)
745 #define FEN_DIO_RF BIT(13)
746 #define FEN_HWPDN BIT(14)
747 #define FEN_MREGEN BIT(15)
748
749
750 #define PFM_LDALL BIT(0)
751 #define PFM_ALDN BIT(1)
752 #define PFM_LDKP BIT(2)
753 #define PFM_WOWL BIT(3)
754 #define ENPDN BIT(4)
755 #define PDN_PL BIT(5)
756 #define APFM_ONMAC BIT(8)
757 #define APFM_OFF BIT(9)
758 #define APFM_RSM BIT(10)
759 #define AFSM_HSUS BIT(11)
760 #define AFSM_PCIE BIT(12)
761 #define APDM_MAC BIT(13)
762 #define APDM_HOST BIT(14)
763 #define APDM_HPDN BIT(15)
764 #define RDY_MACON BIT(16)
765 #define SUS_HOST BIT(17)
766 #define ROP_ALD BIT(20)
767 #define ROP_PWR BIT(21)
768 #define ROP_SPS BIT(22)
769 #define SOP_MRST BIT(25)
770 #define SOP_FUSE BIT(26)
771 #define SOP_ABG BIT(27)
772 #define SOP_AMB BIT(28)
773 #define SOP_RCK BIT(29)
774 #define SOP_A8M BIT(30)
775 #define XOP_BTCK BIT(31)
776
777
778 #define ANAD16V_EN BIT(0)
779 #define ANA8M BIT(1)
780 #define MACSLP BIT(4)
781 #define LOADER_CLK_EN BIT(5)
782 #define _80M_SSC_DIS BIT(7)
783 #define _80M_SSC_EN_HO BIT(8)
784 #define PHY_SSC_RSTB BIT(9)
785 #define SEC_CLK_EN BIT(10)
786 #define MAC_CLK_EN BIT(11)
787 #define SYS_CLK_EN BIT(12)
788 #define RING_CLK_EN BIT(13)
789
790
791
792 #define BOOT_FROM_EEPROM BIT(4)
793 #define EEPROM_EN BIT(5)
794
795
796 #define AFE_BGEN BIT(0)
797 #define AFE_MBEN BIT(1)
798 #define MAC_ID_EN BIT(7)
799
800
801 #define WLOCK_ALL BIT(0)
802 #define WLOCK_00 BIT(1)
803 #define WLOCK_04 BIT(2)
804 #define WLOCK_08 BIT(3)
805 #define WLOCK_40 BIT(4)
806 #define R_DIS_PRST_0 BIT(5)
807 #define R_DIS_PRST_1 BIT(6)
808 #define LOCK_ALL_EN BIT(7)
809
810
811 #define RF_EN BIT(0)
812 #define RF_RSTB BIT(1)
813 #define RF_SDMRSTB BIT(2)
814
815
816
817
818 #define LDA15_EN BIT(0)
819 #define LDA15_STBY BIT(1)
820 #define LDA15_OBUF BIT(2)
821 #define LDA15_REG_VOS BIT(3)
822 #define _LDA15_VOADJ(x) (((x) & 0x7) << 4)
823
824
825
826
827 #define LDV12_EN BIT(0)
828 #define LDV12_SDBY BIT(1)
829 #define LPLDO_HSM BIT(2)
830 #define LPLDO_LSM_DIS BIT(3)
831 #define _LDV12_VADJ(x) (((x) & 0xF) << 4)
832
833
834
835 #define XTAL_EN BIT(0)
836 #define XTAL_BSEL BIT(1)
837 #define _XTAL_BOSC(x) (((x) & 0x3) << 2)
838 #define _XTAL_CADJ(x) (((x) & 0xF) << 4)
839 #define XTAL_GATE_USB BIT(8)
840 #define _XTAL_USB_DRV(x) (((x) & 0x3) << 9)
841 #define XTAL_GATE_AFE BIT(11)
842 #define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12)
843 #define XTAL_RF_GATE BIT(14)
844 #define _XTAL_RF_DRV(x) (((x) & 0x3) << 15)
845 #define XTAL_GATE_DIG BIT(17)
846 #define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18)
847 #define XTAL_BT_GATE BIT(20)
848 #define _XTAL_BT_DRV(x) (((x) & 0x3) << 21)
849 #define _XTAL_GPIO(x) (((x) & 0x7) << 23)
850
851
852 #define CKDLY_AFE BIT(26)
853 #define CKDLY_USB BIT(27)
854 #define CKDLY_DIG BIT(28)
855 #define CKDLY_BT BIT(29)
856
857
858
859 #define APLL_EN BIT(0)
860 #define APLL_320_EN BIT(1)
861 #define APLL_FREF_SEL BIT(2)
862 #define APLL_EDGE_SEL BIT(3)
863 #define APLL_WDOGB BIT(4)
864 #define APLL_LPFEN BIT(5)
865
866 #define APLL_REF_CLK_13MHZ 0x1
867 #define APLL_REF_CLK_19_2MHZ 0x2
868 #define APLL_REF_CLK_20MHZ 0x3
869 #define APLL_REF_CLK_25MHZ 0x4
870 #define APLL_REF_CLK_26MHZ 0x5
871 #define APLL_REF_CLK_38_4MHZ 0x6
872 #define APLL_REF_CLK_40MHZ 0x7
873
874 #define APLL_320EN BIT(14)
875 #define APLL_80EN BIT(15)
876 #define APLL_1MEN BIT(24)
877
878
879
880 #define ALD_EN BIT(18)
881 #define EF_PD BIT(19)
882 #define EF_FLAG BIT(31)
883
884
885 #define EF_TRPT BIT(7)
886 #define LDOE25_EN BIT(31)
887
888
889 #define MCUFWDL_EN BIT(0)
890 #define MCUFWDL_RDY BIT(1)
891 #define FWDL_CHKSUM_RPT BIT(2)
892 #define MACINI_RDY BIT(3)
893 #define BBINI_RDY BIT(4)
894 #define RFINI_RDY BIT(5)
895 #define WINTINI_RDY BIT(6)
896 #define MAC1_WINTINI_RDY BIT(11)
897 #define CPRST BIT(23)
898
899
900 #define XCLK_VLD BIT(0)
901 #define ACLK_VLD BIT(1)
902 #define UCLK_VLD BIT(2)
903 #define PCLK_VLD BIT(3)
904 #define PCIRSTB BIT(4)
905 #define V15_VLD BIT(5)
906 #define TRP_B15V_EN BIT(7)
907 #define SIC_IDLE BIT(8)
908 #define BD_MAC2 BIT(9)
909 #define BD_MAC1 BIT(10)
910 #define IC_MACPHY_MODE BIT(11)
911 #define PAD_HWPD_IDN BIT(22)
912 #define TRP_VAUX_EN BIT(23)
913 #define TRP_BT_EN BIT(24)
914 #define BD_PKG_SEL BIT(25)
915 #define BD_HCI_SEL BIT(26)
916 #define TYPE_ID BIT(27)
917
918
919 #define _LLT_NO_ACTIVE 0x0
920 #define _LLT_WRITE_ACCESS 0x1
921 #define _LLT_READ_ACCESS 0x2
922
923 #define _LLT_INIT_DATA(x) ((x) & 0xFF)
924 #define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8)
925 #define _LLT_OP(x) (((x) & 0x3) << 30)
926 #define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3)
927
928
929
930
931
932 #define RETRY_LIMIT_SHORT_SHIFT 8
933 #define RETRY_LIMIT_LONG_SHIFT 0
934
935
936
937
938
939
940 #define AC_PARAM_TXOP_LIMIT_OFFSET 16
941 #define AC_PARAM_ECW_MAX_OFFSET 12
942 #define AC_PARAM_ECW_MIN_OFFSET 8
943 #define AC_PARAM_AIFS_OFFSET 0
944
945
946 #define ACMHW_HWEN BIT(0)
947 #define ACMHW_BEQEN BIT(1)
948 #define ACMHW_VIQEN BIT(2)
949 #define ACMHW_VOQEN BIT(3)
950
951
952
953
954
955
956 #define TSFRST BIT(0)
957 #define DIS_GCLK BIT(1)
958 #define PAD_SEL BIT(2)
959 #define PWR_ST BIT(6)
960 #define PWRBIT_OW_EN BIT(7)
961 #define ACRC BIT(8)
962 #define CFENDFORM BIT(9)
963 #define ICV BIT(10)
964
965
966 #define SCR_TXUSEDK BIT(0)
967 #define SCR_RXUSEDK BIT(1)
968 #define SCR_TXENCENABLE BIT(2)
969 #define SCR_RXENCENABLE BIT(3)
970 #define SCR_SKBYA2 BIT(4)
971 #define SCR_NOSKMC BIT(5)
972 #define SCR_TXBCUSEDK BIT(6)
973 #define SCR_RXBCUSEDK BIT(7)
974
975
976 #define LAST_ENTRY_OF_TX_PKT_BUFFER 255
977 #define LAST_ENTRY_OF_TX_PKT_BUFFER_DUAL_MAC 127
978
979 #define POLLING_LLT_THRESHOLD 20
980 #define POLLING_READY_TIMEOUT_COUNT 1000
981
982
983 #define MAX_MSS_DENSITY_2T 0x13
984 #define MAX_MSS_DENSITY_1T 0x0A
985
986
987
988
989
990
991
992
993
994
995
996 #define RFPGA0_RFMOD 0x800
997
998 #define RFPGA0_TXINFO 0x804
999 #define RFPGA0_PSDFUNCTION 0x808
1000
1001 #define RFPGA0_TXGAINSTAGE 0x80c
1002
1003 #define RFPGA0_RFTIMING1 0x810
1004 #define RFPGA0_RFTIMING2 0x814
1005
1006 #define RFPGA0_XA_HSSIPARAMETER1 0x820
1007 #define RFPGA0_XA_HSSIPARAMETER2 0x824
1008 #define RFPGA0_XB_HSSIPARAMETER1 0x828
1009 #define RFPGA0_XB_HSSIPARAMETER2 0x82c
1010
1011 #define RFPGA0_XA_LSSIPARAMETER 0x840
1012 #define RFPGA0_XB_LSSIPARAMETER 0x844
1013
1014 #define RFPGA0_RFWAKEUPPARAMETER 0x850
1015 #define RFPGA0_RFSLEEPUPPARAMETER 0x854
1016
1017 #define RFPGA0_XAB_SWITCHCONTROL 0x858
1018 #define RFPGA0_XCD_SWITCHCONTROL 0x85c
1019
1020 #define RFPGA0_XA_RFINTERFACEOE 0x860
1021 #define RFPGA0_XB_RFINTERFACEOE 0x864
1022
1023 #define RFPGA0_XAB_RFINTERFACESW 0x870
1024 #define RFPGA0_XCD_RFINTERFACESW 0x874
1025
1026 #define RFPGA0_XAB_RFPARAMETER 0x878
1027 #define RFPGA0_XCD_RFPARAMETER 0x87c
1028
1029 #define RFPGA0_ANALOGPARAMETER1 0x880
1030 #define RFPGA0_ANALOGPARAMETER2 0x884
1031 #define RFPGA0_ANALOGPARAMETER3 0x888
1032 #define RFPGA0_ADDALLOCKEN 0x888
1033 #define RFPGA0_ANALOGPARAMETER4 0x88c
1034
1035 #define RFPGA0_XA_LSSIREADBACK 0x8a0
1036 #define RFPGA0_XB_LSSIREADBACK 0x8a4
1037 #define RFPGA0_XC_LSSIREADBACK 0x8a8
1038 #define RFPGA0_XD_LSSIREADBACK 0x8ac
1039
1040 #define RFPGA0_PSDREPORT 0x8b4
1041 #define TRANSCEIVERA_HSPI_READBACK 0x8b8
1042 #define TRANSCEIVERB_HSPI_READBACK 0x8bc
1043 #define RFPGA0_XAB_RFINTERFACERB 0x8e0
1044 #define RFPGA0_XCD_RFINTERFACERB 0x8e4
1045
1046
1047 #define RFPGA1_RFMOD 0x900
1048
1049 #define RFPGA1_TXBLOCK 0x904
1050 #define RFPGA1_DEBUGSELECT 0x908
1051 #define RFPGA1_TXINFO 0x90c
1052
1053
1054 #define RCCK0_SYSTEM 0xa00
1055
1056 #define RCCK0_AFESSTTING 0xa04
1057 #define RCCK0_CCA 0xa08
1058
1059 #define RCCK0_RXAGC1 0xa0c
1060 #define RCCK0_RXAGC2 0xa10
1061
1062 #define RCCK0_RXHP 0xa14
1063
1064 #define RCCK0_DSPPARAMETER1 0xa18
1065 #define RCCK0_DSPPARAMETER2 0xa1c
1066
1067 #define RCCK0_TXFILTER1 0xa20
1068 #define RCCK0_TXFILTER2 0xa24
1069 #define RCCK0_DEBUGPORT 0xa28
1070 #define RCCK0_FALSEALARMREPORT 0xa2c
1071 #define RCCK0_TRSSIREPORT 0xa50
1072 #define RCCK0_RXREPORT 0xa54
1073 #define RCCK0_FACOUNTERLOWER 0xa5c
1074 #define RCCK0_FACOUNTERUPPER 0xa58
1075
1076
1077 #define ROFDM0_LSTF 0xc00
1078
1079 #define ROFDM0_TRXPATHENABLE 0xc04
1080 #define ROFDM0_TRMUXPAR 0xc08
1081 #define ROFDM0_TRSWISOLATION 0xc0c
1082
1083 #define ROFDM0_XARXAFE 0xc10
1084 #define ROFDM0_XARXIQIMBALANCE 0xc14
1085 #define ROFDM0_XBRXAFE 0xc18
1086 #define ROFDM0_XBRXIQIMBALANCE 0xc1c
1087 #define ROFDM0_XCRXAFE 0xc20
1088 #define ROFDM0_XCRXIQIMBALANCE 0xc24
1089 #define ROFDM0_XDRXAFE 0xc28
1090 #define ROFDM0_XDRXIQIMBALANCE 0xc2c
1091
1092 #define ROFDM0_RXDETECTOR1 0xc30
1093 #define ROFDM0_RXDETECTOR2 0xc34
1094 #define ROFDM0_RXDETECTOR3 0xc38
1095 #define ROFDM0_RXDETECTOR4 0xc3c
1096
1097 #define ROFDM0_RXDSP 0xc40
1098 #define ROFDM0_CFOANDDAGC 0xc44
1099 #define ROFDM0_CCADROPTHRESHOLD 0xc48
1100 #define ROFDM0_ECCATHRESHOLD 0xc4c
1101
1102 #define ROFDM0_XAAGCCORE1 0xc50
1103 #define ROFDM0_XAAGCCORE2 0xc54
1104 #define ROFDM0_XBAGCCORE1 0xc58
1105 #define ROFDM0_XBAGCCORE2 0xc5c
1106 #define ROFDM0_XCAGCCORE1 0xc60
1107 #define ROFDM0_XCAGCCORE2 0xc64
1108 #define ROFDM0_XDAGCCORE1 0xc68
1109 #define ROFDM0_XDAGCCORE2 0xc6c
1110
1111 #define ROFDM0_AGCPARAMETER1 0xc70
1112 #define ROFDM0_AGCPARAMETER2 0xc74
1113 #define ROFDM0_AGCRSSITABLE 0xc78
1114 #define ROFDM0_HTSTFAGC 0xc7c
1115
1116 #define ROFDM0_XATXIQIMBALANCE 0xc80
1117 #define ROFDM0_XATXAFE 0xc84
1118 #define ROFDM0_XBTXIQIMBALANCE 0xc88
1119 #define ROFDM0_XBTXAFE 0xc8c
1120 #define ROFDM0_XCTXIQIMBALANCE 0xc90
1121 #define ROFDM0_XCTXAFE 0xc94
1122 #define ROFDM0_XDTXIQIMBALANCE 0xc98
1123 #define ROFDM0_XDTXAFE 0xc9c
1124
1125 #define ROFDM0_RXHPPARAMETER 0xce0
1126 #define ROFDM0_TXPSEUDONOISEWGT 0xce4
1127 #define ROFDM0_FRAMESYNC 0xcf0
1128 #define ROFDM0_DFSREPORT 0xcf4
1129 #define ROFDM0_TXCOEFF1 0xca4
1130 #define ROFDM0_TXCOEFF2 0xca8
1131 #define ROFDM0_TXCOEFF3 0xcac
1132 #define ROFDM0_TXCOEFF4 0xcb0
1133 #define ROFDM0_TXCOEFF5 0xcb4
1134 #define ROFDM0_TXCOEFF6 0xcb8
1135
1136
1137 #define ROFDM1_LSTF 0xd00
1138 #define ROFDM1_TRXPATHENABLE 0xd04
1139
1140 #define ROFDM1_CFO 0xd08
1141 #define ROFDM1_CSI1 0xd10
1142 #define ROFDM1_SBD 0xd14
1143 #define ROFDM1_CSI2 0xd18
1144 #define ROFDM1_CFOTRACKING 0xd2c
1145 #define ROFDM1_TRXMESAURE1 0xd34
1146 #define ROFDM1_INTFDET 0xd3c
1147 #define ROFDM1_PSEUDONOISESTATEAB 0xd50
1148 #define ROFDM1_PSEUDONOISESTATECD 0xd54
1149 #define ROFDM1_RXPSEUDONOISEWGT 0xd58
1150
1151 #define ROFDM_PHYCOUNTER1 0xda0
1152 #define ROFDM_PHYCOUNTER2 0xda4
1153 #define ROFDM_PHYCOUNTER3 0xda8
1154
1155 #define ROFDM_SHORTCFOAB 0xdac
1156 #define ROFDM_SHORTCFOCD 0xdb0
1157 #define ROFDM_LONGCFOAB 0xdb4
1158 #define ROFDM_LONGCFOCD 0xdb8
1159 #define ROFDM_TAILCFOAB 0xdbc
1160 #define ROFDM_TAILCFOCD 0xdc0
1161 #define ROFDM_PWMEASURE1 0xdc4
1162 #define ROFDM_PWMEASURE2 0xdc8
1163 #define ROFDM_BWREPORT 0xdcc
1164 #define ROFDM_AGCREPORT 0xdd0
1165 #define ROFDM_RXSNR 0xdd4
1166 #define ROFDM_RXEVMCSI 0xdd8
1167 #define ROFDM_SIGREPORT 0xddc
1168
1169
1170 #define RTXAGC_A_RATE18_06 0xe00
1171 #define RTXAGC_A_RATE54_24 0xe04
1172 #define RTXAGC_A_CCK1_MCS32 0xe08
1173 #define RTXAGC_A_MCS03_MCS00 0xe10
1174 #define RTXAGC_A_MCS07_MCS04 0xe14
1175 #define RTXAGC_A_MCS11_MCS08 0xe18
1176 #define RTXAGC_A_MCS15_MCS12 0xe1c
1177
1178 #define RTXAGC_B_RATE18_06 0x830
1179 #define RTXAGC_B_RATE54_24 0x834
1180 #define RTXAGC_B_CCK1_55_MCS32 0x838
1181 #define RTXAGC_B_MCS03_MCS00 0x83c
1182 #define RTXAGC_B_MCS07_MCS04 0x848
1183 #define RTXAGC_B_MCS11_MCS08 0x84c
1184 #define RTXAGC_B_MCS15_MCS12 0x868
1185 #define RTXAGC_B_CCK11_A_CCK2_11 0x86c
1186
1187
1188 #define RF_AC 0x00
1189
1190 #define RF_IQADJ_G1 0x01
1191 #define RF_IQADJ_G2 0x02
1192 #define RF_POW_TRSW 0x05
1193
1194 #define RF_GAIN_RX 0x06
1195 #define RF_GAIN_TX 0x07
1196
1197 #define RF_TXM_IDAC 0x08
1198 #define RF_BS_IQGEN 0x0F
1199
1200 #define RF_MODE1 0x10
1201 #define RF_MODE2 0x11
1202
1203 #define RF_RX_AGC_HP 0x12
1204 #define RF_TX_AGC 0x13
1205 #define RF_BIAS 0x14
1206 #define RF_IPA 0x15
1207 #define RF_POW_ABILITY 0x17
1208 #define RF_MODE_AG 0x18
1209 #define rfchannel 0x18
1210 #define RF_CHNLBW 0x18
1211 #define RF_TOP 0x19
1212
1213 #define RF_RX_G1 0x1A
1214 #define RF_RX_G2 0x1B
1215
1216 #define RF_RX_BB2 0x1C
1217 #define RF_RX_BB1 0x1D
1218
1219 #define RF_RCK1 0x1E
1220 #define RF_RCK2 0x1F
1221
1222 #define RF_TX_G1 0x20
1223 #define RF_TX_G2 0x21
1224 #define RF_TX_G3 0x22
1225
1226 #define RF_TX_BB1 0x23
1227
1228 #define RF_T_METER 0x42
1229
1230 #define RF_SYN_G1 0x25
1231 #define RF_SYN_G2 0x26
1232 #define RF_SYN_G3 0x27
1233 #define RF_SYN_G4 0x28
1234 #define RF_SYN_G5 0x29
1235 #define RF_SYN_G6 0x2A
1236 #define RF_SYN_G7 0x2B
1237 #define RF_SYN_G8 0x2C
1238
1239 #define RF_RCK_OS 0x30
1240
1241 #define RF_TXPA_G1 0x31
1242 #define RF_TXPA_G2 0x32
1243 #define RF_TXPA_G3 0x33
1244
1245
1246
1247
1248 #define BRFMOD 0x1
1249 #define BCCKTXSC 0x30
1250 #define BCCKEN 0x1000000
1251 #define BOFDMEN 0x2000000
1252
1253 #define B3WIREDATALENGTH 0x800
1254 #define B3WIREADDRESSLENGTH 0x400
1255
1256 #define BRFSI_RFENV 0x10
1257
1258 #define BLSSIREADADDRESS 0x7f800000
1259 #define BLSSIREADEDGE 0x80000000
1260 #define BLSSIREADBACKDATA 0xfffff
1261
1262 #define BCCKSIDEBAND 0x10
1263
1264
1265 #define BBYTE0 0x1
1266 #define BBYTE1 0x2
1267 #define BBYTE2 0x4
1268 #define BBYTE3 0x8
1269 #define BWORD0 0x3
1270 #define BWORD1 0xc
1271 #define BDWORD 0xf
1272
1273 #endif