root/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/sw.c

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DEFINITIONS

This source file includes following definitions.
  1. rtl8723e_init_aspm_vars
  2. rtl8723e_init_sw_vars
  3. rtl8723e_deinit_sw_vars
  4. rtl8723e_get_btc_status
  5. is_fw_header

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2009-2012  Realtek Corporation.*/
   3 
   4 #include "../wifi.h"
   5 #include "../core.h"
   6 #include "../pci.h"
   7 #include "reg.h"
   8 #include "def.h"
   9 #include "phy.h"
  10 #include "dm.h"
  11 #include "fw.h"
  12 #include "../rtl8723com/fw_common.h"
  13 #include "hw.h"
  14 #include "sw.h"
  15 #include "trx.h"
  16 #include "led.h"
  17 #include "table.h"
  18 #include "hal_btc.h"
  19 #include "../btcoexist/rtl_btc.h"
  20 #include "../rtl8723com/phy_common.h"
  21 
  22 #include <linux/vmalloc.h>
  23 #include <linux/module.h>
  24 
  25 static void rtl8723e_init_aspm_vars(struct ieee80211_hw *hw)
  26 {
  27         struct rtl_priv *rtlpriv = rtl_priv(hw);
  28         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  29 
  30         /*close ASPM for AMD defaultly */
  31         rtlpci->const_amdpci_aspm = 0;
  32 
  33         /**
  34          * ASPM PS mode.
  35          * 0 - Disable ASPM,
  36          * 1 - Enable ASPM without Clock Req,
  37          * 2 - Enable ASPM with Clock Req,
  38          * 3 - Alwyas Enable ASPM with Clock Req,
  39          * 4 - Always Enable ASPM without Clock Req.
  40          * set defult to RTL8192CE:3 RTL8192E:2
  41          */
  42         rtlpci->const_pci_aspm = 3;
  43 
  44         /*Setting for PCI-E device */
  45         rtlpci->const_devicepci_aspm_setting = 0x03;
  46 
  47         /*Setting for PCI-E bridge */
  48         rtlpci->const_hostpci_aspm_setting = 0x02;
  49 
  50         /**
  51          * In Hw/Sw Radio Off situation.
  52          * 0 - Default,
  53          * 1 - From ASPM setting without low Mac Pwr,
  54          * 2 - From ASPM setting with low Mac Pwr,
  55          * 3 - Bus D3
  56          * set default to RTL8192CE:0 RTL8192SE:2
  57          */
  58         rtlpci->const_hwsw_rfoff_d3 = 0;
  59 
  60         /**
  61          * This setting works for those device with
  62          * backdoor ASPM setting such as EPHY setting.
  63          * 0 - Not support ASPM,
  64          * 1 - Support ASPM,
  65          * 2 - According to chipset.
  66          */
  67         rtlpci->const_support_pciaspm = rtlpriv->cfg->mod_params->aspm_support;
  68 }
  69 
  70 int rtl8723e_init_sw_vars(struct ieee80211_hw *hw)
  71 {
  72         struct rtl_priv *rtlpriv = rtl_priv(hw);
  73         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  74         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  75         int err = 0;
  76         char *fw_name = "rtlwifi/rtl8723fw.bin";
  77 
  78         rtl8723e_bt_reg_init(hw);
  79 
  80         rtlpriv->btcoexist.btc_ops = rtl_btc_get_ops_pointer();
  81 
  82         rtlpriv->dm.dm_initialgain_enable = 1;
  83         rtlpriv->dm.dm_flag = 0;
  84         rtlpriv->dm.disable_framebursting = 0;
  85         rtlpriv->dm.thermalvalue = 0;
  86         rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13);
  87 
  88         /* compatible 5G band 88ce just 2.4G band & smsp */
  89         rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
  90         rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
  91         rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
  92 
  93         rtlpci->receive_config = (RCR_APPFCS |
  94                                   RCR_APP_MIC |
  95                                   RCR_APP_ICV |
  96                                   RCR_APP_PHYST_RXFF |
  97                                   RCR_HTC_LOC_CTRL |
  98                                   RCR_AMF |
  99                                   RCR_ACF |
 100                                   RCR_ADF |
 101                                   RCR_AICV |
 102                                   RCR_AB |
 103                                   RCR_AM |
 104                                   RCR_APM |
 105                                   0);
 106 
 107         rtlpci->irq_mask[0] =
 108             (u32) (PHIMR_ROK |
 109                    PHIMR_RDU |
 110                    PHIMR_VODOK |
 111                    PHIMR_VIDOK |
 112                    PHIMR_BEDOK |
 113                    PHIMR_BKDOK |
 114                    PHIMR_MGNTDOK |
 115                    PHIMR_HIGHDOK |
 116                    PHIMR_C2HCMD |
 117                    PHIMR_HISRE_IND |
 118                    PHIMR_TSF_BIT32_TOGGLE |
 119                    PHIMR_TXBCNOK |
 120                    PHIMR_PSTIMEOUT |
 121                    0);
 122 
 123         rtlpci->irq_mask[1]     =
 124                  (u32)(PHIMR_RXFOVW |
 125                                 0);
 126 
 127         /* for LPS & IPS */
 128         rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
 129         rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
 130         rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
 131         rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
 132         if (rtlpriv->cfg->mod_params->disable_watchdog)
 133                 pr_info("watchdog disabled\n");
 134         rtlpriv->psc.reg_fwctrl_lps = 3;
 135         rtlpriv->psc.reg_max_lps_awakeintvl = 5;
 136         rtl8723e_init_aspm_vars(hw);
 137 
 138         if (rtlpriv->psc.reg_fwctrl_lps == 1)
 139                 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
 140         else if (rtlpriv->psc.reg_fwctrl_lps == 2)
 141                 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
 142         else if (rtlpriv->psc.reg_fwctrl_lps == 3)
 143                 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
 144 
 145         /* for firmware buf */
 146         rtlpriv->rtlhal.pfirmware = vzalloc(0x6000);
 147         if (!rtlpriv->rtlhal.pfirmware) {
 148                 pr_err("Can't alloc buffer for fw.\n");
 149                 return 1;
 150         }
 151 
 152         if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version))
 153                 fw_name = "rtlwifi/rtl8723fw_B.bin";
 154 
 155         rtlpriv->max_fw_size = 0x6000;
 156         pr_info("Using firmware %s\n", fw_name);
 157         err = request_firmware_nowait(THIS_MODULE, 1, fw_name,
 158                                       rtlpriv->io.dev, GFP_KERNEL, hw,
 159                                       rtl_fw_cb);
 160         if (err) {
 161                 pr_err("Failed to request firmware!\n");
 162                 vfree(rtlpriv->rtlhal.pfirmware);
 163                 rtlpriv->rtlhal.pfirmware = NULL;
 164                 return 1;
 165         }
 166         return 0;
 167 }
 168 
 169 void rtl8723e_deinit_sw_vars(struct ieee80211_hw *hw)
 170 {
 171         struct rtl_priv *rtlpriv = rtl_priv(hw);
 172 
 173         if (rtlpriv->rtlhal.pfirmware) {
 174                 vfree(rtlpriv->rtlhal.pfirmware);
 175                 rtlpriv->rtlhal.pfirmware = NULL;
 176         }
 177 }
 178 
 179 /* get bt coexist status */
 180 bool rtl8723e_get_btc_status(void)
 181 {
 182         return true;
 183 }
 184 
 185 static bool is_fw_header(struct rtlwifi_firmware_header *hdr)
 186 {
 187         return (le16_to_cpu(hdr->signature) & 0xfff0) == 0x2300;
 188 }
 189 
 190 static struct rtl_hal_ops rtl8723e_hal_ops = {
 191         .init_sw_vars = rtl8723e_init_sw_vars,
 192         .deinit_sw_vars = rtl8723e_deinit_sw_vars,
 193         .read_eeprom_info = rtl8723e_read_eeprom_info,
 194         .interrupt_recognized = rtl8723e_interrupt_recognized,
 195         .hw_init = rtl8723e_hw_init,
 196         .hw_disable = rtl8723e_card_disable,
 197         .hw_suspend = rtl8723e_suspend,
 198         .hw_resume = rtl8723e_resume,
 199         .enable_interrupt = rtl8723e_enable_interrupt,
 200         .disable_interrupt = rtl8723e_disable_interrupt,
 201         .set_network_type = rtl8723e_set_network_type,
 202         .set_chk_bssid = rtl8723e_set_check_bssid,
 203         .set_qos = rtl8723e_set_qos,
 204         .set_bcn_reg = rtl8723e_set_beacon_related_registers,
 205         .set_bcn_intv = rtl8723e_set_beacon_interval,
 206         .update_interrupt_mask = rtl8723e_update_interrupt_mask,
 207         .get_hw_reg = rtl8723e_get_hw_reg,
 208         .set_hw_reg = rtl8723e_set_hw_reg,
 209         .update_rate_tbl = rtl8723e_update_hal_rate_tbl,
 210         .fill_tx_desc = rtl8723e_tx_fill_desc,
 211         .fill_tx_cmddesc = rtl8723e_tx_fill_cmddesc,
 212         .query_rx_desc = rtl8723e_rx_query_desc,
 213         .set_channel_access = rtl8723e_update_channel_access_setting,
 214         .radio_onoff_checking = rtl8723e_gpio_radio_on_off_checking,
 215         .set_bw_mode = rtl8723e_phy_set_bw_mode,
 216         .switch_channel = rtl8723e_phy_sw_chnl,
 217         .dm_watchdog = rtl8723e_dm_watchdog,
 218         .scan_operation_backup = rtl8723e_phy_scan_operation_backup,
 219         .set_rf_power_state = rtl8723e_phy_set_rf_power_state,
 220         .led_control = rtl8723e_led_control,
 221         .set_desc = rtl8723e_set_desc,
 222         .get_desc = rtl8723e_get_desc,
 223         .is_tx_desc_closed = rtl8723e_is_tx_desc_closed,
 224         .tx_polling = rtl8723e_tx_polling,
 225         .enable_hw_sec = rtl8723e_enable_hw_security_config,
 226         .set_key = rtl8723e_set_key,
 227         .init_sw_leds = rtl8723e_init_sw_leds,
 228         .get_bbreg = rtl8723_phy_query_bb_reg,
 229         .set_bbreg = rtl8723_phy_set_bb_reg,
 230         .get_rfreg = rtl8723e_phy_query_rf_reg,
 231         .set_rfreg = rtl8723e_phy_set_rf_reg,
 232         .c2h_command_handle = rtl_8723e_c2h_command_handle,
 233         .bt_wifi_media_status_notify = rtl_8723e_bt_wifi_media_status_notify,
 234         .bt_coex_off_before_lps =
 235                 rtl8723e_dm_bt_turn_off_bt_coexist_before_enter_lps,
 236         .get_btc_status = rtl8723e_get_btc_status,
 237         .is_fw_header = is_fw_header,
 238 };
 239 
 240 static struct rtl_mod_params rtl8723e_mod_params = {
 241         .sw_crypto = false,
 242         .inactiveps = true,
 243         .swctrl_lps = true,
 244         .fwctrl_lps = false,
 245         .aspm_support = 1,
 246         .debug_level = 0,
 247         .debug_mask = 0,
 248         .msi_support = false,
 249         .disable_watchdog = false,
 250 };
 251 
 252 static const struct rtl_hal_cfg rtl8723e_hal_cfg = {
 253         .bar_id = 2,
 254         .write_readback = true,
 255         .name = "rtl8723e_pci",
 256         .ops = &rtl8723e_hal_ops,
 257         .mod_params = &rtl8723e_mod_params,
 258         .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
 259         .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
 260         .maps[SYS_CLK] = REG_SYS_CLKR,
 261         .maps[MAC_RCR_AM] = AM,
 262         .maps[MAC_RCR_AB] = AB,
 263         .maps[MAC_RCR_ACRC32] = ACRC32,
 264         .maps[MAC_RCR_ACF] = ACF,
 265         .maps[MAC_RCR_AAP] = AAP,
 266         .maps[MAC_HIMR] = REG_HIMR,
 267         .maps[MAC_HIMRE] = REG_HIMRE,
 268         .maps[EFUSE_TEST] = REG_EFUSE_TEST,
 269         .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
 270         .maps[EFUSE_CLK] = 0,
 271         .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
 272         .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
 273         .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
 274         .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
 275         .maps[EFUSE_ANA8M] = ANA8M,
 276         .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
 277         .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
 278         .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
 279         .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
 280 
 281         .maps[RWCAM] = REG_CAMCMD,
 282         .maps[WCAMI] = REG_CAMWRITE,
 283         .maps[RCAMO] = REG_CAMREAD,
 284         .maps[CAMDBG] = REG_CAMDBG,
 285         .maps[SECR] = REG_SECCFG,
 286         .maps[SEC_CAM_NONE] = CAM_NONE,
 287         .maps[SEC_CAM_WEP40] = CAM_WEP40,
 288         .maps[SEC_CAM_TKIP] = CAM_TKIP,
 289         .maps[SEC_CAM_AES] = CAM_AES,
 290         .maps[SEC_CAM_WEP104] = CAM_WEP104,
 291 
 292         .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
 293         .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
 294         .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
 295         .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
 296         .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
 297         .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
 298         .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
 299         .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
 300         .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
 301         .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
 302         .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
 303         .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
 304         .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
 305         .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
 306         .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
 307         .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
 308 
 309         .maps[RTL_IMR_TXFOVW] = PHIMR_TXFOVW,
 310         .maps[RTL_IMR_PSTIMEOUT] = PHIMR_PSTIMEOUT,
 311         .maps[RTL_IMR_BCNINT] = PHIMR_BCNDMAINT0,
 312         .maps[RTL_IMR_RXFOVW] = PHIMR_RXFOVW,
 313         .maps[RTL_IMR_RDU] = PHIMR_RDU,
 314         .maps[RTL_IMR_ATIMEND] = PHIMR_ATIMEND_E,
 315         .maps[RTL_IMR_BDOK] = PHIMR_BCNDOK0,
 316         .maps[RTL_IMR_MGNTDOK] = PHIMR_MGNTDOK,
 317         .maps[RTL_IMR_TBDER] = PHIMR_TXBCNERR,
 318         .maps[RTL_IMR_HIGHDOK] = PHIMR_HIGHDOK,
 319         .maps[RTL_IMR_TBDOK] = PHIMR_TXBCNOK,
 320         .maps[RTL_IMR_BKDOK] = PHIMR_BKDOK,
 321         .maps[RTL_IMR_BEDOK] = PHIMR_BEDOK,
 322         .maps[RTL_IMR_VIDOK] = PHIMR_VIDOK,
 323         .maps[RTL_IMR_VODOK] = PHIMR_VODOK,
 324         .maps[RTL_IMR_ROK] = PHIMR_ROK,
 325         .maps[RTL_IBSS_INT_MASKS] =
 326                 (PHIMR_BCNDMAINT0 | PHIMR_TXBCNOK | PHIMR_TXBCNERR),
 327         .maps[RTL_IMR_C2HCMD] = PHIMR_C2HCMD,
 328 
 329 
 330         .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
 331         .maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
 332         .maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
 333         .maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
 334         .maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
 335         .maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
 336         .maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
 337         .maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
 338         .maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
 339         .maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
 340         .maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
 341         .maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
 342 
 343         .maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
 344         .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
 345 };
 346 
 347 static const struct pci_device_id rtl8723e_pci_ids[] = {
 348         {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8723, rtl8723e_hal_cfg)},
 349         {},
 350 };
 351 
 352 MODULE_DEVICE_TABLE(pci, rtl8723e_pci_ids);
 353 
 354 MODULE_AUTHOR("lizhaoming       <chaoming_li@realsil.com.cn>");
 355 MODULE_AUTHOR("Realtek WlanFAE  <wlanfae@realtek.com>");
 356 MODULE_LICENSE("GPL");
 357 MODULE_DESCRIPTION("Realtek 8723E 802.11n PCI wireless");
 358 MODULE_FIRMWARE("rtlwifi/rtl8723efw.bin");
 359 
 360 module_param_named(swenc, rtl8723e_mod_params.sw_crypto, bool, 0444);
 361 module_param_named(debug_level, rtl8723e_mod_params.debug_level, int, 0644);
 362 module_param_named(debug_mask, rtl8723e_mod_params.debug_mask, ullong, 0644);
 363 module_param_named(ips, rtl8723e_mod_params.inactiveps, bool, 0444);
 364 module_param_named(swlps, rtl8723e_mod_params.swctrl_lps, bool, 0444);
 365 module_param_named(fwlps, rtl8723e_mod_params.fwctrl_lps, bool, 0444);
 366 module_param_named(msi, rtl8723e_mod_params.msi_support, bool, 0444);
 367 module_param_named(aspm, rtl8723e_mod_params.aspm_support, int, 0444);
 368 module_param_named(disable_watchdog, rtl8723e_mod_params.disable_watchdog,
 369                    bool, 0444);
 370 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
 371 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
 372 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 1)\n");
 373 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 0)\n");
 374 MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 0)\n");
 375 MODULE_PARM_DESC(aspm, "Set to 1 to enable ASPM (default 1)\n");
 376 MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)");
 377 MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)");
 378 MODULE_PARM_DESC(disable_watchdog, "Set to 1 to disable the watchdog (default 0)\n");
 379 
 380 static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
 381 
 382 static struct pci_driver rtl8723e_driver = {
 383         .name = KBUILD_MODNAME,
 384         .id_table = rtl8723e_pci_ids,
 385         .probe = rtl_pci_probe,
 386         .remove = rtl_pci_disconnect,
 387         .driver.pm = &rtlwifi_pm_ops,
 388 };
 389 
 390 module_pci_driver(rtl8723e_driver);

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