1
2
3
4 #ifndef __RTL92C_DEF_H__
5 #define __RTL92C_DEF_H__
6
7 #define PHY_RSSI_SLID_WIN_MAX 100
8 #define PHY_LINKQUALITY_SLID_WIN_MAX 20
9 #define PHY_BEACON_RSSI_SLID_WIN_MAX 10
10
11 #define RX_SMOOTH_FACTOR 20
12
13 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
14 #define HAL_PRIME_CHNL_OFFSET_LOWER 1
15 #define HAL_PRIME_CHNL_OFFSET_UPPER 2
16
17 #define RX_MPDU_QUEUE 0
18 #define RX_CMD_QUEUE 1
19
20 #define CHIP_VER_B BIT(4)
21 #define CHIP_BONDING_IDENTIFIER(_value) (((_value) >> 22) & 0x3)
22 #define CHIP_BONDING_92C_1T2R 0x1
23 #define RF_TYPE_1T2R BIT(1)
24 #define CHIP_92C_BITMASK BIT(0)
25 #define CHIP_UNKNOWN BIT(7)
26 #define CHIP_92C_1T2R 0x03
27 #define CHIP_92C 0x01
28 #define CHIP_88C 0x00
29
30 enum version_8192c {
31 VERSION_A_CHIP_92C = 0x01,
32 VERSION_A_CHIP_88C = 0x00,
33 VERSION_B_CHIP_92C = 0x11,
34 VERSION_B_CHIP_88C = 0x10,
35 VERSION_TEST_CHIP_88C = 0x00,
36 VERSION_TEST_CHIP_92C = 0x01,
37 VERSION_NORMAL_TSMC_CHIP_88C = 0x10,
38 VERSION_NORMAL_TSMC_CHIP_92C = 0x11,
39 VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x13,
40 VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x30,
41 VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x31,
42 VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x33,
43 VERSION_NORMA_UMC_CHIP_8723_1T1R_A_CUT = 0x34,
44 VERSION_NORMA_UMC_CHIP_8723_1T1R_B_CUT = 0x3c,
45 VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x70,
46 VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x71,
47 VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x73,
48 VERSION_UNKNOWN = 0x88,
49 };
50
51 enum rtl819x_loopback_e {
52 RTL819X_NO_LOOPBACK = 0,
53 RTL819X_MAC_LOOPBACK = 1,
54 RTL819X_DMA_LOOPBACK = 2,
55 RTL819X_CCK_LOOPBACK = 3,
56 };
57
58 enum rf_optype {
59 RF_OP_BY_SW_3WIRE = 0,
60 RF_OP_BY_FW,
61 RF_OP_MAX
62 };
63
64 enum rf_power_state {
65 RF_ON,
66 RF_OFF,
67 RF_SLEEP,
68 RF_SHUT_DOWN,
69 };
70
71 enum power_save_mode {
72 POWER_SAVE_MODE_ACTIVE,
73 POWER_SAVE_MODE_SAVE,
74 };
75
76 enum power_polocy_config {
77 POWERCFG_MAX_POWER_SAVINGS,
78 POWERCFG_GLOBAL_POWER_SAVINGS,
79 POWERCFG_LOCAL_POWER_SAVINGS,
80 POWERCFG_LENOVO,
81 };
82
83 enum interface_select_pci {
84 INTF_SEL1_MINICARD = 0,
85 INTF_SEL0_PCIE = 1,
86 INTF_SEL2_RSV = 2,
87 INTF_SEL3_RSV = 3,
88 };
89
90 enum rtl_desc_qsel {
91 QSLT_BK = 0x2,
92 QSLT_BE = 0x0,
93 QSLT_VI = 0x5,
94 QSLT_VO = 0x7,
95 QSLT_BEACON = 0x10,
96 QSLT_HIGH = 0x11,
97 QSLT_MGNT = 0x12,
98 QSLT_CMD = 0x13,
99 };
100
101 struct phy_sts_cck_8192s_t {
102 u8 adc_pwdb_X[4];
103 u8 sq_rpt;
104 u8 cck_agc_rpt;
105 };
106
107 struct h2c_cmd_8192c {
108 u8 element_id;
109 u32 cmd_len;
110 u8 *p_cmdbuffer;
111 };
112
113 #endif