1
2
3
4 #ifndef __RTL92E_DEF_H__
5 #define __RTL92E_DEF_H__
6
7 #define RX_DESC_NUM_92E 512
8
9 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
10 #define HAL_PRIME_CHNL_OFFSET_LOWER 1
11 #define HAL_PRIME_CHNL_OFFSET_UPPER 2
12
13 #define RX_MPDU_QUEUE 0
14
15 #define IS_HT_RATE(_rate) \
16 (_rate >= DESC92C_RATEMCS0)
17 #define IS_CCK_RATE(_rate) \
18 (_rate >= DESC92C_RATE1M && _rate <= DESC92C_RATE11M)
19 #define IS_OFDM_RATE(_rate) \
20 (_rate >= DESC92C_RATE6M && _rate <= DESC92C_RATE54M)
21
22 enum version_8192e {
23 VERSION_TEST_CHIP_2T2R_8192E = 0x0024,
24 VERSION_NORMAL_CHIP_2T2R_8192E = 0x102C,
25 VERSION_UNKNOWN = 0xFF,
26 };
27
28 enum rtl_desc_qsel {
29 QSLT_BK = 0x2,
30 QSLT_BE = 0x0,
31 QSLT_VI = 0x5,
32 QSLT_VO = 0x7,
33 QSLT_BEACON = 0x10,
34 QSLT_HIGH = 0x11,
35 QSLT_MGNT = 0x12,
36 QSLT_CMD = 0x13,
37 };
38
39 enum rtl_desc92c_rate {
40 DESC92C_RATE1M = 0x00,
41 DESC92C_RATE2M = 0x01,
42 DESC92C_RATE5_5M = 0x02,
43 DESC92C_RATE11M = 0x03,
44
45 DESC92C_RATE6M = 0x04,
46 DESC92C_RATE9M = 0x05,
47 DESC92C_RATE12M = 0x06,
48 DESC92C_RATE18M = 0x07,
49 DESC92C_RATE24M = 0x08,
50 DESC92C_RATE36M = 0x09,
51 DESC92C_RATE48M = 0x0a,
52 DESC92C_RATE54M = 0x0b,
53
54 DESC92C_RATEMCS0 = 0x0c,
55 DESC92C_RATEMCS1 = 0x0d,
56 DESC92C_RATEMCS2 = 0x0e,
57 DESC92C_RATEMCS3 = 0x0f,
58 DESC92C_RATEMCS4 = 0x10,
59 DESC92C_RATEMCS5 = 0x11,
60 DESC92C_RATEMCS6 = 0x12,
61 DESC92C_RATEMCS7 = 0x13,
62 DESC92C_RATEMCS8 = 0x14,
63 DESC92C_RATEMCS9 = 0x15,
64 DESC92C_RATEMCS10 = 0x16,
65 DESC92C_RATEMCS11 = 0x17,
66 DESC92C_RATEMCS12 = 0x18,
67 DESC92C_RATEMCS13 = 0x19,
68 DESC92C_RATEMCS14 = 0x1a,
69 DESC92C_RATEMCS15 = 0x1b,
70 };
71 #endif