1
2
3
4 #ifndef __RTL92E_DM_H__
5 #define __RTL92E_DM_H__
6
7 #define OFDMCCA_TH 500
8 #define BW_IND_BIAS 500
9 #define MF_USC 2
10 #define MF_LSC 1
11 #define MF_USC_LSC 0
12 #define MONITOR_TIME 30
13
14 #define MAIN_ANT 0
15 #define AUX_ANT 1
16 #define MAIN_ANT_CG_TRX 1
17 #define AUX_ANT_CG_TRX 0
18 #define MAIN_ANT_CGCS_RX 0
19 #define AUX_ANT_CGCS_RX 1
20
21
22 #define DM_REG_RF_MODE_11N 0x00
23 #define DM_REG_RF_0B_11N 0x0B
24 #define DM_REG_CHNBW_11N 0x18
25 #define DM_REG_T_METER_11N 0x24
26 #define DM_REG_RF_25_11N 0x25
27 #define DM_REG_RF_26_11N 0x26
28 #define DM_REG_RF_27_11N 0x27
29 #define DM_REG_RF_2B_11N 0x2B
30 #define DM_REG_RF_2C_11N 0x2C
31 #define DM_REG_RXRF_A3_11N 0x3C
32 #define DM_REG_T_METER_92D_11N 0x42
33 #define DM_REG_T_METER_92E_11N 0x42
34
35
36
37 #define DM_REG_BB_CTRL_11N 0x800
38 #define DM_REG_RF_PIN_11N 0x804
39 #define DM_REG_PSD_CTRL_11N 0x808
40 #define DM_REG_TX_ANT_CTRL_11N 0x80C
41 #define DM_REG_BB_PWR_SAV5_11N 0x818
42 #define DM_REG_CCK_RPT_FORMAT_11N 0x824
43 #define DM_REG_RX_DEFUALT_A_11N 0x858
44 #define DM_REG_RX_DEFUALT_B_11N 0x85A
45 #define DM_REG_BB_PWR_SAV3_11N 0x85C
46 #define DM_REG_ANTSEL_CTRL_11N 0x860
47 #define DM_REG_RX_ANT_CTRL_11N 0x864
48 #define DM_REG_PIN_CTRL_11N 0x870
49 #define DM_REG_BB_PWR_SAV1_11N 0x874
50 #define DM_REG_ANTSEL_PATH_11N 0x878
51 #define DM_REG_BB_3WIRE_11N 0x88C
52 #define DM_REG_SC_CNT_11N 0x8C4
53 #define DM_REG_PSD_DATA_11N 0x8B4
54
55 #define DM_REG_ANT_MAPPING1_11N 0x914
56 #define DM_REG_ANT_MAPPING2_11N 0x918
57
58 #define DM_REG_CCK_ANTDIV_PARA1_11N 0xA00
59 #define DM_REG_CCK_CCA_11N 0xA0A
60 #define DM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
61 #define DM_REG_CCK_ANTDIV_PARA3_11N 0xA10
62 #define DM_REG_CCK_ANTDIV_PARA4_11N 0xA14
63 #define DM_REG_CCK_FILTER_PARA1_11N 0xA22
64 #define DM_REG_CCK_FILTER_PARA2_11N 0xA23
65 #define DM_REG_CCK_FILTER_PARA3_11N 0xA24
66 #define DM_REG_CCK_FILTER_PARA4_11N 0xA25
67 #define DM_REG_CCK_FILTER_PARA5_11N 0xA26
68 #define DM_REG_CCK_FILTER_PARA6_11N 0xA27
69 #define DM_REG_CCK_FILTER_PARA7_11N 0xA28
70 #define DM_REG_CCK_FILTER_PARA8_11N 0xA29
71 #define DM_REG_CCK_FA_RST_11N 0xA2C
72 #define DM_REG_CCK_FA_MSB_11N 0xA58
73 #define DM_REG_CCK_FA_LSB_11N 0xA5C
74 #define DM_REG_CCK_CCA_CNT_11N 0xA60
75 #define DM_REG_BB_PWR_SAV4_11N 0xA74
76
77 #define DM_REG_LNA_SWITCH_11N 0xB2C
78 #define DM_REG_PATH_SWITCH_11N 0xB30
79 #define DM_REG_RSSI_CTRL_11N 0xB38
80 #define DM_REG_CONFIG_ANTA_11N 0xB68
81 #define DM_REG_RSSI_BT_11N 0xB9C
82
83 #define DM_REG_OFDM_FA_HOLDC_11N 0xC00
84 #define DM_REG_RX_PATH_11N 0xC04
85 #define DM_REG_TRMUX_11N 0xC08
86 #define DM_REG_OFDM_FA_RSTC_11N 0xC0C
87 #define DM_REG_RXIQI_MATRIX_11N 0xC14
88 #define DM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
89 #define DM_REG_IGI_A_11N 0xC50
90 #define DM_REG_ANTDIV_PARA2_11N 0xC54
91 #define DM_REG_IGI_B_11N 0xC58
92 #define DM_REG_ANTDIV_PARA3_11N 0xC5C
93 #define DM_REG_L1SBD_PD_CH_11N 0XC6C
94 #define DM_REG_BB_PWR_SAV2_11N 0xC70
95 #define DM_REG_RX_OFF_11N 0xC7C
96 #define DM_REG_TXIQK_MATRIXA_11N 0xC80
97 #define DM_REG_TXIQK_MATRIXB_11N 0xC88
98 #define DM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
99 #define DM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
100 #define DM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
101 #define DM_REG_ANTDIV_PARA1_11N 0xCA4
102 #define DM_REG_OFDM_FA_TYPE1_11N 0xCF0
103
104 #define DM_REG_OFDM_FA_RSTD_11N 0xD00
105 #define DM_REG_OFDM_FA_TYPE2_11N 0xDA0
106 #define DM_REG_OFDM_FA_TYPE3_11N 0xDA4
107 #define DM_REG_OFDM_FA_TYPE4_11N 0xDA8
108
109 #define DM_REG_TXAGC_A_6_18_11N 0xE00
110 #define DM_REG_TXAGC_A_24_54_11N 0xE04
111 #define DM_REG_TXAGC_A_1_MCS32_11N 0xE08
112 #define DM_REG_TXAGC_A_MCS0_3_11N 0xE10
113 #define DM_REG_TXAGC_A_MCS4_7_11N 0xE14
114 #define DM_REG_TXAGC_A_MCS8_11_11N 0xE18
115 #define DM_REG_TXAGC_A_MCS12_15_11N 0xE1C
116 #define DM_REG_FPGA0_IQK_11N 0xE28
117 #define DM_REG_TXIQK_TONE_A_11N 0xE30
118 #define DM_REG_RXIQK_TONE_A_11N 0xE34
119 #define DM_REG_TXIQK_PI_A_11N 0xE38
120 #define DM_REG_RXIQK_PI_A_11N 0xE3C
121 #define DM_REG_TXIQK_11N 0xE40
122 #define DM_REG_RXIQK_11N 0xE44
123 #define DM_REG_IQK_AGC_PTS_11N 0xE48
124 #define DM_REG_IQK_AGC_RSP_11N 0xE4C
125 #define DM_REG_BLUETOOTH_11N 0xE6C
126 #define DM_REG_RX_WAIT_CCA_11N 0xE70
127 #define DM_REG_TX_CCK_RFON_11N 0xE74
128 #define DM_REG_TX_CCK_BBON_11N 0xE78
129 #define DM_REG_OFDM_RFON_11N 0xE7C
130 #define DM_REG_OFDM_BBON_11N 0xE80
131 #define DM_REG_TX2RX_11N 0xE84
132 #define DM_REG_TX2TX_11N 0xE88
133 #define DM_REG_RX_CCK_11N 0xE8C
134 #define DM_REG_RX_OFDM_11N 0xED0
135 #define DM_REG_RX_WAIT_RIFS_11N 0xED4
136 #define DM_REG_RX2RX_11N 0xED8
137 #define DM_REG_STANDBY_11N 0xEDC
138 #define DM_REG_SLEEP_11N 0xEE0
139 #define DM_REG_PMPD_ANAEN_11N 0xEEC
140
141
142 #define DM_REG_BB_RST_11N 0x02
143 #define DM_REG_ANTSEL_PIN_11N 0x4C
144 #define DM_REG_EARLY_MODE_11N 0x4D0
145 #define DM_REG_RSSI_MONITOR_11N 0x4FE
146 #define DM_REG_EDCA_VO_11N 0x500
147 #define DM_REG_EDCA_VI_11N 0x504
148 #define DM_REG_EDCA_BE_11N 0x508
149 #define DM_REG_EDCA_BK_11N 0x50C
150 #define DM_REG_TXPAUSE_11N 0x522
151 #define DM_REG_RESP_TX_11N 0x6D8
152 #define DM_REG_ANT_TRAIN_PARA1_11N 0x7b0
153 #define DM_REG_ANT_TRAIN_PARA2_11N 0x7b4
154
155
156 #define DM_BIT_IGI_11N 0x0000007F
157
158 #define HAL_DM_DIG_DISABLE BIT(0)
159 #define HAL_DM_HIPWR_DISABLE BIT(1)
160
161 #define OFDM_TABLE_LENGTH 43
162 #define CCK_TABLE_LENGTH 33
163
164 #define OFDM_TABLE_SIZE 43
165 #define CCK_TABLE_SIZE 33
166
167 #define BW_AUTO_SWITCH_HIGH_LOW 25
168 #define BW_AUTO_SWITCH_LOW_HIGH 30
169
170 #define DM_DIG_FA_UPPER 0x3e
171 #define DM_DIG_FA_LOWER 0x1e
172 #define DM_DIG_FA_TH0 0x200
173 #define DM_DIG_FA_TH1 0x300
174 #define DM_DIG_FA_TH2 0x400
175
176 #define RXPATHSELECTION_SS_TH_LOW 30
177 #define RXPATHSELECTION_DIFF_TH 18
178
179 #define DM_RATR_STA_INIT 0
180 #define DM_RATR_STA_HIGH 1
181 #define DM_RATR_STA_MIDDLE 2
182 #define DM_RATR_STA_LOW 3
183
184 #define CTS2SELF_THVAL 30
185 #define REGC38_TH 20
186
187 #define WAIOTTHVAL 25
188
189 #define TXHIGHPWRLEVEL_NORMAL 0
190 #define TXHIGHPWRLEVEL_LEVEL1 1
191 #define TXHIGHPWRLEVEL_LEVEL2 2
192 #define TXHIGHPWRLEVEL_BT1 3
193 #define TXHIGHPWRLEVEL_BT2 4
194
195 #define DM_TYPE_BYFW 0
196 #define DM_TYPE_BYDRIVER 1
197
198 #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
199 #define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
200 #define TXPWRTRACK_MAX_IDX 6
201
202
203 #define ATC_STATUS_OFF 0x0
204 #define ATC_STATUS_ON 0x1
205 #define CFO_THRESHOLD_XTAL 10
206 #define CFO_THRESHOLD_ATC 80
207
208
209 #define RA_RSSIDUMP 0xcb0
210 #define RB_RSSIDUMP 0xcb1
211 #define RS1_RXEVMDUMP 0xcb2
212 #define RS2_RXEVMDUMP 0xcb3
213 #define RA_RXSNRDUMP 0xcb4
214 #define RB_RXSNRDUMP 0xcb5
215 #define RA_CFOSHORTDUMP 0xcb6
216 #define RB_CFOSHORTDUMP 0xcb8
217 #define RA_CFOLONGDUMP 0xcba
218 #define RB_CFOLONGDUMP 0xcbc
219
220 void rtl92ee_dm_init(struct ieee80211_hw *hw);
221 void rtl92ee_dm_watchdog(struct ieee80211_hw *hw);
222 void rtl92ee_dm_write_cck_cca_thres(struct ieee80211_hw *hw,
223 u8 cur_thres);
224 void rtl92ee_dm_write_dig(struct ieee80211_hw *hw, u8 current_igi);
225 void rtl92ee_dm_init_edca_turbo(struct ieee80211_hw *hw);
226 void rtl92ee_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
227 void rtl92ee_dm_dynamic_arfb_select(struct ieee80211_hw *hw,
228 u8 rate, bool collision_state);
229 #endif