This source file includes following definitions.
- _rtl_mac_to_hwqueue
- _rtl_pci_update_default_setting
- _rtl_pci_platform_switch_device_pci_aspm
- _rtl_pci_switch_clk_req
- rtl_pci_disable_aspm
- rtl_pci_enable_aspm
- rtl_pci_get_amd_l1_patch
- rtl_pci_check_buddy_priv
- rtl_pci_get_linkcontrol_field
- rtl_pci_parse_configuration
- rtl_pci_init_aspm
- _rtl_pci_io_handler_init
- _rtl_update_earlymode_info
- _rtl_pci_tx_chk_waitq
- _rtl_pci_tx_isr
- _rtl_pci_init_one_rxdesc
- _rtl_pci_rx_to_mac80211
- _rtl_pci_hs_interrupt
- _rtl_pci_rx_interrupt
- _rtl_pci_interrupt
- _rtl_pci_irq_tasklet
- _rtl_pci_prepare_bcn_tasklet
- _rtl_pci_init_trx_var
- _rtl_pci_init_struct
- _rtl_pci_init_tx_ring
- _rtl_pci_init_rx_ring
- _rtl_pci_free_tx_ring
- _rtl_pci_free_rx_ring
- _rtl_pci_init_trx_ring
- _rtl_pci_deinit_trx_ring
- rtl_pci_reset_trx_ring
- rtl_pci_tx_chk_waitq_insert
- rtl_pci_tx
- rtl_pci_flush
- rtl_pci_deinit
- rtl_pci_init
- rtl_pci_start
- rtl_pci_stop
- _rtl_pci_find_adapter
- rtl_pci_intr_mode_msi
- rtl_pci_intr_mode_legacy
- rtl_pci_intr_mode_decide
- platform_enable_dma64
- rtl_pci_probe
- rtl_pci_disconnect
- rtl_pci_suspend
- rtl_pci_resume
1
2
3
4 #include "wifi.h"
5 #include "core.h"
6 #include "pci.h"
7 #include "base.h"
8 #include "ps.h"
9 #include "efuse.h"
10 #include <linux/interrupt.h>
11 #include <linux/export.h>
12 #include <linux/module.h>
13
14 MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
15 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
16 MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>");
17 MODULE_LICENSE("GPL");
18 MODULE_DESCRIPTION("PCI basic driver for rtlwifi");
19
20 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
21 INTEL_VENDOR_ID,
22 ATI_VENDOR_ID,
23 AMD_VENDOR_ID,
24 SIS_VENDOR_ID
25 };
26
27 static const u8 ac_to_hwq[] = {
28 VO_QUEUE,
29 VI_QUEUE,
30 BE_QUEUE,
31 BK_QUEUE
32 };
33
34 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw, struct sk_buff *skb)
35 {
36 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
37 __le16 fc = rtl_get_fc(skb);
38 u8 queue_index = skb_get_queue_mapping(skb);
39 struct ieee80211_hdr *hdr;
40
41 if (unlikely(ieee80211_is_beacon(fc)))
42 return BEACON_QUEUE;
43 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
44 return MGNT_QUEUE;
45 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
46 if (ieee80211_is_nullfunc(fc))
47 return HIGH_QUEUE;
48 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
49 hdr = rtl_get_hdr(skb);
50
51 if (is_multicast_ether_addr(hdr->addr1) ||
52 is_broadcast_ether_addr(hdr->addr1))
53 return HIGH_QUEUE;
54 }
55
56 return ac_to_hwq[queue_index];
57 }
58
59
60 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
61 {
62 struct rtl_priv *rtlpriv = rtl_priv(hw);
63 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
64 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
65 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
66 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
67 u8 init_aspm;
68
69 ppsc->reg_rfps_level = 0;
70 ppsc->support_aspm = false;
71
72
73 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
74 switch (rtlpci->const_pci_aspm) {
75 case 0:
76
77 break;
78
79 case 1:
80
81 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
82 break;
83
84 case 2:
85
86 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
87 RT_RF_OFF_LEVL_CLK_REQ);
88 break;
89
90 case 3:
91
92
93
94 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
95 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
96 RT_RF_OFF_LEVL_CLK_REQ);
97 break;
98
99 case 4:
100
101
102
103 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
104 RT_RF_OFF_LEVL_CLK_REQ);
105 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
106 break;
107 }
108
109 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
110
111
112 switch (rtlpci->const_hwsw_rfoff_d3) {
113 case 1:
114 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
115 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
116 break;
117
118 case 2:
119 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
120 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
121 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
122 break;
123
124 case 3:
125 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
126 break;
127 }
128
129
130 switch (rtlpci->const_support_pciaspm) {
131 case 0:
132
133 ppsc->support_aspm = false;
134 break;
135 case 1:
136
137 ppsc->support_aspm = true;
138 ppsc->support_backdoor = true;
139 break;
140 case 2:
141
142 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
143 ppsc->support_aspm = true;
144 break;
145 default:
146 pr_err("switch case %#x not processed\n",
147 rtlpci->const_support_pciaspm);
148 break;
149 }
150
151
152
153
154 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
155 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
156 init_aspm == 0x43)
157 ppsc->support_aspm = false;
158 }
159
160 static bool _rtl_pci_platform_switch_device_pci_aspm(
161 struct ieee80211_hw *hw,
162 u8 value)
163 {
164 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
165 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
166
167 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
168 value |= 0x40;
169
170 pci_write_config_byte(rtlpci->pdev, 0x80, value);
171
172 return false;
173 }
174
175
176 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
177 {
178 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
179 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
180
181 pci_write_config_byte(rtlpci->pdev, 0x81, value);
182
183 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
184 udelay(100);
185 }
186
187
188 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
189 {
190 struct rtl_priv *rtlpriv = rtl_priv(hw);
191 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
192 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
193 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
194 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
195 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
196
197 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
198 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
199 pcibridge_linkctrlreg;
200 u16 aspmlevel = 0;
201 u8 tmp_u1b = 0;
202
203 if (!ppsc->support_aspm)
204 return;
205
206 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
207 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
208 "PCI(Bridge) UNKNOWN\n");
209
210 return;
211 }
212
213 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
214 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
215 _rtl_pci_switch_clk_req(hw, 0x0);
216 }
217
218
219 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
220
221
222 aspmlevel |= BIT(0) | BIT(1);
223 linkctrl_reg &= ~aspmlevel;
224 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
225
226 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
227 udelay(50);
228
229
230 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
231 pcibridge_linkctrlreg);
232
233 udelay(50);
234 }
235
236
237
238
239
240
241 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
242 {
243 struct rtl_priv *rtlpriv = rtl_priv(hw);
244 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
245 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
246 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
247 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
248 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
249 u16 aspmlevel;
250 u8 u_pcibridge_aspmsetting;
251 u8 u_device_aspmsetting;
252
253 if (!ppsc->support_aspm)
254 return;
255
256 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
257 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
258 "PCI(Bridge) UNKNOWN\n");
259 return;
260 }
261
262
263
264 u_pcibridge_aspmsetting =
265 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
266 rtlpci->const_hostpci_aspm_setting;
267
268 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
269 u_pcibridge_aspmsetting &= ~BIT(0);
270
271 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
272 u_pcibridge_aspmsetting);
273
274 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
275 "PlatformEnableASPM(): Write reg[%x] = %x\n",
276 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
277 u_pcibridge_aspmsetting);
278
279 udelay(50);
280
281
282 aspmlevel = rtlpci->const_devicepci_aspm_setting;
283 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
284
285
286
287
288 u_device_aspmsetting |= aspmlevel;
289
290 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
291
292 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
293 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
294 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
295 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
296 }
297 udelay(100);
298 }
299
300 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
301 {
302 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
303
304 bool status = false;
305 u8 offset_e0;
306 unsigned int offset_e4;
307
308 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
309
310 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
311
312 if (offset_e0 == 0xA0) {
313 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
314 if (offset_e4 & BIT(23))
315 status = true;
316 }
317
318 return status;
319 }
320
321 static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw,
322 struct rtl_priv **buddy_priv)
323 {
324 struct rtl_priv *rtlpriv = rtl_priv(hw);
325 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
326 bool find_buddy_priv = false;
327 struct rtl_priv *tpriv;
328 struct rtl_pci_priv *tpcipriv = NULL;
329
330 if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) {
331 list_for_each_entry(tpriv, &rtlpriv->glb_var->glb_priv_list,
332 list) {
333 tpcipriv = (struct rtl_pci_priv *)tpriv->priv;
334 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
335 "pcipriv->ndis_adapter.funcnumber %x\n",
336 pcipriv->ndis_adapter.funcnumber);
337 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
338 "tpcipriv->ndis_adapter.funcnumber %x\n",
339 tpcipriv->ndis_adapter.funcnumber);
340
341 if (pcipriv->ndis_adapter.busnumber ==
342 tpcipriv->ndis_adapter.busnumber &&
343 pcipriv->ndis_adapter.devnumber ==
344 tpcipriv->ndis_adapter.devnumber &&
345 pcipriv->ndis_adapter.funcnumber !=
346 tpcipriv->ndis_adapter.funcnumber) {
347 find_buddy_priv = true;
348 break;
349 }
350 }
351 }
352
353 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
354 "find_buddy_priv %d\n", find_buddy_priv);
355
356 if (find_buddy_priv)
357 *buddy_priv = tpriv;
358
359 return find_buddy_priv;
360 }
361
362 static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
363 {
364 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
365 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
366 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
367 u8 linkctrl_reg;
368 u8 num4bbytes;
369
370 num4bbytes = (capabilityoffset + 0x10) / 4;
371
372
373 pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg);
374
375 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
376 }
377
378 static void rtl_pci_parse_configuration(struct pci_dev *pdev,
379 struct ieee80211_hw *hw)
380 {
381 struct rtl_priv *rtlpriv = rtl_priv(hw);
382 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
383
384 u8 tmp;
385 u16 linkctrl_reg;
386
387
388 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg);
389 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg;
390
391 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
392 pcipriv->ndis_adapter.linkctrl_reg);
393
394 pci_read_config_byte(pdev, 0x98, &tmp);
395 tmp |= BIT(4);
396 pci_write_config_byte(pdev, 0x98, tmp);
397
398 tmp = 0x17;
399 pci_write_config_byte(pdev, 0x70f, tmp);
400 }
401
402 static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
403 {
404 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
405
406 _rtl_pci_update_default_setting(hw);
407
408 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
409
410 rtl_pci_enable_aspm(hw);
411 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
412 }
413 }
414
415 static void _rtl_pci_io_handler_init(struct device *dev,
416 struct ieee80211_hw *hw)
417 {
418 struct rtl_priv *rtlpriv = rtl_priv(hw);
419
420 rtlpriv->io.dev = dev;
421
422 rtlpriv->io.write8_async = pci_write8_async;
423 rtlpriv->io.write16_async = pci_write16_async;
424 rtlpriv->io.write32_async = pci_write32_async;
425
426 rtlpriv->io.read8_sync = pci_read8_sync;
427 rtlpriv->io.read16_sync = pci_read16_sync;
428 rtlpriv->io.read32_sync = pci_read32_sync;
429 }
430
431 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
432 struct sk_buff *skb,
433 struct rtl_tcb_desc *tcb_desc, u8 tid)
434 {
435 struct rtl_priv *rtlpriv = rtl_priv(hw);
436 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
437 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
438 struct sk_buff *next_skb;
439 u8 additionlen = FCS_LEN;
440
441
442 if (info->control.hw_key)
443 additionlen += info->control.hw_key->icv_len;
444
445
446 tcb_desc->empkt_num = 0;
447 spin_lock_bh(&rtlpriv->locks.waitq_lock);
448 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
449 struct ieee80211_tx_info *next_info;
450
451 next_info = IEEE80211_SKB_CB(next_skb);
452 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
453 tcb_desc->empkt_len[tcb_desc->empkt_num] =
454 next_skb->len + additionlen;
455 tcb_desc->empkt_num++;
456 } else {
457 break;
458 }
459
460 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
461 next_skb))
462 break;
463
464 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num)
465 break;
466 }
467 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
468
469 return true;
470 }
471
472
473 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
474 {
475 struct rtl_priv *rtlpriv = rtl_priv(hw);
476 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
477 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
478 struct sk_buff *skb = NULL;
479 struct ieee80211_tx_info *info = NULL;
480 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
481 int tid;
482
483 if (!rtlpriv->rtlhal.earlymode_enable)
484 return;
485
486 if (rtlpriv->dm.supp_phymode_switch &&
487 (rtlpriv->easy_concurrent_ctl.switch_in_process ||
488 (rtlpriv->buddy_priv &&
489 rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process)))
490 return;
491
492 for (tid = 7; tid >= 0; tid--) {
493 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)];
494 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
495
496 while (!mac->act_scanning &&
497 rtlpriv->psc.rfpwr_state == ERFON) {
498 struct rtl_tcb_desc tcb_desc;
499
500 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
501
502 spin_lock(&rtlpriv->locks.waitq_lock);
503 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
504 (ring->entries - skb_queue_len(&ring->queue) >
505 rtlhal->max_earlymode_num)) {
506 skb = skb_dequeue(&mac->skb_waitq[tid]);
507 } else {
508 spin_unlock(&rtlpriv->locks.waitq_lock);
509 break;
510 }
511 spin_unlock(&rtlpriv->locks.waitq_lock);
512
513
514
515
516 info = IEEE80211_SKB_CB(skb);
517 if (info->flags & IEEE80211_TX_CTL_AMPDU)
518 _rtl_update_earlymode_info(hw, skb,
519 &tcb_desc, tid);
520
521 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
522 }
523 }
524 }
525
526 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
527 {
528 struct rtl_priv *rtlpriv = rtl_priv(hw);
529 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
530
531 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
532
533 while (skb_queue_len(&ring->queue)) {
534 struct sk_buff *skb;
535 struct ieee80211_tx_info *info;
536 __le16 fc;
537 u8 tid;
538 u8 *entry;
539
540 if (rtlpriv->use_new_trx_flow)
541 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
542 else
543 entry = (u8 *)(&ring->desc[ring->idx]);
544
545 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx))
546 return;
547 ring->idx = (ring->idx + 1) % ring->entries;
548
549 skb = __skb_dequeue(&ring->queue);
550 pci_unmap_single(rtlpci->pdev,
551 rtlpriv->cfg->ops->
552 get_desc(hw, (u8 *)entry, true,
553 HW_DESC_TXBUFF_ADDR),
554 skb->len, PCI_DMA_TODEVICE);
555
556
557 if (rtlpriv->rtlhal.earlymode_enable)
558 skb_pull(skb, EM_HDR_LEN);
559
560 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
561 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
562 ring->idx,
563 skb_queue_len(&ring->queue),
564 *(u16 *)(skb->data + 22));
565
566 if (prio == TXCMD_QUEUE) {
567 dev_kfree_skb(skb);
568 goto tx_status_ok;
569 }
570
571
572
573
574
575 fc = rtl_get_fc(skb);
576 if (ieee80211_is_nullfunc(fc)) {
577 if (ieee80211_has_pm(fc)) {
578 rtlpriv->mac80211.offchan_delay = true;
579 rtlpriv->psc.state_inap = true;
580 } else {
581 rtlpriv->psc.state_inap = false;
582 }
583 }
584 if (ieee80211_is_action(fc)) {
585 struct ieee80211_mgmt *action_frame =
586 (struct ieee80211_mgmt *)skb->data;
587 if (action_frame->u.action.u.ht_smps.action ==
588 WLAN_HT_ACTION_SMPS) {
589 dev_kfree_skb(skb);
590 goto tx_status_ok;
591 }
592 }
593
594
595 tid = rtl_get_tid(skb);
596 if (tid <= 7)
597 rtlpriv->link_info.tidtx_inperiod[tid]++;
598
599 info = IEEE80211_SKB_CB(skb);
600
601 if (likely(!ieee80211_is_nullfunc(fc))) {
602 ieee80211_tx_info_clear_status(info);
603 info->flags |= IEEE80211_TX_STAT_ACK;
604
605 ieee80211_tx_status_irqsafe(hw, skb);
606 } else {
607 rtl_tx_ackqueue(hw, skb);
608 }
609
610 if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) {
611 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
612 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n",
613 prio, ring->idx,
614 skb_queue_len(&ring->queue));
615
616 ieee80211_wake_queue(hw, skb_get_queue_mapping(skb));
617 }
618 tx_status_ok:
619 skb = NULL;
620 }
621
622 if (((rtlpriv->link_info.num_rx_inperiod +
623 rtlpriv->link_info.num_tx_inperiod) > 8) ||
624 rtlpriv->link_info.num_rx_inperiod > 2)
625 rtl_lps_leave(hw);
626 }
627
628 static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw,
629 struct sk_buff *new_skb, u8 *entry,
630 int rxring_idx, int desc_idx)
631 {
632 struct rtl_priv *rtlpriv = rtl_priv(hw);
633 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
634 u32 bufferaddress;
635 u8 tmp_one = 1;
636 struct sk_buff *skb;
637
638 if (likely(new_skb)) {
639 skb = new_skb;
640 goto remap;
641 }
642 skb = dev_alloc_skb(rtlpci->rxbuffersize);
643 if (!skb)
644 return 0;
645
646 remap:
647
648 *((dma_addr_t *)skb->cb) =
649 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
650 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
651 bufferaddress = *((dma_addr_t *)skb->cb);
652 if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress))
653 return 0;
654 rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb;
655 if (rtlpriv->use_new_trx_flow) {
656
657 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
658 HW_DESC_RX_PREPARE,
659 (u8 *)(dma_addr_t *)skb->cb);
660 } else {
661 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
662 HW_DESC_RXBUFF_ADDR,
663 (u8 *)&bufferaddress);
664 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
665 HW_DESC_RXPKT_LEN,
666 (u8 *)&rtlpci->rxbuffersize);
667 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
668 HW_DESC_RXOWN,
669 (u8 *)&tmp_one);
670 }
671 return 1;
672 }
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687 static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw,
688 struct sk_buff *skb,
689 struct ieee80211_rx_status rx_status)
690 {
691 if (unlikely(!rtl_action_proc(hw, skb, false))) {
692 dev_kfree_skb_any(skb);
693 } else {
694 struct sk_buff *uskb = NULL;
695
696 uskb = dev_alloc_skb(skb->len + 128);
697 if (likely(uskb)) {
698 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status,
699 sizeof(rx_status));
700 skb_put_data(uskb, skb->data, skb->len);
701 dev_kfree_skb_any(skb);
702 ieee80211_rx_irqsafe(hw, uskb);
703 } else {
704 ieee80211_rx_irqsafe(hw, skb);
705 }
706 }
707 }
708
709
710 static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw)
711 {
712 struct rtl_priv *rtlpriv = rtl_priv(hw);
713 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
714
715 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR],
716 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) |
717 rtlpci->sys_irq_mask);
718 }
719
720 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
721 {
722 struct rtl_priv *rtlpriv = rtl_priv(hw);
723 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
724 int rxring_idx = RTL_PCI_RX_MPDU_QUEUE;
725 struct ieee80211_rx_status rx_status = { 0 };
726 unsigned int count = rtlpci->rxringcount;
727 u8 own;
728 u8 tmp_one;
729 bool unicast = false;
730 u8 hw_queue = 0;
731 unsigned int rx_remained_cnt = 0;
732 struct rtl_stats stats = {
733 .signal = 0,
734 .rate = 0,
735 };
736
737
738 while (count--) {
739 struct ieee80211_hdr *hdr;
740 __le16 fc;
741 u16 len;
742
743 struct rtl_rx_buffer_desc *buffer_desc = NULL;
744
745 struct rtl_rx_desc *pdesc = NULL;
746
747 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[
748 rtlpci->rx_ring[rxring_idx].idx];
749 struct sk_buff *new_skb;
750
751 if (rtlpriv->use_new_trx_flow) {
752 if (rx_remained_cnt == 0)
753 rx_remained_cnt =
754 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw,
755 hw_queue);
756 if (rx_remained_cnt == 0)
757 return;
758 buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[
759 rtlpci->rx_ring[rxring_idx].idx];
760 pdesc = (struct rtl_rx_desc *)skb->data;
761 } else {
762 pdesc = &rtlpci->rx_ring[rxring_idx].desc[
763 rtlpci->rx_ring[rxring_idx].idx];
764
765 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
766 false,
767 HW_DESC_OWN);
768 if (own)
769 return;
770 }
771
772
773
774
775
776 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb),
777 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
778
779
780 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
781 if (unlikely(!new_skb))
782 goto no_new;
783 memset(&rx_status, 0, sizeof(rx_status));
784 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
785 &rx_status, (u8 *)pdesc, skb);
786
787 if (rtlpriv->use_new_trx_flow)
788 rtlpriv->cfg->ops->rx_check_dma_ok(hw,
789 (u8 *)buffer_desc,
790 hw_queue);
791
792 len = rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, false,
793 HW_DESC_RXPKT_LEN);
794
795 if (skb->end - skb->tail > len) {
796 skb_put(skb, len);
797 if (rtlpriv->use_new_trx_flow)
798 skb_reserve(skb, stats.rx_drvinfo_size +
799 stats.rx_bufshift + 24);
800 else
801 skb_reserve(skb, stats.rx_drvinfo_size +
802 stats.rx_bufshift);
803 } else {
804 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
805 "skb->end - skb->tail = %d, len is %d\n",
806 skb->end - skb->tail, len);
807 dev_kfree_skb_any(skb);
808 goto new_trx_end;
809 }
810
811 if (stats.packet_report_type == C2H_PACKET) {
812 rtl_c2hcmd_enqueue(hw, skb);
813 goto new_trx_end;
814 }
815
816
817
818
819
820
821
822 hdr = rtl_get_hdr(skb);
823 fc = rtl_get_fc(skb);
824
825 if (!stats.crc && !stats.hwerror && (skb->len > FCS_LEN)) {
826 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
827 sizeof(rx_status));
828
829 if (is_broadcast_ether_addr(hdr->addr1)) {
830 ;
831 } else if (is_multicast_ether_addr(hdr->addr1)) {
832 ;
833 } else {
834 unicast = true;
835 rtlpriv->stats.rxbytesunicast += skb->len;
836 }
837 rtl_is_special_data(hw, skb, false, true);
838
839 if (ieee80211_is_data(fc)) {
840 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
841 if (unicast)
842 rtlpriv->link_info.num_rx_inperiod++;
843 }
844
845 rtl_collect_scan_list(hw, skb);
846
847
848 rtl_beacon_statistic(hw, skb);
849 rtl_p2p_info(hw, (void *)skb->data, skb->len);
850
851 rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
852 rtl_recognize_peer(hw, (void *)skb->data, skb->len);
853 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP &&
854 rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G &&
855 (ieee80211_is_beacon(fc) ||
856 ieee80211_is_probe_resp(fc))) {
857 dev_kfree_skb_any(skb);
858 } else {
859 _rtl_pci_rx_to_mac80211(hw, skb, rx_status);
860 }
861 } else {
862
863 dev_kfree_skb_any(skb);
864 }
865 new_trx_end:
866 if (rtlpriv->use_new_trx_flow) {
867 rtlpci->rx_ring[hw_queue].next_rx_rp += 1;
868 rtlpci->rx_ring[hw_queue].next_rx_rp %=
869 RTL_PCI_MAX_RX_COUNT;
870
871 rx_remained_cnt--;
872 rtl_write_word(rtlpriv, 0x3B4,
873 rtlpci->rx_ring[hw_queue].next_rx_rp);
874 }
875 if (((rtlpriv->link_info.num_rx_inperiod +
876 rtlpriv->link_info.num_tx_inperiod) > 8) ||
877 rtlpriv->link_info.num_rx_inperiod > 2)
878 rtl_lps_leave(hw);
879 skb = new_skb;
880 no_new:
881 if (rtlpriv->use_new_trx_flow) {
882 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc,
883 rxring_idx,
884 rtlpci->rx_ring[rxring_idx].idx);
885 } else {
886 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc,
887 rxring_idx,
888 rtlpci->rx_ring[rxring_idx].idx);
889 if (rtlpci->rx_ring[rxring_idx].idx ==
890 rtlpci->rxringcount - 1)
891 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc,
892 false,
893 HW_DESC_RXERO,
894 (u8 *)&tmp_one);
895 }
896 rtlpci->rx_ring[rxring_idx].idx =
897 (rtlpci->rx_ring[rxring_idx].idx + 1) %
898 rtlpci->rxringcount;
899 }
900 }
901
902 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
903 {
904 struct ieee80211_hw *hw = dev_id;
905 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
906 struct rtl_priv *rtlpriv = rtl_priv(hw);
907 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
908 unsigned long flags;
909 struct rtl_int intvec = {0};
910
911 irqreturn_t ret = IRQ_HANDLED;
912
913 if (rtlpci->irq_enabled == 0)
914 return ret;
915
916 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
917 rtlpriv->cfg->ops->disable_interrupt(hw);
918
919
920 rtlpriv->cfg->ops->interrupt_recognized(hw, &intvec);
921
922
923 if (!intvec.inta || intvec.inta == 0xffff)
924 goto done;
925
926
927 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK])
928 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
929 "beacon ok interrupt!\n");
930
931 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDER]))
932 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
933 "beacon err interrupt!\n");
934
935 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BDOK])
936 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
937
938 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) {
939 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
940 "prepare beacon for interrupt!\n");
941 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
942 }
943
944
945 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
946 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
947
948 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
949 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
950 "Manage ok interrupt!\n");
951 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
952 }
953
954 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
955 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
956 "HIGH_QUEUE ok interrupt!\n");
957 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
958 }
959
960 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
961 rtlpriv->link_info.num_tx_inperiod++;
962
963 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
964 "BK Tx OK interrupt!\n");
965 _rtl_pci_tx_isr(hw, BK_QUEUE);
966 }
967
968 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
969 rtlpriv->link_info.num_tx_inperiod++;
970
971 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
972 "BE TX OK interrupt!\n");
973 _rtl_pci_tx_isr(hw, BE_QUEUE);
974 }
975
976 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
977 rtlpriv->link_info.num_tx_inperiod++;
978
979 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
980 "VI TX OK interrupt!\n");
981 _rtl_pci_tx_isr(hw, VI_QUEUE);
982 }
983
984 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
985 rtlpriv->link_info.num_tx_inperiod++;
986
987 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
988 "Vo TX OK interrupt!\n");
989 _rtl_pci_tx_isr(hw, VO_QUEUE);
990 }
991
992 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
993 if (intvec.intd & rtlpriv->cfg->maps[RTL_IMR_H2CDOK]) {
994 rtlpriv->link_info.num_tx_inperiod++;
995
996 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
997 "H2C TX OK interrupt!\n");
998 _rtl_pci_tx_isr(hw, H2C_QUEUE);
999 }
1000 }
1001
1002 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
1003 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
1004 rtlpriv->link_info.num_tx_inperiod++;
1005
1006 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1007 "CMD TX OK interrupt!\n");
1008 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
1009 }
1010 }
1011
1012
1013 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
1014 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
1015 _rtl_pci_rx_interrupt(hw);
1016 }
1017
1018 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
1019 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1020 "rx descriptor unavailable!\n");
1021 _rtl_pci_rx_interrupt(hw);
1022 }
1023
1024 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
1025 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
1026 _rtl_pci_rx_interrupt(hw);
1027 }
1028
1029
1030 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) {
1031 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) {
1032 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1033 "firmware interrupt!\n");
1034 queue_delayed_work(rtlpriv->works.rtl_wq,
1035 &rtlpriv->works.fwevt_wq, 0);
1036 }
1037 }
1038
1039
1040
1041
1042
1043
1044
1045 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE ||
1046 rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
1047 if (unlikely(intvec.inta &
1048 rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) {
1049 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1050 "hsisr interrupt!\n");
1051 _rtl_pci_hs_interrupt(hw);
1052 }
1053 }
1054
1055 if (rtlpriv->rtlhal.earlymode_enable)
1056 tasklet_schedule(&rtlpriv->works.irq_tasklet);
1057
1058 done:
1059 rtlpriv->cfg->ops->enable_interrupt(hw);
1060 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1061 return ret;
1062 }
1063
1064 static void _rtl_pci_irq_tasklet(unsigned long data)
1065 {
1066 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
1067 _rtl_pci_tx_chk_waitq(hw);
1068 }
1069
1070 static void _rtl_pci_prepare_bcn_tasklet(unsigned long data)
1071 {
1072 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
1073 struct rtl_priv *rtlpriv = rtl_priv(hw);
1074 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1075 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1076 struct rtl8192_tx_ring *ring = NULL;
1077 struct ieee80211_hdr *hdr = NULL;
1078 struct ieee80211_tx_info *info = NULL;
1079 struct sk_buff *pskb = NULL;
1080 struct rtl_tx_desc *pdesc = NULL;
1081 struct rtl_tcb_desc tcb_desc;
1082
1083 struct rtl_tx_buffer_desc *pbuffer_desc = NULL;
1084 u8 temp_one = 1;
1085 u8 *entry;
1086
1087 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
1088 ring = &rtlpci->tx_ring[BEACON_QUEUE];
1089 pskb = __skb_dequeue(&ring->queue);
1090 if (rtlpriv->use_new_trx_flow)
1091 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1092 else
1093 entry = (u8 *)(&ring->desc[ring->idx]);
1094 if (pskb) {
1095 pci_unmap_single(rtlpci->pdev,
1096 rtlpriv->cfg->ops->get_desc(
1097 hw, (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
1098 pskb->len, PCI_DMA_TODEVICE);
1099 kfree_skb(pskb);
1100 }
1101
1102
1103 pskb = ieee80211_beacon_get(hw, mac->vif);
1104 if (!pskb)
1105 return;
1106 hdr = rtl_get_hdr(pskb);
1107 info = IEEE80211_SKB_CB(pskb);
1108 pdesc = &ring->desc[0];
1109 if (rtlpriv->use_new_trx_flow)
1110 pbuffer_desc = &ring->buffer_desc[0];
1111
1112 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1113 (u8 *)pbuffer_desc, info, NULL, pskb,
1114 BEACON_QUEUE, &tcb_desc);
1115
1116 __skb_queue_tail(&ring->queue, pskb);
1117
1118 if (rtlpriv->use_new_trx_flow) {
1119 temp_one = 4;
1120 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true,
1121 HW_DESC_OWN, (u8 *)&temp_one);
1122 } else {
1123 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN,
1124 &temp_one);
1125 }
1126 }
1127
1128 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
1129 {
1130 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1131 struct rtl_priv *rtlpriv = rtl_priv(hw);
1132 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1133 u8 i;
1134 u16 desc_num;
1135
1136 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE)
1137 desc_num = TX_DESC_NUM_92E;
1138 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE)
1139 desc_num = TX_DESC_NUM_8822B;
1140 else
1141 desc_num = RT_TXDESC_NUM;
1142
1143 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1144 rtlpci->txringcount[i] = desc_num;
1145
1146
1147
1148
1149 rtlpci->txringcount[BEACON_QUEUE] = 2;
1150
1151
1152
1153
1154
1155 if (!rtl_priv(hw)->use_new_trx_flow)
1156 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
1157
1158 rtlpci->rxbuffersize = 9100;
1159 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT;
1160 }
1161
1162 static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1163 struct pci_dev *pdev)
1164 {
1165 struct rtl_priv *rtlpriv = rtl_priv(hw);
1166 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1167 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1168 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1169
1170 rtlpci->up_first_time = true;
1171 rtlpci->being_init_adapter = false;
1172
1173 rtlhal->hw = hw;
1174 rtlpci->pdev = pdev;
1175
1176
1177 _rtl_pci_init_trx_var(hw);
1178
1179
1180 mac->beacon_interval = 100;
1181
1182
1183 mac->min_space_cfg = 0;
1184 mac->max_mss_density = 0;
1185
1186 mac->current_ampdu_density = 7;
1187 mac->current_ampdu_factor = 3;
1188
1189
1190 mac->retry_short = 7;
1191 mac->retry_long = 7;
1192
1193
1194 rtlpci->acm_method = EACMWAY2_SW;
1195
1196
1197 tasklet_init(&rtlpriv->works.irq_tasklet,
1198 _rtl_pci_irq_tasklet,
1199 (unsigned long)hw);
1200 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1201 _rtl_pci_prepare_bcn_tasklet,
1202 (unsigned long)hw);
1203 INIT_WORK(&rtlpriv->works.lps_change_work,
1204 rtl_lps_change_work_callback);
1205 }
1206
1207 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1208 unsigned int prio, unsigned int entries)
1209 {
1210 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1211 struct rtl_priv *rtlpriv = rtl_priv(hw);
1212 struct rtl_tx_buffer_desc *buffer_desc;
1213 struct rtl_tx_desc *desc;
1214 dma_addr_t buffer_desc_dma, desc_dma;
1215 u32 nextdescaddress;
1216 int i;
1217
1218
1219 if (rtlpriv->use_new_trx_flow) {
1220 buffer_desc =
1221 pci_zalloc_consistent(rtlpci->pdev,
1222 sizeof(*buffer_desc) * entries,
1223 &buffer_desc_dma);
1224
1225 if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) {
1226 pr_err("Cannot allocate TX ring (prio = %d)\n",
1227 prio);
1228 return -ENOMEM;
1229 }
1230
1231 rtlpci->tx_ring[prio].buffer_desc = buffer_desc;
1232 rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma;
1233
1234 rtlpci->tx_ring[prio].cur_tx_rp = 0;
1235 rtlpci->tx_ring[prio].cur_tx_wp = 0;
1236 }
1237
1238
1239 desc = pci_zalloc_consistent(rtlpci->pdev,
1240 sizeof(*desc) * entries, &desc_dma);
1241
1242 if (!desc || (unsigned long)desc & 0xFF) {
1243 pr_err("Cannot allocate TX ring (prio = %d)\n", prio);
1244 return -ENOMEM;
1245 }
1246
1247 rtlpci->tx_ring[prio].desc = desc;
1248 rtlpci->tx_ring[prio].dma = desc_dma;
1249
1250 rtlpci->tx_ring[prio].idx = 0;
1251 rtlpci->tx_ring[prio].entries = entries;
1252 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1253
1254 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
1255 prio, desc);
1256
1257
1258 if (!rtlpriv->use_new_trx_flow) {
1259 for (i = 0; i < entries; i++) {
1260 nextdescaddress = (u32)desc_dma +
1261 ((i + 1) % entries) *
1262 sizeof(*desc);
1263
1264 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i],
1265 true,
1266 HW_DESC_TX_NEXTDESC_ADDR,
1267 (u8 *)&nextdescaddress);
1268 }
1269 }
1270 return 0;
1271 }
1272
1273 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1274 {
1275 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1276 struct rtl_priv *rtlpriv = rtl_priv(hw);
1277 int i;
1278
1279 if (rtlpriv->use_new_trx_flow) {
1280 struct rtl_rx_buffer_desc *entry = NULL;
1281
1282 rtlpci->rx_ring[rxring_idx].buffer_desc =
1283 pci_zalloc_consistent(rtlpci->pdev,
1284 sizeof(*rtlpci->rx_ring[rxring_idx].
1285 buffer_desc) *
1286 rtlpci->rxringcount,
1287 &rtlpci->rx_ring[rxring_idx].dma);
1288 if (!rtlpci->rx_ring[rxring_idx].buffer_desc ||
1289 (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) {
1290 pr_err("Cannot allocate RX ring\n");
1291 return -ENOMEM;
1292 }
1293
1294
1295 rtlpci->rx_ring[rxring_idx].idx = 0;
1296 for (i = 0; i < rtlpci->rxringcount; i++) {
1297 entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i];
1298 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
1299 rxring_idx, i))
1300 return -ENOMEM;
1301 }
1302 } else {
1303 struct rtl_rx_desc *entry = NULL;
1304 u8 tmp_one = 1;
1305
1306 rtlpci->rx_ring[rxring_idx].desc =
1307 pci_zalloc_consistent(rtlpci->pdev,
1308 sizeof(*rtlpci->rx_ring[rxring_idx].
1309 desc) * rtlpci->rxringcount,
1310 &rtlpci->rx_ring[rxring_idx].dma);
1311 if (!rtlpci->rx_ring[rxring_idx].desc ||
1312 (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) {
1313 pr_err("Cannot allocate RX ring\n");
1314 return -ENOMEM;
1315 }
1316
1317
1318 rtlpci->rx_ring[rxring_idx].idx = 0;
1319
1320 for (i = 0; i < rtlpci->rxringcount; i++) {
1321 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1322 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
1323 rxring_idx, i))
1324 return -ENOMEM;
1325 }
1326
1327 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1328 HW_DESC_RXERO, &tmp_one);
1329 }
1330 return 0;
1331 }
1332
1333 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1334 unsigned int prio)
1335 {
1336 struct rtl_priv *rtlpriv = rtl_priv(hw);
1337 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1338 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1339
1340
1341 while (skb_queue_len(&ring->queue)) {
1342 u8 *entry;
1343 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1344
1345 if (rtlpriv->use_new_trx_flow)
1346 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1347 else
1348 entry = (u8 *)(&ring->desc[ring->idx]);
1349
1350 pci_unmap_single(rtlpci->pdev,
1351 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1352 true,
1353 HW_DESC_TXBUFF_ADDR),
1354 skb->len, PCI_DMA_TODEVICE);
1355 kfree_skb(skb);
1356 ring->idx = (ring->idx + 1) % ring->entries;
1357 }
1358
1359
1360 pci_free_consistent(rtlpci->pdev,
1361 sizeof(*ring->desc) * ring->entries,
1362 ring->desc, ring->dma);
1363 ring->desc = NULL;
1364 if (rtlpriv->use_new_trx_flow) {
1365 pci_free_consistent(rtlpci->pdev,
1366 sizeof(*ring->buffer_desc) * ring->entries,
1367 ring->buffer_desc, ring->buffer_desc_dma);
1368 ring->buffer_desc = NULL;
1369 }
1370 }
1371
1372 static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1373 {
1374 struct rtl_priv *rtlpriv = rtl_priv(hw);
1375 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1376 int i;
1377
1378
1379 for (i = 0; i < rtlpci->rxringcount; i++) {
1380 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i];
1381
1382 if (!skb)
1383 continue;
1384 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb),
1385 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
1386 kfree_skb(skb);
1387 }
1388
1389
1390 if (rtlpriv->use_new_trx_flow) {
1391 pci_free_consistent(rtlpci->pdev,
1392 sizeof(*rtlpci->rx_ring[rxring_idx].
1393 buffer_desc) * rtlpci->rxringcount,
1394 rtlpci->rx_ring[rxring_idx].buffer_desc,
1395 rtlpci->rx_ring[rxring_idx].dma);
1396 rtlpci->rx_ring[rxring_idx].buffer_desc = NULL;
1397 } else {
1398 pci_free_consistent(rtlpci->pdev,
1399 sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1400 rtlpci->rxringcount,
1401 rtlpci->rx_ring[rxring_idx].desc,
1402 rtlpci->rx_ring[rxring_idx].dma);
1403 rtlpci->rx_ring[rxring_idx].desc = NULL;
1404 }
1405 }
1406
1407 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1408 {
1409 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1410 int ret;
1411 int i, rxring_idx;
1412
1413
1414
1415
1416 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1417 ret = _rtl_pci_init_rx_ring(hw, rxring_idx);
1418 if (ret)
1419 return ret;
1420 }
1421
1422 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1423 ret = _rtl_pci_init_tx_ring(hw, i, rtlpci->txringcount[i]);
1424 if (ret)
1425 goto err_free_rings;
1426 }
1427
1428 return 0;
1429
1430 err_free_rings:
1431 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1432 _rtl_pci_free_rx_ring(hw, rxring_idx);
1433
1434 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1435 if (rtlpci->tx_ring[i].desc ||
1436 rtlpci->tx_ring[i].buffer_desc)
1437 _rtl_pci_free_tx_ring(hw, i);
1438
1439 return 1;
1440 }
1441
1442 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1443 {
1444 u32 i, rxring_idx;
1445
1446
1447 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1448 _rtl_pci_free_rx_ring(hw, rxring_idx);
1449
1450
1451 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1452 _rtl_pci_free_tx_ring(hw, i);
1453
1454 return 0;
1455 }
1456
1457 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1458 {
1459 struct rtl_priv *rtlpriv = rtl_priv(hw);
1460 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1461 int i, rxring_idx;
1462 unsigned long flags;
1463 u8 tmp_one = 1;
1464 u32 bufferaddress;
1465
1466
1467 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1468
1469
1470
1471
1472 if (!rtlpriv->use_new_trx_flow &&
1473 rtlpci->rx_ring[rxring_idx].desc) {
1474 struct rtl_rx_desc *entry = NULL;
1475
1476 rtlpci->rx_ring[rxring_idx].idx = 0;
1477 for (i = 0; i < rtlpci->rxringcount; i++) {
1478 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1479 bufferaddress =
1480 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1481 false, HW_DESC_RXBUFF_ADDR);
1482 memset((u8 *)entry, 0,
1483 sizeof(*rtlpci->rx_ring
1484 [rxring_idx].desc));
1485 if (rtlpriv->use_new_trx_flow) {
1486 rtlpriv->cfg->ops->set_desc(hw,
1487 (u8 *)entry, false,
1488 HW_DESC_RX_PREPARE,
1489 (u8 *)&bufferaddress);
1490 } else {
1491 rtlpriv->cfg->ops->set_desc(hw,
1492 (u8 *)entry, false,
1493 HW_DESC_RXBUFF_ADDR,
1494 (u8 *)&bufferaddress);
1495 rtlpriv->cfg->ops->set_desc(hw,
1496 (u8 *)entry, false,
1497 HW_DESC_RXPKT_LEN,
1498 (u8 *)&rtlpci->rxbuffersize);
1499 rtlpriv->cfg->ops->set_desc(hw,
1500 (u8 *)entry, false,
1501 HW_DESC_RXOWN,
1502 (u8 *)&tmp_one);
1503 }
1504 }
1505 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1506 HW_DESC_RXERO, (u8 *)&tmp_one);
1507 }
1508 rtlpci->rx_ring[rxring_idx].idx = 0;
1509 }
1510
1511
1512
1513
1514 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1515 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1516 if (rtlpci->tx_ring[i].desc ||
1517 rtlpci->tx_ring[i].buffer_desc) {
1518 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1519
1520 while (skb_queue_len(&ring->queue)) {
1521 u8 *entry;
1522 struct sk_buff *skb =
1523 __skb_dequeue(&ring->queue);
1524 if (rtlpriv->use_new_trx_flow)
1525 entry = (u8 *)(&ring->buffer_desc
1526 [ring->idx]);
1527 else
1528 entry = (u8 *)(&ring->desc[ring->idx]);
1529
1530 pci_unmap_single(rtlpci->pdev,
1531 rtlpriv->cfg->ops->
1532 get_desc(hw, (u8 *)
1533 entry,
1534 true,
1535 HW_DESC_TXBUFF_ADDR),
1536 skb->len, PCI_DMA_TODEVICE);
1537 dev_kfree_skb_irq(skb);
1538 ring->idx = (ring->idx + 1) % ring->entries;
1539 }
1540
1541 if (rtlpriv->use_new_trx_flow) {
1542 rtlpci->tx_ring[i].cur_tx_rp = 0;
1543 rtlpci->tx_ring[i].cur_tx_wp = 0;
1544 }
1545
1546 ring->idx = 0;
1547 ring->entries = rtlpci->txringcount[i];
1548 }
1549 }
1550 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1551
1552 return 0;
1553 }
1554
1555 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1556 struct ieee80211_sta *sta,
1557 struct sk_buff *skb)
1558 {
1559 struct rtl_priv *rtlpriv = rtl_priv(hw);
1560 struct rtl_sta_info *sta_entry = NULL;
1561 u8 tid = rtl_get_tid(skb);
1562 __le16 fc = rtl_get_fc(skb);
1563
1564 if (!sta)
1565 return false;
1566 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1567
1568 if (!rtlpriv->rtlhal.earlymode_enable)
1569 return false;
1570 if (ieee80211_is_nullfunc(fc))
1571 return false;
1572 if (ieee80211_is_qos_nullfunc(fc))
1573 return false;
1574 if (ieee80211_is_pspoll(fc))
1575 return false;
1576 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1577 return false;
1578 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1579 return false;
1580 if (tid > 7)
1581 return false;
1582
1583
1584 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1585 return false;
1586
1587 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1588 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1589 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1590
1591 return true;
1592 }
1593
1594 static int rtl_pci_tx(struct ieee80211_hw *hw,
1595 struct ieee80211_sta *sta,
1596 struct sk_buff *skb,
1597 struct rtl_tcb_desc *ptcb_desc)
1598 {
1599 struct rtl_priv *rtlpriv = rtl_priv(hw);
1600 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1601 struct rtl8192_tx_ring *ring;
1602 struct rtl_tx_desc *pdesc;
1603 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL;
1604 u16 idx;
1605 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1606 unsigned long flags;
1607 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1608 __le16 fc = rtl_get_fc(skb);
1609 u8 *pda_addr = hdr->addr1;
1610 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1611 u8 own;
1612 u8 temp_one = 1;
1613
1614 if (ieee80211_is_mgmt(fc))
1615 rtl_tx_mgmt_proc(hw, skb);
1616
1617 if (rtlpriv->psc.sw_ps_enabled) {
1618 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1619 !ieee80211_has_pm(fc))
1620 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1621 }
1622
1623 rtl_action_proc(hw, skb, true);
1624
1625 if (is_multicast_ether_addr(pda_addr))
1626 rtlpriv->stats.txbytesmulticast += skb->len;
1627 else if (is_broadcast_ether_addr(pda_addr))
1628 rtlpriv->stats.txbytesbroadcast += skb->len;
1629 else
1630 rtlpriv->stats.txbytesunicast += skb->len;
1631
1632 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1633 ring = &rtlpci->tx_ring[hw_queue];
1634 if (hw_queue != BEACON_QUEUE) {
1635 if (rtlpriv->use_new_trx_flow)
1636 idx = ring->cur_tx_wp;
1637 else
1638 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1639 ring->entries;
1640 } else {
1641 idx = 0;
1642 }
1643
1644 pdesc = &ring->desc[idx];
1645 if (rtlpriv->use_new_trx_flow) {
1646 ptx_bd_desc = &ring->buffer_desc[idx];
1647 } else {
1648 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
1649 true, HW_DESC_OWN);
1650
1651 if (own == 1 && hw_queue != BEACON_QUEUE) {
1652 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1653 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1654 hw_queue, ring->idx, idx,
1655 skb_queue_len(&ring->queue));
1656
1657 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1658 flags);
1659 return skb->len;
1660 }
1661 }
1662
1663 if (rtlpriv->cfg->ops->get_available_desc &&
1664 rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) {
1665 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1666 "get_available_desc fail\n");
1667 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1668 return skb->len;
1669 }
1670
1671 if (ieee80211_is_data(fc))
1672 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1673
1674 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1675 (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc);
1676
1677 __skb_queue_tail(&ring->queue, skb);
1678
1679 if (rtlpriv->use_new_trx_flow) {
1680 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1681 HW_DESC_OWN, &hw_queue);
1682 } else {
1683 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1684 HW_DESC_OWN, &temp_one);
1685 }
1686
1687 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1688 hw_queue != BEACON_QUEUE) {
1689 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1690 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1691 hw_queue, ring->idx, idx,
1692 skb_queue_len(&ring->queue));
1693
1694 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1695 }
1696
1697 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1698
1699 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1700
1701 return 0;
1702 }
1703
1704 static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
1705 {
1706 struct rtl_priv *rtlpriv = rtl_priv(hw);
1707 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1708 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1709 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1710 u16 i = 0;
1711 int queue_id;
1712 struct rtl8192_tx_ring *ring;
1713
1714 if (mac->skip_scan)
1715 return;
1716
1717 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1718 u32 queue_len;
1719
1720 if (((queues >> queue_id) & 0x1) == 0) {
1721 queue_id--;
1722 continue;
1723 }
1724 ring = &pcipriv->dev.tx_ring[queue_id];
1725 queue_len = skb_queue_len(&ring->queue);
1726 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1727 queue_id == TXCMD_QUEUE) {
1728 queue_id--;
1729 continue;
1730 } else {
1731 msleep(20);
1732 i++;
1733 }
1734
1735
1736 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1737 is_hal_stop(rtlhal) || i >= 200)
1738 return;
1739 }
1740 }
1741
1742 static void rtl_pci_deinit(struct ieee80211_hw *hw)
1743 {
1744 struct rtl_priv *rtlpriv = rtl_priv(hw);
1745 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1746
1747 _rtl_pci_deinit_trx_ring(hw);
1748
1749 synchronize_irq(rtlpci->pdev->irq);
1750 tasklet_kill(&rtlpriv->works.irq_tasklet);
1751 cancel_work_sync(&rtlpriv->works.lps_change_work);
1752
1753 flush_workqueue(rtlpriv->works.rtl_wq);
1754 destroy_workqueue(rtlpriv->works.rtl_wq);
1755 }
1756
1757 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1758 {
1759 int err;
1760
1761 _rtl_pci_init_struct(hw, pdev);
1762
1763 err = _rtl_pci_init_trx_ring(hw);
1764 if (err) {
1765 pr_err("tx ring initialization failed\n");
1766 return err;
1767 }
1768
1769 return 0;
1770 }
1771
1772 static int rtl_pci_start(struct ieee80211_hw *hw)
1773 {
1774 struct rtl_priv *rtlpriv = rtl_priv(hw);
1775 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1776 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1777 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1778 struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
1779 struct rtl_btc_ops *btc_ops = rtlpriv->btcoexist.btc_ops;
1780
1781 int err;
1782
1783 rtl_pci_reset_trx_ring(hw);
1784
1785 rtlpci->driver_is_goingto_unload = false;
1786 if (rtlpriv->cfg->ops->get_btc_status &&
1787 rtlpriv->cfg->ops->get_btc_status()) {
1788 rtlpriv->btcoexist.btc_info.ap_num = 36;
1789 btc_ops->btc_init_variables(rtlpriv);
1790 btc_ops->btc_init_hal_vars(rtlpriv);
1791 } else if (btc_ops) {
1792 btc_ops->btc_init_variables_wifi_only(rtlpriv);
1793 }
1794
1795 err = rtlpriv->cfg->ops->hw_init(hw);
1796 if (err) {
1797 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1798 "Failed to config hardware!\n");
1799 kfree(rtlpriv->btcoexist.btc_context);
1800 kfree(rtlpriv->btcoexist.wifi_only_context);
1801 return err;
1802 }
1803 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
1804 &rtlmac->retry_long);
1805
1806 rtlpriv->cfg->ops->enable_interrupt(hw);
1807 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
1808
1809 rtl_init_rx_config(hw);
1810
1811
1812 set_hal_start(rtlhal);
1813
1814 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1815
1816 rtlpci->up_first_time = false;
1817
1818 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%s OK\n", __func__);
1819 return 0;
1820 }
1821
1822 static void rtl_pci_stop(struct ieee80211_hw *hw)
1823 {
1824 struct rtl_priv *rtlpriv = rtl_priv(hw);
1825 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1826 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1827 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1828 unsigned long flags;
1829 u8 rf_timeout = 0;
1830
1831 if (rtlpriv->cfg->ops->get_btc_status())
1832 rtlpriv->btcoexist.btc_ops->btc_halt_notify(rtlpriv);
1833
1834 if (rtlpriv->btcoexist.btc_ops)
1835 rtlpriv->btcoexist.btc_ops->btc_deinit_variables(rtlpriv);
1836
1837
1838
1839
1840 set_hal_stop(rtlhal);
1841
1842 rtlpci->driver_is_goingto_unload = true;
1843 rtlpriv->cfg->ops->disable_interrupt(hw);
1844 cancel_work_sync(&rtlpriv->works.lps_change_work);
1845
1846 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1847 while (ppsc->rfchange_inprogress) {
1848 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1849 if (rf_timeout > 100) {
1850 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1851 break;
1852 }
1853 mdelay(1);
1854 rf_timeout++;
1855 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1856 }
1857 ppsc->rfchange_inprogress = true;
1858 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1859
1860 rtlpriv->cfg->ops->hw_disable(hw);
1861
1862 if (!rtlpriv->max_fw_size)
1863 return;
1864 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1865
1866 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1867 ppsc->rfchange_inprogress = false;
1868 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1869
1870 rtl_pci_enable_aspm(hw);
1871 }
1872
1873 static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1874 struct ieee80211_hw *hw)
1875 {
1876 struct rtl_priv *rtlpriv = rtl_priv(hw);
1877 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1878 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1879 struct pci_dev *bridge_pdev = pdev->bus->self;
1880 u16 venderid;
1881 u16 deviceid;
1882 u8 revisionid;
1883 u16 irqline;
1884 u8 tmp;
1885
1886 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1887 venderid = pdev->vendor;
1888 deviceid = pdev->device;
1889 pci_read_config_byte(pdev, 0x8, &revisionid);
1890 pci_read_config_word(pdev, 0x3C, &irqline);
1891
1892
1893
1894
1895
1896
1897
1898 if (deviceid == RTL_PCI_8192SE_DID &&
1899 revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1900 return false;
1901
1902 if (deviceid == RTL_PCI_8192_DID ||
1903 deviceid == RTL_PCI_0044_DID ||
1904 deviceid == RTL_PCI_0047_DID ||
1905 deviceid == RTL_PCI_8192SE_DID ||
1906 deviceid == RTL_PCI_8174_DID ||
1907 deviceid == RTL_PCI_8173_DID ||
1908 deviceid == RTL_PCI_8172_DID ||
1909 deviceid == RTL_PCI_8171_DID) {
1910 switch (revisionid) {
1911 case RTL_PCI_REVISION_ID_8192PCIE:
1912 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1913 "8192 PCI-E is found - vid/did=%x/%x\n",
1914 venderid, deviceid);
1915 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1916 return false;
1917 case RTL_PCI_REVISION_ID_8192SE:
1918 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1919 "8192SE is found - vid/did=%x/%x\n",
1920 venderid, deviceid);
1921 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1922 break;
1923 default:
1924 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1925 "Err: Unknown device - vid/did=%x/%x\n",
1926 venderid, deviceid);
1927 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1928 break;
1929 }
1930 } else if (deviceid == RTL_PCI_8723AE_DID) {
1931 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE;
1932 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1933 "8723AE PCI-E is found - vid/did=%x/%x\n",
1934 venderid, deviceid);
1935 } else if (deviceid == RTL_PCI_8192CET_DID ||
1936 deviceid == RTL_PCI_8192CE_DID ||
1937 deviceid == RTL_PCI_8191CE_DID ||
1938 deviceid == RTL_PCI_8188CE_DID) {
1939 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1940 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1941 "8192C PCI-E is found - vid/did=%x/%x\n",
1942 venderid, deviceid);
1943 } else if (deviceid == RTL_PCI_8192DE_DID ||
1944 deviceid == RTL_PCI_8192DE_DID2) {
1945 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1946 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1947 "8192D PCI-E is found - vid/did=%x/%x\n",
1948 venderid, deviceid);
1949 } else if (deviceid == RTL_PCI_8188EE_DID) {
1950 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE;
1951 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1952 "Find adapter, Hardware type is 8188EE\n");
1953 } else if (deviceid == RTL_PCI_8723BE_DID) {
1954 rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE;
1955 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1956 "Find adapter, Hardware type is 8723BE\n");
1957 } else if (deviceid == RTL_PCI_8192EE_DID) {
1958 rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE;
1959 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1960 "Find adapter, Hardware type is 8192EE\n");
1961 } else if (deviceid == RTL_PCI_8821AE_DID) {
1962 rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE;
1963 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1964 "Find adapter, Hardware type is 8821AE\n");
1965 } else if (deviceid == RTL_PCI_8812AE_DID) {
1966 rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE;
1967 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1968 "Find adapter, Hardware type is 8812AE\n");
1969 } else if (deviceid == RTL_PCI_8822BE_DID) {
1970 rtlhal->hw_type = HARDWARE_TYPE_RTL8822BE;
1971 rtlhal->bandset = BAND_ON_BOTH;
1972 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1973 "Find adapter, Hardware type is 8822BE\n");
1974 } else {
1975 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1976 "Err: Unknown device - vid/did=%x/%x\n",
1977 venderid, deviceid);
1978
1979 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1980 }
1981
1982 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1983 if (revisionid == 0 || revisionid == 1) {
1984 if (revisionid == 0) {
1985 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1986 "Find 92DE MAC0\n");
1987 rtlhal->interfaceindex = 0;
1988 } else if (revisionid == 1) {
1989 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1990 "Find 92DE MAC1\n");
1991 rtlhal->interfaceindex = 1;
1992 }
1993 } else {
1994 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1995 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
1996 venderid, deviceid, revisionid);
1997 rtlhal->interfaceindex = 0;
1998 }
1999 }
2000
2001 switch (rtlhal->hw_type) {
2002 case HARDWARE_TYPE_RTL8192EE:
2003 case HARDWARE_TYPE_RTL8822BE:
2004
2005 rtlpriv->use_new_trx_flow = true;
2006 break;
2007
2008 default:
2009 rtlpriv->use_new_trx_flow = false;
2010 break;
2011 }
2012
2013
2014 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
2015 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
2016 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
2017
2018
2019 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
2020
2021
2022
2023 if (bridge_pdev) {
2024
2025 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
2026 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
2027 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
2028 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
2029 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2030 "Pci Bridge Vendor is found index: %d\n",
2031 tmp);
2032 break;
2033 }
2034 }
2035 }
2036
2037 if (pcipriv->ndis_adapter.pcibridge_vendor !=
2038 PCI_BRIDGE_VENDOR_UNKNOWN) {
2039 pcipriv->ndis_adapter.pcibridge_busnum =
2040 bridge_pdev->bus->number;
2041 pcipriv->ndis_adapter.pcibridge_devnum =
2042 PCI_SLOT(bridge_pdev->devfn);
2043 pcipriv->ndis_adapter.pcibridge_funcnum =
2044 PCI_FUNC(bridge_pdev->devfn);
2045 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
2046 pci_pcie_cap(bridge_pdev);
2047 pcipriv->ndis_adapter.num4bytes =
2048 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
2049
2050 rtl_pci_get_linkcontrol_field(hw);
2051
2052 if (pcipriv->ndis_adapter.pcibridge_vendor ==
2053 PCI_BRIDGE_VENDOR_AMD) {
2054 pcipriv->ndis_adapter.amd_l1_patch =
2055 rtl_pci_get_amd_l1_patch(hw);
2056 }
2057 }
2058
2059 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2060 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
2061 pcipriv->ndis_adapter.busnumber,
2062 pcipriv->ndis_adapter.devnumber,
2063 pcipriv->ndis_adapter.funcnumber,
2064 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg);
2065
2066 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2067 "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
2068 pcipriv->ndis_adapter.pcibridge_busnum,
2069 pcipriv->ndis_adapter.pcibridge_devnum,
2070 pcipriv->ndis_adapter.pcibridge_funcnum,
2071 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
2072 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
2073 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
2074 pcipriv->ndis_adapter.amd_l1_patch);
2075
2076 rtl_pci_parse_configuration(pdev, hw);
2077 list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list);
2078
2079 return true;
2080 }
2081
2082 static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw)
2083 {
2084 struct rtl_priv *rtlpriv = rtl_priv(hw);
2085 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2086 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2087 int ret;
2088
2089 ret = pci_enable_msi(rtlpci->pdev);
2090 if (ret < 0)
2091 return ret;
2092
2093 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2094 IRQF_SHARED, KBUILD_MODNAME, hw);
2095 if (ret < 0) {
2096 pci_disable_msi(rtlpci->pdev);
2097 return ret;
2098 }
2099
2100 rtlpci->using_msi = true;
2101
2102 RT_TRACE(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2103 "MSI Interrupt Mode!\n");
2104 return 0;
2105 }
2106
2107 static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw)
2108 {
2109 struct rtl_priv *rtlpriv = rtl_priv(hw);
2110 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2111 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2112 int ret;
2113
2114 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2115 IRQF_SHARED, KBUILD_MODNAME, hw);
2116 if (ret < 0)
2117 return ret;
2118
2119 rtlpci->using_msi = false;
2120 RT_TRACE(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2121 "Pin-based Interrupt Mode!\n");
2122 return 0;
2123 }
2124
2125 static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw)
2126 {
2127 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2128 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2129 int ret;
2130
2131 if (rtlpci->msi_support) {
2132 ret = rtl_pci_intr_mode_msi(hw);
2133 if (ret < 0)
2134 ret = rtl_pci_intr_mode_legacy(hw);
2135 } else {
2136 ret = rtl_pci_intr_mode_legacy(hw);
2137 }
2138 return ret;
2139 }
2140
2141 static void platform_enable_dma64(struct pci_dev *pdev, bool dma64)
2142 {
2143 u8 value;
2144
2145 pci_read_config_byte(pdev, 0x719, &value);
2146
2147
2148 if (dma64)
2149 value |= BIT(5);
2150 else
2151 value &= ~BIT(5);
2152
2153 pci_write_config_byte(pdev, 0x719, value);
2154 }
2155
2156 int rtl_pci_probe(struct pci_dev *pdev,
2157 const struct pci_device_id *id)
2158 {
2159 struct ieee80211_hw *hw = NULL;
2160
2161 struct rtl_priv *rtlpriv = NULL;
2162 struct rtl_pci_priv *pcipriv = NULL;
2163 struct rtl_pci *rtlpci;
2164 unsigned long pmem_start, pmem_len, pmem_flags;
2165 int err;
2166
2167 err = pci_enable_device(pdev);
2168 if (err) {
2169 WARN_ONCE(true, "%s : Cannot enable new PCI device\n",
2170 pci_name(pdev));
2171 return err;
2172 }
2173
2174 if (((struct rtl_hal_cfg *)id->driver_data)->mod_params->dma64 &&
2175 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
2176 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2177 WARN_ONCE(true,
2178 "Unable to obtain 64bit DMA for consistent allocations\n");
2179 err = -ENOMEM;
2180 goto fail1;
2181 }
2182
2183 platform_enable_dma64(pdev, true);
2184 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
2185 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
2186 WARN_ONCE(true,
2187 "rtlwifi: Unable to obtain 32bit DMA for consistent allocations\n");
2188 err = -ENOMEM;
2189 goto fail1;
2190 }
2191
2192 platform_enable_dma64(pdev, false);
2193 }
2194
2195 pci_set_master(pdev);
2196
2197 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
2198 sizeof(struct rtl_priv), &rtl_ops);
2199 if (!hw) {
2200 WARN_ONCE(true,
2201 "%s : ieee80211 alloc failed\n", pci_name(pdev));
2202 err = -ENOMEM;
2203 goto fail1;
2204 }
2205
2206 SET_IEEE80211_DEV(hw, &pdev->dev);
2207 pci_set_drvdata(pdev, hw);
2208
2209 rtlpriv = hw->priv;
2210 rtlpriv->hw = hw;
2211 pcipriv = (void *)rtlpriv->priv;
2212 pcipriv->dev.pdev = pdev;
2213 init_completion(&rtlpriv->firmware_loading_complete);
2214
2215 rtlpriv->proximity.proxim_on = false;
2216
2217 pcipriv = (void *)rtlpriv->priv;
2218 pcipriv->dev.pdev = pdev;
2219
2220
2221 rtlpriv->rtlhal.interface = INTF_PCI;
2222 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
2223 rtlpriv->intf_ops = &rtl_pci_ops;
2224 rtlpriv->glb_var = &rtl_global_var;
2225 rtl_efuse_ops_init(hw);
2226
2227
2228 err = pci_request_regions(pdev, KBUILD_MODNAME);
2229 if (err) {
2230 WARN_ONCE(true, "rtlwifi: Can't obtain PCI resources\n");
2231 goto fail1;
2232 }
2233
2234 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
2235 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
2236 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
2237
2238
2239 rtlpriv->io.pci_mem_start =
2240 (unsigned long)pci_iomap(pdev,
2241 rtlpriv->cfg->bar_id, pmem_len);
2242 if (rtlpriv->io.pci_mem_start == 0) {
2243 WARN_ONCE(true, "rtlwifi: Can't map PCI mem\n");
2244 err = -ENOMEM;
2245 goto fail2;
2246 }
2247
2248 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2249 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
2250 pmem_start, pmem_len, pmem_flags,
2251 rtlpriv->io.pci_mem_start);
2252
2253
2254 pci_write_config_byte(pdev, 0x81, 0);
2255
2256 pci_write_config_byte(pdev, 0x44, 0);
2257 pci_write_config_byte(pdev, 0x04, 0x06);
2258 pci_write_config_byte(pdev, 0x04, 0x07);
2259
2260
2261 if (!_rtl_pci_find_adapter(pdev, hw)) {
2262 err = -ENODEV;
2263 goto fail2;
2264 }
2265
2266
2267 _rtl_pci_io_handler_init(&pdev->dev, hw);
2268
2269
2270 rtlpriv->cfg->ops->read_eeprom_info(hw);
2271
2272 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
2273 pr_err("Can't init_sw_vars\n");
2274 err = -ENODEV;
2275 goto fail3;
2276 }
2277 rtlpriv->cfg->ops->init_sw_leds(hw);
2278
2279
2280 rtl_pci_init_aspm(hw);
2281
2282
2283 err = rtl_init_core(hw);
2284 if (err) {
2285 pr_err("Can't allocate sw for mac80211\n");
2286 goto fail3;
2287 }
2288
2289
2290 err = rtl_pci_init(hw, pdev);
2291 if (err) {
2292 pr_err("Failed to init PCI\n");
2293 goto fail3;
2294 }
2295
2296 err = ieee80211_register_hw(hw);
2297 if (err) {
2298 pr_err("Can't register mac80211 hw.\n");
2299 err = -ENODEV;
2300 goto fail3;
2301 }
2302 rtlpriv->mac80211.mac80211_registered = 1;
2303
2304
2305 rtl_debug_add_one(hw);
2306
2307
2308 rtl_init_rfkill(hw);
2309
2310 rtlpci = rtl_pcidev(pcipriv);
2311 err = rtl_pci_intr_mode_decide(hw);
2312 if (err) {
2313 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2314 "%s: failed to register IRQ handler\n",
2315 wiphy_name(hw->wiphy));
2316 goto fail3;
2317 }
2318 rtlpci->irq_alloc = 1;
2319
2320 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2321 return 0;
2322
2323 fail3:
2324 pci_set_drvdata(pdev, NULL);
2325 rtl_deinit_core(hw);
2326
2327 fail2:
2328 if (rtlpriv->io.pci_mem_start != 0)
2329 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2330
2331 pci_release_regions(pdev);
2332 complete(&rtlpriv->firmware_loading_complete);
2333
2334 fail1:
2335 if (hw)
2336 ieee80211_free_hw(hw);
2337 pci_disable_device(pdev);
2338
2339 return err;
2340 }
2341 EXPORT_SYMBOL(rtl_pci_probe);
2342
2343 void rtl_pci_disconnect(struct pci_dev *pdev)
2344 {
2345 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2346 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2347 struct rtl_priv *rtlpriv = rtl_priv(hw);
2348 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2349 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
2350
2351
2352 wait_for_completion(&rtlpriv->firmware_loading_complete);
2353 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2354
2355
2356 rtl_debug_remove_one(hw);
2357
2358
2359 if (rtlmac->mac80211_registered == 1) {
2360 ieee80211_unregister_hw(hw);
2361 rtlmac->mac80211_registered = 0;
2362 } else {
2363 rtl_deinit_deferred_work(hw, false);
2364 rtlpriv->intf_ops->adapter_stop(hw);
2365 }
2366 rtlpriv->cfg->ops->disable_interrupt(hw);
2367
2368
2369 rtl_deinit_rfkill(hw);
2370
2371 rtl_pci_deinit(hw);
2372 rtl_deinit_core(hw);
2373 rtlpriv->cfg->ops->deinit_sw_vars(hw);
2374
2375 if (rtlpci->irq_alloc) {
2376 free_irq(rtlpci->pdev->irq, hw);
2377 rtlpci->irq_alloc = 0;
2378 }
2379
2380 if (rtlpci->using_msi)
2381 pci_disable_msi(rtlpci->pdev);
2382
2383 list_del(&rtlpriv->list);
2384 if (rtlpriv->io.pci_mem_start != 0) {
2385 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2386 pci_release_regions(pdev);
2387 }
2388
2389 pci_disable_device(pdev);
2390
2391 rtl_pci_disable_aspm(hw);
2392
2393 pci_set_drvdata(pdev, NULL);
2394
2395 ieee80211_free_hw(hw);
2396 }
2397 EXPORT_SYMBOL(rtl_pci_disconnect);
2398
2399 #ifdef CONFIG_PM_SLEEP
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415 int rtl_pci_suspend(struct device *dev)
2416 {
2417 struct ieee80211_hw *hw = dev_get_drvdata(dev);
2418 struct rtl_priv *rtlpriv = rtl_priv(hw);
2419
2420 rtlpriv->cfg->ops->hw_suspend(hw);
2421 rtl_deinit_rfkill(hw);
2422
2423 return 0;
2424 }
2425 EXPORT_SYMBOL(rtl_pci_suspend);
2426
2427 int rtl_pci_resume(struct device *dev)
2428 {
2429 struct ieee80211_hw *hw = dev_get_drvdata(dev);
2430 struct rtl_priv *rtlpriv = rtl_priv(hw);
2431
2432 rtlpriv->cfg->ops->hw_resume(hw);
2433 rtl_init_rfkill(hw);
2434 return 0;
2435 }
2436 EXPORT_SYMBOL(rtl_pci_resume);
2437 #endif
2438
2439 const struct rtl_intf_ops rtl_pci_ops = {
2440 .read_efuse_byte = read_efuse_byte,
2441 .adapter_start = rtl_pci_start,
2442 .adapter_stop = rtl_pci_stop,
2443 .check_buddy_priv = rtl_pci_check_buddy_priv,
2444 .adapter_tx = rtl_pci_tx,
2445 .flush = rtl_pci_flush,
2446 .reset_trx_ring = rtl_pci_reset_trx_ring,
2447 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
2448
2449 .disable_aspm = rtl_pci_disable_aspm,
2450 .enable_aspm = rtl_pci_enable_aspm,
2451 };