1
2
3
4 #ifndef __RTL8821AE_DEF_H__
5 #define __RTL8821AE_DEF_H__
6
7
8 #define USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN 1
9
10
11
12 #define MGN_1M 0x02
13 #define MGN_2M 0x04
14 #define MGN_5_5M 0x0b
15 #define MGN_11M 0x16
16
17 #define MGN_6M 0x0c
18 #define MGN_9M 0x12
19 #define MGN_12M 0x18
20 #define MGN_18M 0x24
21 #define MGN_24M 0x30
22 #define MGN_36M 0x48
23 #define MGN_48M 0x60
24 #define MGN_54M 0x6c
25
26
27 #define MGN_MCS0 0x80
28 #define MGN_MCS1 0x81
29 #define MGN_MCS2 0x82
30 #define MGN_MCS3 0x83
31 #define MGN_MCS4 0x84
32 #define MGN_MCS5 0x85
33 #define MGN_MCS6 0x86
34 #define MGN_MCS7 0x87
35 #define MGN_MCS8 0x88
36 #define MGN_MCS9 0x89
37 #define MGN_MCS10 0x8a
38 #define MGN_MCS11 0x8b
39 #define MGN_MCS12 0x8c
40 #define MGN_MCS13 0x8d
41 #define MGN_MCS14 0x8e
42 #define MGN_MCS15 0x8f
43
44 #define MGN_VHT1SS_MCS0 0x90
45 #define MGN_VHT1SS_MCS1 0x91
46 #define MGN_VHT1SS_MCS2 0x92
47 #define MGN_VHT1SS_MCS3 0x93
48 #define MGN_VHT1SS_MCS4 0x94
49 #define MGN_VHT1SS_MCS5 0x95
50 #define MGN_VHT1SS_MCS6 0x96
51 #define MGN_VHT1SS_MCS7 0x97
52 #define MGN_VHT1SS_MCS8 0x98
53 #define MGN_VHT1SS_MCS9 0x99
54 #define MGN_VHT2SS_MCS0 0x9a
55 #define MGN_VHT2SS_MCS1 0x9b
56 #define MGN_VHT2SS_MCS2 0x9c
57 #define MGN_VHT2SS_MCS3 0x9d
58 #define MGN_VHT2SS_MCS4 0x9e
59 #define MGN_VHT2SS_MCS5 0x9f
60 #define MGN_VHT2SS_MCS6 0xa0
61 #define MGN_VHT2SS_MCS7 0xa1
62 #define MGN_VHT2SS_MCS8 0xa2
63 #define MGN_VHT2SS_MCS9 0xa3
64
65 #define MGN_VHT3SS_MCS0 0xa4
66 #define MGN_VHT3SS_MCS1 0xa5
67 #define MGN_VHT3SS_MCS2 0xa6
68 #define MGN_VHT3SS_MCS3 0xa7
69 #define MGN_VHT3SS_MCS4 0xa8
70 #define MGN_VHT3SS_MCS5 0xa9
71 #define MGN_VHT3SS_MCS6 0xaa
72 #define MGN_VHT3SS_MCS7 0xab
73 #define MGN_VHT3SS_MCS8 0xac
74 #define MGN_VHT3SS_MCS9 0xad
75
76 #define MGN_MCS0_SG 0xc0
77 #define MGN_MCS1_SG 0xc1
78 #define MGN_MCS2_SG 0xc2
79 #define MGN_MCS3_SG 0xc3
80 #define MGN_MCS4_SG 0xc4
81 #define MGN_MCS5_SG 0xc5
82 #define MGN_MCS6_SG 0xc6
83 #define MGN_MCS7_SG 0xc7
84 #define MGN_MCS8_SG 0xc8
85 #define MGN_MCS9_SG 0xc9
86 #define MGN_MCS10_SG 0xca
87 #define MGN_MCS11_SG 0xcb
88 #define MGN_MCS12_SG 0xcc
89 #define MGN_MCS13_SG 0xcd
90 #define MGN_MCS14_SG 0xce
91 #define MGN_MCS15_SG 0xcf
92
93 #define MGN_UNKNOWN 0xff
94
95
96 #define WIFI_NAV_UPPER_US 30000
97 #define HAL_92C_NAV_UPPER_UNIT 128
98
99 #define MAX_RX_DMA_BUFFER_SIZE 0x3E80
100
101 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
102 #define HAL_PRIME_CHNL_OFFSET_LOWER 1
103 #define HAL_PRIME_CHNL_OFFSET_UPPER 2
104
105 #define RX_MPDU_QUEUE 0
106 #define RX_CMD_QUEUE 1
107
108 #define MAX_RX_DMA_BUFFER_SIZE_8812 0x3E80
109
110 #define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
111
112 #define CHIP_8812 BIT(2)
113 #define CHIP_8821 (BIT(0)|BIT(2))
114
115 #define CHIP_8821A (BIT(0)|BIT(2))
116 #define NORMAL_CHIP BIT(3)
117 #define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6)))
118 #define RF_TYPE_1T2R BIT(4)
119 #define RF_TYPE_2T2R BIT(5)
120 #define CHIP_VENDOR_UMC BIT(7)
121 #define B_CUT_VERSION BIT(12)
122 #define C_CUT_VERSION BIT(13)
123 #define D_CUT_VERSION ((BIT(12)|BIT(13)))
124 #define E_CUT_VERSION BIT(14)
125 #define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28))
126
127 enum version_8821ae {
128 VERSION_TEST_CHIP_1T1R_8812 = 0x0004,
129 VERSION_TEST_CHIP_2T2R_8812 = 0x0024,
130 VERSION_NORMAL_TSMC_CHIP_1T1R_8812 = 0x100c,
131 VERSION_NORMAL_TSMC_CHIP_2T2R_8812 = 0x102c,
132 VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT = 0x200c,
133 VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT = 0x202c,
134 VERSION_TEST_CHIP_8821 = 0x0005,
135 VERSION_NORMAL_TSMC_CHIP_8821 = 0x000d,
136 VERSION_NORMAL_TSMC_CHIP_8821_B_CUT = 0x100d,
137 VERSION_UNKNOWN = 0xFF,
138 };
139
140 enum vht_data_sc {
141 VHT_DATA_SC_DONOT_CARE = 0,
142 VHT_DATA_SC_20_UPPER_OF_80MHZ = 1,
143 VHT_DATA_SC_20_LOWER_OF_80MHZ = 2,
144 VHT_DATA_SC_20_UPPERST_OF_80MHZ = 3,
145 VHT_DATA_SC_20_LOWEST_OF_80MHZ = 4,
146 VHT_DATA_SC_20_RECV1 = 5,
147 VHT_DATA_SC_20_RECV2 = 6,
148 VHT_DATA_SC_20_RECV3 = 7,
149 VHT_DATA_SC_20_RECV4 = 8,
150 VHT_DATA_SC_40_UPPER_OF_80MHZ = 9,
151 VHT_DATA_SC_40_LOWER_OF_80MHZ = 10,
152 };
153
154
155 #define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2))
156 #define CHIP_TYPE_MASK BIT(3)
157 #define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6))
158 #define MANUFACTUER_MASK BIT(7)
159 #define ROM_VERSION_MASK (BIT(11)|BIT(10)|BIT(9)|BIT(8))
160 #define CUT_VERSION_MASK (BIT(15)|BIT(14)|BIT(13)|BIT(12))
161
162
163 #define GET_CVID_IC_TYPE(version) ((version) & IC_TYPE_MASK)
164 #define GET_CVID_CHIP_TYPE(version) ((version) & CHIP_TYPE_MASK)
165 #define GET_CVID_RF_TYPE(version) ((version) & RF_TYPE_MASK)
166 #define GET_CVID_MANUFACTUER(version) ((version) & MANUFACTUER_MASK)
167 #define GET_CVID_ROM_VERSION(version) ((version) & ROM_VERSION_MASK)
168 #define GET_CVID_CUT_VERSION(version) ((version) & CUT_VERSION_MASK)
169
170 #define IS_1T1R(version) ((GET_CVID_RF_TYPE(version)) ? false : true)
171 #define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)\
172 ? true : false)
173 #define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)\
174 ? true : false)
175
176 #define IS_8812_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8812) ? \
177 true : false)
178 #define IS_8821_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8821) ? \
179 true : false)
180
181 #define IS_VENDOR_8812A_TEST_CHIP(version) ((IS_8812_SERIES(version)) ? \
182 ((IS_NORMAL_CHIP(version)) ? \
183 false : true) : false)
184 #define IS_VENDOR_8812A_MP_CHIP(version) ((IS_8812_SERIES(version)) ? \
185 ((IS_NORMAL_CHIP(version)) ? \
186 true : false) : false)
187 #define IS_VENDOR_8812A_C_CUT(version) ((IS_8812_SERIES(version)) ? \
188 ((GET_CVID_CUT_VERSION(version) == \
189 C_CUT_VERSION) ? \
190 true : false) : false)
191
192 #define IS_VENDOR_8821A_TEST_CHIP(version) ((IS_8821_SERIES(version)) ? \
193 ((IS_NORMAL_CHIP(version)) ? \
194 false : true) : false)
195 #define IS_VENDOR_8821A_MP_CHIP(version) ((IS_8821_SERIES(version)) ? \
196 ((IS_NORMAL_CHIP(version)) ? \
197 true : false) : false)
198 #define IS_VENDOR_8821A_B_CUT(version) ((IS_8821_SERIES(version)) ? \
199 ((GET_CVID_CUT_VERSION(version) == \
200 B_CUT_VERSION) ? \
201 true : false) : false)
202 enum board_type {
203 ODM_BOARD_DEFAULT = 0,
204 ODM_BOARD_MINICARD = BIT(0),
205 ODM_BOARD_SLIM = BIT(1),
206 ODM_BOARD_BT = BIT(2),
207 ODM_BOARD_EXT_PA = BIT(3),
208 ODM_BOARD_EXT_LNA = BIT(4),
209 ODM_BOARD_EXT_TRSW = BIT(5),
210 ODM_BOARD_EXT_PA_5G = BIT(6),
211 ODM_BOARD_EXT_LNA_5G = BIT(7),
212 };
213
214 enum rf_optype {
215 RF_OP_BY_SW_3WIRE = 0,
216 RF_OP_BY_FW,
217 RF_OP_MAX
218 };
219
220 enum rf_power_state {
221 RF_ON,
222 RF_OFF,
223 RF_SLEEP,
224 RF_SHUT_DOWN,
225 };
226
227 enum power_save_mode {
228 POWER_SAVE_MODE_ACTIVE,
229 POWER_SAVE_MODE_SAVE,
230 };
231
232 enum power_polocy_config {
233 POWERCFG_MAX_POWER_SAVINGS,
234 POWERCFG_GLOBAL_POWER_SAVINGS,
235 POWERCFG_LOCAL_POWER_SAVINGS,
236 POWERCFG_LENOVO,
237 };
238
239 enum interface_select_pci {
240 INTF_SEL1_MINICARD = 0,
241 INTF_SEL0_PCIE = 1,
242 INTF_SEL2_RSV = 2,
243 INTF_SEL3_RSV = 3,
244 };
245
246 enum rtl_desc_qsel {
247 QSLT_BK = 0x2,
248 QSLT_BE = 0x0,
249 QSLT_VI = 0x5,
250 QSLT_VO = 0x7,
251 QSLT_BEACON = 0x10,
252 QSLT_HIGH = 0x11,
253 QSLT_MGNT = 0x12,
254 QSLT_CMD = 0x13,
255 };
256
257 struct phy_sts_cck_8821ae_t {
258 u8 adc_pwdb_X[4];
259 u8 sq_rpt;
260 u8 cck_agc_rpt;
261 };
262
263 struct h2c_cmd_8821ae {
264 u8 element_id;
265 u32 cmd_len;
266 u8 *p_cmdbuffer;
267 };
268
269 #endif