root/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/reg.h

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INCLUDED FROM


   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright(c) 2009-2010  Realtek Corporation.*/
   3 
   4 #ifndef __RTL8821AE_REG_H__
   5 #define __RTL8821AE_REG_H__
   6 
   7 #define TXPKT_BUF_SELECT                        0x69
   8 #define RXPKT_BUF_SELECT                        0xA5
   9 #define DISABLE_TRXPKT_BUF_ACCESS               0x0
  10 
  11 #define REG_SYS_ISO_CTRL                        0x0000
  12 #define REG_SYS_FUNC_EN                         0x0002
  13 #define REG_APS_FSMCO                           0x0004
  14 #define REG_SYS_CLKR                            0x0008
  15 #define REG_9346CR                              0x000A
  16 #define REG_EE_VPD                              0x000C
  17 #define REG_AFE_MISC                            0x0010
  18 #define REG_SPS0_CTRL                           0x0011
  19 #define REG_SPS_OCP_CFG                         0x0018
  20 #define REG_RSV_CTRL                            0x001C
  21 #define REG_RF_CTRL                             0x001F
  22 #define REG_LDOA15_CTRL                         0x0020
  23 #define REG_LDOV12D_CTRL                        0x0021
  24 #define REG_LDOHCI12_CTRL                       0x0022
  25 #define REG_LPLDO_CTRL                          0x0023
  26 #define REG_AFE_XTAL_CTRL                       0x0024
  27  /* 1.5v for 8188EE test chip, 1.4v for MP chip */
  28 #define REG_AFE_LDO_CTRL                        0x0027
  29 #define REG_AFE_PLL_CTRL                        0x0028
  30 #define REG_MAC_PHY_CTRL                        0x002c
  31 #define REG_EFUSE_CTRL                          0x0030
  32 #define REG_EFUSE_TEST                          0x0034
  33 #define REG_PWR_DATA                            0x0038
  34 #define REG_CAL_TIMER                           0x003C
  35 #define REG_ACLK_MON                            0x003E
  36 #define REG_GPIO_MUXCFG                         0x0040
  37 #define REG_GPIO_IO_SEL                         0x0042
  38 #define REG_MAC_PINMUX_CFG                      0x0043
  39 #define REG_GPIO_PIN_CTRL                       0x0044
  40 #define REG_GPIO_INTM                           0x0048
  41 #define REG_LEDCFG0                             0x004C
  42 #define REG_LEDCFG1                             0x004D
  43 #define REG_LEDCFG2                             0x004E
  44 #define REG_LEDCFG3                             0x004F
  45 #define REG_FSIMR                               0x0050
  46 #define REG_FSISR                               0x0054
  47 #define REG_HSIMR                               0x0058
  48 #define REG_HSISR                               0x005c
  49 #define REG_GPIO_PIN_CTRL_2                     0x0060
  50 #define REG_GPIO_IO_SEL_2                       0x0062
  51 #define REG_MULTI_FUNC_CTRL                     0x0068
  52 #define REG_GPIO_OUTPUT                         0x006c
  53 #define REG_OPT_CTRL                            0x0074
  54 #define REG_AFE_XTAL_CTRL_EXT                   0x0078
  55 #define REG_XCK_OUT_CTRL                        0x007c
  56 #define REG_MCUFWDL                             0x0080
  57 #define REG_WOL_EVENT                           0x0081
  58 #define REG_MCUTSTCFG                           0x0084
  59 
  60 #define REG_HIMR                                0x00B0
  61 #define REG_HISR                                0x00B4
  62 #define REG_HIMRE                               0x00B8
  63 #define REG_HISRE                               0x00BC
  64 
  65 #define REG_PMC_DBG_CTRL2                       0x00CC
  66 
  67 #define REG_EFUSE_ACCESS                        0x00CF
  68 
  69 #define REG_BIST_SCAN                           0x00D0
  70 #define REG_BIST_RPT                            0x00D4
  71 #define REG_BIST_ROM_RPT                        0x00D8
  72 #define REG_USB_SIE_INTF                        0x00E0
  73 #define REG_PCIE_MIO_INTF                       0x00E4
  74 #define REG_PCIE_MIO_INTD                       0x00E8
  75 #define REG_HPON_FSM                            0x00EC
  76 #define REG_SYS_CFG                             0x00F0
  77 #define REG_GPIO_OUTSTS                         0x00F4
  78 #define REG_MAC_PHY_CTRL_NORMAL                 0x00F8
  79 #define REG_SYS_CFG1                            0x00FC
  80 #define REG_ROM_VERSION                         0x00FD
  81 
  82 #define REG_CR                                  0x0100
  83 #define REG_PBP                                 0x0104
  84 #define REG_PKT_BUFF_ACCESS_CTRL                0x0106
  85 #define REG_TRXDMA_CTRL                         0x010C
  86 #define REG_TRXFF_BNDY                          0x0114
  87 #define REG_TRXFF_STATUS                        0x0118
  88 #define REG_RXFF_PTR                            0x011C
  89 
  90 #define REG_CPWM                                0x012F
  91 #define REG_FWIMR                               0x0130
  92 #define REG_FWISR                               0x0134
  93 #define REG_FTISR                               0x013C
  94 #define REG_PKTBUF_DBG_CTRL                     0x0140
  95 #define REG_PKTBUF_DBG_DATA_L                   0x0144
  96 #define REG_PKTBUF_DBG_DATA_H                   0x0148
  97 #define REG_RXPKTBUF_CTRL                       (REG_PKTBUF_DBG_CTRL+2)
  98 
  99 #define REG_TC0_CTRL                            0x0150
 100 #define REG_TC1_CTRL                            0x0154
 101 #define REG_TC2_CTRL                            0x0158
 102 #define REG_TC3_CTRL                            0x015C
 103 #define REG_TC4_CTRL                            0x0160
 104 #define REG_TCUNIT_BASE                         0x0164
 105 #define REG_MBIST_START                         0x0174
 106 #define REG_MBIST_DONE                          0x0178
 107 #define REG_MBIST_FAIL                          0x017C
 108 #define REG_32K_CTRL                            0x0194
 109 #define REG_C2HEVT_MSG_NORMAL                   0x01A0
 110 #define REG_C2HEVT_CLEAR                        0x01AF
 111 #define REG_C2HEVT_MSG_TEST                     0x01B8
 112 #define REG_MCUTST_1                            0x01c0
 113 #define REG_MCUTST_WOWLAN                       0x01C7
 114 #define REG_FMETHR                              0x01C8
 115 #define REG_HMETFR                              0x01CC
 116 #define REG_HMEBOX_0                            0x01D0
 117 #define REG_HMEBOX_1                            0x01D4
 118 #define REG_HMEBOX_2                            0x01D8
 119 #define REG_HMEBOX_3                            0x01DC
 120 
 121 #define REG_LLT_INIT                            0x01E0
 122 #define REG_BB_ACCEESS_CTRL                     0x01E8
 123 #define REG_BB_ACCESS_DATA                      0x01EC
 124 
 125 #define REG_HMEBOX_EXT_0                        0x01F0
 126 #define REG_HMEBOX_EXT_1                        0x01F4
 127 #define REG_HMEBOX_EXT_2                        0x01F8
 128 #define REG_HMEBOX_EXT_3                        0x01FC
 129 
 130 #define REG_RQPN                                0x0200
 131 #define REG_FIFOPAGE                            0x0204
 132 #define REG_TDECTRL                             0x0208
 133 #define REG_TXDMA_OFFSET_CHK                    0x020C
 134 #define REG_TXDMA_STATUS                        0x0210
 135 #define REG_RQPN_NPQ                            0x0214
 136 
 137 #define REG_RXDMA_AGG_PG_TH                     0x0280
 138  /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */
 139 #define REG_FW_UPD_RDPTR                        0x0284
 140  /* Control the RX DMA.*/
 141 #define REG_RXDMA_CONTROL                       0x0286
 142 /* The number of packets in RXPKTBUF.   */
 143 #define REG_RXPKT_NUM                           0x0287
 144 
 145 #define REG_PCIE_CTRL_REG                       0x0300
 146 #define REG_INT_MIG                             0x0304
 147 #define REG_BCNQ_DESA                           0x0308
 148 #define REG_HQ_DESA                             0x0310
 149 #define REG_MGQ_DESA                            0x0318
 150 #define REG_VOQ_DESA                            0x0320
 151 #define REG_VIQ_DESA                            0x0328
 152 #define REG_BEQ_DESA                            0x0330
 153 #define REG_BKQ_DESA                            0x0338
 154 #define REG_RX_DESA                             0x0340
 155 
 156 #define REG_DBI_WDATA                           0x0348
 157 #define REG_DBI_RDATA                           0x034C
 158 #define REG_DBI_CTRL                            0x0350
 159 #define REG_DBI_ADDR                            0x0350
 160 #define REG_DBI_FLAG                            0x0352
 161 #define REG_MDIO_WDATA                          0x0354
 162 #define REG_MDIO_RDATA                          0x0356
 163 #define REG_MDIO_CTL                            0x0358
 164 #define REG_DBG_SEL                             0x0360
 165 #define REG_PCIE_HRPWM                          0x0361
 166 #define REG_PCIE_HCPWM                          0x0363
 167 #define REG_UART_CTRL                           0x0364
 168 #define REG_WATCH_DOG                           0x0368
 169 #define REG_UART_TX_DESA                        0x0370
 170 #define REG_UART_RX_DESA                        0x0378
 171 
 172 #define REG_HDAQ_DESA_NODEF                     0x0000
 173 #define REG_CMDQ_DESA_NODEF                     0x0000
 174 
 175 #define REG_VOQ_INFORMATION                     0x0400
 176 #define REG_VIQ_INFORMATION                     0x0404
 177 #define REG_BEQ_INFORMATION                     0x0408
 178 #define REG_BKQ_INFORMATION                     0x040C
 179 #define REG_MGQ_INFORMATION                     0x0410
 180 #define REG_HGQ_INFORMATION                     0x0414
 181 #define REG_BCNQ_INFORMATION                    0x0418
 182 #define REG_TXPKT_EMPTY                         0x041A
 183 
 184 #define REG_CPU_MGQ_INFORMATION                 0x041C
 185 #define REG_FWHW_TXQ_CTRL                       0x0420
 186 #define REG_HWSEQ_CTRL                          0x0423
 187 #define REG_TXPKTBUF_BCNQ_BDNY                  0x0424
 188 #define REG_TXPKTBUF_MGQ_BDNY                   0x0425
 189 #define REG_MULTI_BCNQ_EN                       0x0426
 190 #define REG_MULTI_BCNQ_OFFSET                   0x0427
 191 #define REG_SPEC_SIFS                           0x0428
 192 #define REG_RL                                  0x042A
 193 #define REG_DARFRC                              0x0430
 194 #define REG_RARFRC                              0x0438
 195 #define REG_RRSR                                0x0440
 196 #define REG_ARFR0                               0x0444
 197 #define REG_ARFR1                               0x044C
 198 #define REG_CCK_CHECK                           0x0454
 199 #define REG_AMPDU_MAX_TIME                      0x0456
 200 #define REG_AGGLEN_LMT                          0x0458
 201 #define REG_AMPDU_MIN_SPACE                     0x045C
 202 #define REG_TXPKTBUF_WMAC_LBK_BF_HD             0x045D
 203 #define REG_FAST_EDCA_CTRL                      0x0460
 204 #define REG_RD_RESP_PKT_TH                      0x0463
 205 #define REG_INIRTS_RATE_SEL                     0x0480
 206 #define REG_INIDATA_RATE_SEL                    0x0484
 207 #define REG_ARFR2                               0x048C
 208 #define REG_ARFR3                               0x0494
 209 #define REG_POWER_STATUS                        0x04A4
 210 #define REG_POWER_STAGE1                        0x04B4
 211 #define REG_POWER_STAGE2                        0x04B8
 212 #define REG_PKT_LIFE_TIME                       0x04C0
 213 #define REG_STBC_SETTING                        0x04C4
 214 #define REG_HT_SINGLE_AMPDU                     0x04C7
 215 #define REG_PROT_MODE_CTRL                      0x04C8
 216 #define REG_MAX_AGGR_NUM                        0x04CA
 217 #define REG_BAR_MODE_CTRL                       0x04CC
 218 #define REG_RA_TRY_RATE_AGG_LMT                 0x04CF
 219 #define REG_EARLY_MODE_CONTROL                  0x04D0
 220 #define REG_NQOS_SEQ                            0x04DC
 221 #define REG_QOS_SEQ                             0x04DE
 222 #define REG_NEED_CPU_HANDLE                     0x04E0
 223 #define REG_PKT_LOSE_RPT                        0x04E1
 224 #define REG_PTCL_ERR_STATUS                     0x04E2
 225 #define REG_TX_RPT_CTRL                         0x04EC
 226 #define REG_TX_RPT_TIME                         0x04F0
 227 #define REG_DUMMY                               0x04FC
 228 
 229 #define REG_EDCA_VO_PARAM                       0x0500
 230 #define REG_EDCA_VI_PARAM                       0x0504
 231 #define REG_EDCA_BE_PARAM                       0x0508
 232 #define REG_EDCA_BK_PARAM                       0x050C
 233 #define REG_BCNTCFG                             0x0510
 234 #define REG_PIFS                                0x0512
 235 #define REG_RDG_PIFS                            0x0513
 236 #define REG_SIFS_CTX                            0x0514
 237 #define REG_SIFS_TRX                            0x0516
 238 #define REG_AGGR_BREAK_TIME                     0x051A
 239 #define REG_SLOT                                0x051B
 240 #define REG_TX_PTCL_CTRL                        0x0520
 241 #define REG_TXPAUSE                             0x0522
 242 #define REG_DIS_TXREQ_CLR                       0x0523
 243 #define REG_RD_CTRL                             0x0524
 244 #define REG_TBTT_PROHIBIT                       0x0540
 245 #define REG_RD_NAV_NXT                          0x0544
 246 #define REG_NAV_PROT_LEN                        0x0546
 247 #define REG_BCN_CTRL                            0x0550
 248 #define REG_MBID_NUM                            0x0552
 249 #define REG_DUAL_TSF_RST                        0x0553
 250 #define REG_BCN_INTERVAL                        0x0554
 251 #define REG_MBSSID_BCN_SPACE                    0x0554
 252 #define REG_DRVERLYINT                          0x0558
 253 #define REG_BCNDMATIM                           0x0559
 254 #define REG_ATIMWND                             0x055A
 255 #define REG_USTIME_TSF                          0x055C
 256 #define REG_BCN_MAX_ERR                         0x055D
 257 #define REG_RXTSF_OFFSET_CCK                    0x055E
 258 #define REG_RXTSF_OFFSET_OFDM                   0x055F
 259 #define REG_TSFTR                               0x0560
 260 #define REG_INIT_TSFTR                          0x0564
 261 #define REG_SECONDARY_CCA_CTRL                  0x0577
 262 #define REG_PSTIMER                             0x0580
 263 #define REG_TIMER0                              0x0584
 264 #define REG_TIMER1                              0x0588
 265 #define REG_ACMHWCTRL                           0x05C0
 266 #define REG_ACMRSTCTRL                          0x05C1
 267 #define REG_ACMAVG                              0x05C2
 268 #define REG_VO_ADMTIME                          0x05C4
 269 #define REG_VI_ADMTIME                          0x05C6
 270 #define REG_BE_ADMTIME                          0x05C8
 271 #define REG_EDCA_RANDOM_GEN                     0x05CC
 272 #define REG_NOA_DESC_SEL                        0x05CF
 273 #define REG_NOA_DESC_DURATION                   0x05E0
 274 #define REG_NOA_DESC_INTERVAL                   0x05E4
 275 #define REG_NOA_DESC_START                      0x05E8
 276 #define REG_NOA_DESC_COUNT                      0x05EC
 277 #define REG_SCH_TXCMD                           0x05F8
 278 
 279 #define REG_APSD_CTRL                           0x0600
 280 #define REG_BWOPMODE                            0x0603
 281 #define REG_TCR                                 0x0604
 282 #define REG_RCR                                 0x0608
 283 #define REG_RX_PKT_LIMIT                        0x060C
 284 #define REG_RX_DLK_TIME                         0x060D
 285 #define REG_RX_DRVINFO_SZ                       0x060F
 286 
 287 #define REG_MACID                               0x0610
 288 #define REG_BSSID                               0x0618
 289 #define REG_MAR                                 0x0620
 290 #define REG_MBIDCAMCFG                          0x0628
 291 
 292 #define REG_USTIME_EDCA                         0x0638
 293 #define REG_MAC_SPEC_SIFS                       0x063A
 294 #define REG_RESP_SIFS_CCK                       0x063C
 295 #define REG_RESP_SIFS_OFDM                      0x063E
 296 #define REG_ACKTO                               0x0640
 297 #define REG_CTS2TO                              0x0641
 298 #define REG_EIFS                                0x0642
 299 
 300 #define REG_NAV_CTRL                            0x0650
 301 #define REG_NAV_UPPER                           0x0652
 302 #define REG_BACAMCMD                            0x0654
 303 #define REG_BACAMCONTENT                        0x0658
 304 #define REG_LBDLY                               0x0660
 305 #define REG_FWDLY                               0x0661
 306 #define REG_RXERR_RPT                           0x0664
 307 #define REG_TRXPTCL_CTL                         0x0668
 308 
 309 #define REG_CAMCMD                              0x0670
 310 #define REG_CAMWRITE                            0x0674
 311 #define REG_CAMREAD                             0x0678
 312 #define REG_CAMDBG                              0x067C
 313 #define REG_SECCFG                              0x0680
 314 
 315 #define REG_WOW_CTRL                            0x0690
 316 #define REG_PSSTATUS                            0x0691
 317 #define REG_PS_RX_INFO                          0x0692
 318 #define REG_UAPSD_TID                           0x0693
 319 #define REG_LPNAV_CTRL                          0x0694
 320 #define REG_WKFMCAM_NUM                         0x0698
 321 #define REG_WKFMCAM_RWD                         0x069C
 322 #define REG_RXFLTMAP0                           0x06A0
 323 #define REG_RXFLTMAP1                           0x06A2
 324 #define REG_RXFLTMAP2                           0x06A4
 325 #define REG_BCN_PSR_RPT                         0x06A8
 326 #define REG_CALB32K_CTRL                        0x06AC
 327 #define REG_PKT_MON_CTRL                        0x06B4
 328 #define REG_BT_COEX_TABLE                       0x06C0
 329 #define REG_WMAC_RESP_TXINFO                    0x06D8
 330 
 331 #define REG_USB_INFO                            0xFE17
 332 #define REG_USB_SPECIAL_OPTION                  0xFE55
 333 #define REG_USB_DMA_AGG_TO                      0xFE5B
 334 #define REG_USB_AGG_TO                          0xFE5C
 335 #define REG_USB_AGG_TH                          0xFE5D
 336 
 337 #define REG_TEST_USB_TXQS                       0xFE48
 338 #define REG_TEST_SIE_VID                        0xFE60
 339 #define REG_TEST_SIE_PID                        0xFE62
 340 #define REG_TEST_SIE_OPTIONAL                   0xFE64
 341 #define REG_TEST_SIE_CHIRP_K                    0xFE65
 342 #define REG_TEST_SIE_PHY                        0xFE66
 343 #define REG_TEST_SIE_MAC_ADDR                   0xFE70
 344 #define REG_TEST_SIE_STRING                     0xFE80
 345 
 346 #define REG_NORMAL_SIE_VID                      0xFE60
 347 #define REG_NORMAL_SIE_PID                      0xFE62
 348 #define REG_NORMAL_SIE_OPTIONAL                 0xFE64
 349 #define REG_NORMAL_SIE_EP                       0xFE65
 350 #define REG_NORMAL_SIE_PHY                      0xFE68
 351 #define REG_NORMAL_SIE_MAC_ADDR                 0xFE70
 352 #define REG_NORMAL_SIE_STRING                   0xFE80
 353 
 354 #define CR9346                                  REG_9346CR
 355 #define MSR                                     (REG_CR + 2)
 356 #define ISR                                     REG_HISR
 357 #define TSFR                                    REG_TSFTR
 358 
 359 #define MACIDR0                                 REG_MACID
 360 #define MACIDR4                                 (REG_MACID + 4)
 361 
 362 #define PBP                                     REG_PBP
 363 
 364 #define IDR0                                    MACIDR0
 365 #define IDR4                                    MACIDR4
 366 
 367 #define UNUSED_REGISTER                         0x1BF
 368 #define DCAM                                    UNUSED_REGISTER
 369 #define PSR                                     UNUSED_REGISTER
 370 #define BBADDR                                  UNUSED_REGISTER
 371 #define PHYDATAR                                UNUSED_REGISTER
 372 
 373 #define INVALID_BBRF_VALUE                      0x12345678
 374 
 375 #define MAX_MSS_DENSITY_2T                      0x13
 376 #define MAX_MSS_DENSITY_1T                      0x0A
 377 
 378 #define CMDEEPROM_EN                            BIT(5)
 379 #define CMDEEPROM_SEL                           BIT(4)
 380 #define CMD9346CR_9356SEL                       BIT(4)
 381 #define AUTOLOAD_EEPROM                 (CMDEEPROM_EN|CMDEEPROM_SEL)
 382 #define AUTOLOAD_EFUSE                  CMDEEPROM_EN
 383 
 384 #define GPIOSEL_GPIO                            0
 385 #define GPIOSEL_ENBT                            BIT(5)
 386 
 387 #define GPIO_IN                         REG_GPIO_PIN_CTRL
 388 #define GPIO_OUT                        (REG_GPIO_PIN_CTRL+1)
 389 #define GPIO_IO_SEL                     (REG_GPIO_PIN_CTRL+2)
 390 #define GPIO_MOD                        (REG_GPIO_PIN_CTRL+3)
 391 
 392 /*    8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) */
 393 #define HSIMR_GPIO12_0_INT_EN                   BIT(0)
 394 #define HSIMR_SPS_OCP_INT_EN                    BIT(5)
 395 #define HSIMR_RON_INT_EN                        BIT(6)
 396 #define HSIMR_PDN_INT_EN                        BIT(7)
 397 #define HSIMR_GPIO9_INT_EN                      BIT(25)
 398 
 399 /* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */
 400 #define HSISR_GPIO12_0_INT                      BIT(0)
 401 #define HSISR_SPS_OCP_INT                       BIT(5)
 402 #define HSISR_RON_INT_EN                        BIT(6)
 403 #define HSISR_PDNINT                            BIT(7)
 404 #define HSISR_GPIO9_INT                         BIT(25)
 405 
 406 #define MSR_NOLINK                              0x00
 407 #define MSR_ADHOC                               0x01
 408 #define MSR_INFRA                               0x02
 409 #define MSR_AP                                  0x03
 410 #define MSR_MASK                                0x03
 411 
 412 #define RRSR_RSC_OFFSET                         21
 413 #define RRSR_SHORT_OFFSET                       23
 414 #define RRSR_RSC_BW_40M                         0x600000
 415 #define RRSR_RSC_UPSUBCHNL                      0x400000
 416 #define RRSR_RSC_LOWSUBCHNL                     0x200000
 417 #define RRSR_SHORT                              0x800000
 418 #define RRSR_1M                                 BIT(0)
 419 #define RRSR_2M                                 BIT(1)
 420 #define RRSR_5_5M                               BIT(2)
 421 #define RRSR_11M                                BIT(3)
 422 #define RRSR_6M                                 BIT(4)
 423 #define RRSR_9M                                 BIT(5)
 424 #define RRSR_12M                                BIT(6)
 425 #define RRSR_18M                                BIT(7)
 426 #define RRSR_24M                                BIT(8)
 427 #define RRSR_36M                                BIT(9)
 428 #define RRSR_48M                                BIT(10)
 429 #define RRSR_54M                                BIT(11)
 430 #define RRSR_MCS0                               BIT(12)
 431 #define RRSR_MCS1                               BIT(13)
 432 #define RRSR_MCS2                               BIT(14)
 433 #define RRSR_MCS3                               BIT(15)
 434 #define RRSR_MCS4                               BIT(16)
 435 #define RRSR_MCS5                               BIT(17)
 436 #define RRSR_MCS6                               BIT(18)
 437 #define RRSR_MCS7                               BIT(19)
 438 #define BRSR_ACKSHORTPMB                        BIT(23)
 439 
 440 #define RATR_1M                                 0x00000001
 441 #define RATR_2M                                 0x00000002
 442 #define RATR_55M                                0x00000004
 443 #define RATR_11M                                0x00000008
 444 #define RATR_6M                                 0x00000010
 445 #define RATR_9M                                 0x00000020
 446 #define RATR_12M                                0x00000040
 447 #define RATR_18M                                0x00000080
 448 #define RATR_24M                                0x00000100
 449 #define RATR_36M                                0x00000200
 450 #define RATR_48M                                0x00000400
 451 #define RATR_54M                                0x00000800
 452 #define RATR_MCS0                               0x00001000
 453 #define RATR_MCS1                               0x00002000
 454 #define RATR_MCS2                               0x00004000
 455 #define RATR_MCS3                               0x00008000
 456 #define RATR_MCS4                               0x00010000
 457 #define RATR_MCS5                               0x00020000
 458 #define RATR_MCS6                               0x00040000
 459 #define RATR_MCS7                               0x00080000
 460 #define RATR_MCS8                               0x00100000
 461 #define RATR_MCS9                               0x00200000
 462 #define RATR_MCS10                              0x00400000
 463 #define RATR_MCS11                              0x00800000
 464 #define RATR_MCS12                              0x01000000
 465 #define RATR_MCS13                              0x02000000
 466 #define RATR_MCS14                              0x04000000
 467 #define RATR_MCS15                              0x08000000
 468 
 469 #define RATE_1M                                 BIT(0)
 470 #define RATE_2M                                 BIT(1)
 471 #define RATE_5_5M                               BIT(2)
 472 #define RATE_11M                                BIT(3)
 473 #define RATE_6M                                 BIT(4)
 474 #define RATE_9M                                 BIT(5)
 475 #define RATE_12M                                BIT(6)
 476 #define RATE_18M                                BIT(7)
 477 #define RATE_24M                                BIT(8)
 478 #define RATE_36M                                BIT(9)
 479 #define RATE_48M                                BIT(10)
 480 #define RATE_54M                                BIT(11)
 481 #define RATE_MCS0                               BIT(12)
 482 #define RATE_MCS1                               BIT(13)
 483 #define RATE_MCS2                               BIT(14)
 484 #define RATE_MCS3                               BIT(15)
 485 #define RATE_MCS4                               BIT(16)
 486 #define RATE_MCS5                               BIT(17)
 487 #define RATE_MCS6                               BIT(18)
 488 #define RATE_MCS7                               BIT(19)
 489 #define RATE_MCS8                               BIT(20)
 490 #define RATE_MCS9                               BIT(21)
 491 #define RATE_MCS10                              BIT(22)
 492 #define RATE_MCS11                              BIT(23)
 493 #define RATE_MCS12                              BIT(24)
 494 #define RATE_MCS13                              BIT(25)
 495 #define RATE_MCS14                              BIT(26)
 496 #define RATE_MCS15                              BIT(27)
 497 
 498 #define RATE_ALL_CCK            (RATR_1M | RATR_2M | RATR_55M | RATR_11M)
 499 #define RATE_ALL_OFDM_AG        (RATR_6M | RATR_9M | RATR_12M | RATR_18M |\
 500                                 RATR_24M | RATR_36M | RATR_48M | RATR_54M)
 501 #define RATE_ALL_OFDM_1SS       (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 |\
 502                                 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 |\
 503                                 RATR_MCS6 | RATR_MCS7)
 504 #define RATE_ALL_OFDM_2SS       (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 |\
 505                                 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 |\
 506                                 RATR_MCS14 | RATR_MCS15)
 507 
 508 #define BW_OPMODE_20MHZ                         BIT(2)
 509 #define BW_OPMODE_5G                            BIT(1)
 510 #define BW_OPMODE_11J                           BIT(0)
 511 
 512 #define CAM_VALID                               BIT(15)
 513 #define CAM_NOTVALID                            0x0000
 514 #define CAM_USEDK                               BIT(5)
 515 
 516 #define CAM_NONE                                0x0
 517 #define CAM_WEP40                               0x01
 518 #define CAM_TKIP                                0x02
 519 #define CAM_AES                                 0x04
 520 #define CAM_WEP104                              0x05
 521 
 522 #define TOTAL_CAM_ENTRY                         32
 523 #define HALF_CAM_ENTRY                          16
 524 
 525 #define CAM_WRITE                               BIT(16)
 526 #define CAM_READ                                0x00000000
 527 #define CAM_POLLINIG                            BIT(31)
 528 
 529 #define SCR_USEDK                               0x01
 530 #define SCR_TXSEC_ENABLE                        0x02
 531 #define SCR_RXSEC_ENABLE                        0x04
 532 
 533 #define WOW_PMEN                                BIT(0)
 534 #define WOW_WOMEN                               BIT(1)
 535 #define WOW_MAGIC                               BIT(2)
 536 #define WOW_UWF                                 BIT(3)
 537 
 538 /*********************************************
 539 *       8188 IMR/ISR bits
 540 **********************************************/
 541 #define IMR_DISABLED                            0x0
 542 /* IMR DW0(0x0060-0063) Bit 0-31 */
 543 /* TXRPT interrupt when CCX bit of the packet is set    */
 544 #define IMR_TXCCK                               BIT(30)
 545 /* Power Save Time Out Interrupt */
 546 #define IMR_PSTIMEOUT                           BIT(29)
 547 /* When GTIMER4 expires, this bit is set to 1   */
 548 #define IMR_GTINT4                              BIT(28)
 549 /* When GTIMER3 expires, this bit is set to 1   */
 550 #define IMR_GTINT3                              BIT(27)
 551 /* Transmit Beacon0 Error                       */
 552 #define IMR_TBDER                               BIT(26)
 553 /* Transmit Beacon0 OK                  */
 554 #define IMR_TBDOK                               BIT(25)
 555 /* TSF Timer BIT32 toggle indication interrupt          */
 556 #define IMR_TSF_BIT32_TOGGLE                    BIT(24)
 557 /* Beacon DMA Interrupt 0                       */
 558 #define IMR_BCNDMAINT0                          BIT(20)
 559 /* Beacon Queue DMA OK0                 */
 560 #define IMR_BCNDOK0                             BIT(16)
 561 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
 562 #define IMR_HSISR_IND_ON_INT                    BIT(15)
 563 /* Beacon DMA Interrupt Extension for Win7                      */
 564 #define IMR_BCNDMAINT_E                         BIT(14)
 565 /* CTWidnow End or ATIM Window End */
 566 #define IMR_ATIMEND                             BIT(12)
 567 /* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1)*/
 568 #define IMR_HISR1_IND_INT                       BIT(11)
 569 /* CPU to Host Command INT Status, Write 1 clear        */
 570 #define IMR_C2HCMD                              BIT(10)
 571 /* CPU power Mode exchange INT Status, Write 1 clear    */
 572 #define IMR_CPWM2                               BIT(9)
 573 /* CPU power Mode exchange INT Status, Write 1 clear    */
 574 #define IMR_CPWM                                BIT(8)
 575 /* High Queue DMA OK    */
 576 #define IMR_HIGHDOK                             BIT(7)
 577 /* Management Queue DMA OK      */
 578 #define IMR_MGNTDOK                             BIT(6)
 579 /* AC_BK DMA OK         */
 580 #define IMR_BKDOK                               BIT(5)
 581 /* AC_BE DMA OK */
 582 #define IMR_BEDOK                               BIT(4)
 583 /* AC_VI DMA OK */
 584 #define IMR_VIDOK                               BIT(3)
 585 /* AC_VO DMA OK */
 586 #define IMR_VODOK                               BIT(2)
 587 /* Rx Descriptor Unavailable    */
 588 #define IMR_RDU                                 BIT(1)
 589 #define IMR_ROK                                 BIT(0)  /* Receive DMA OK */
 590 
 591 /* IMR DW1(0x00B4-00B7) Bit 0-31 */
 592 /* Beacon DMA Interrupt 7       */
 593 #define IMR_BCNDMAINT7                          BIT(27)
 594 /* Beacon DMA Interrupt 6               */
 595 #define IMR_BCNDMAINT6                          BIT(26)
 596 /* Beacon DMA Interrupt 5               */
 597 #define IMR_BCNDMAINT5                          BIT(25)
 598 /* Beacon DMA Interrupt 4               */
 599 #define IMR_BCNDMAINT4                          BIT(24)
 600 /* Beacon DMA Interrupt 3               */
 601 #define IMR_BCNDMAINT3                          BIT(23)
 602 /* Beacon DMA Interrupt 2               */
 603 #define IMR_BCNDMAINT2                          BIT(22)
 604 /* Beacon DMA Interrupt 1               */
 605 #define IMR_BCNDMAINT1                          BIT(21)
 606 /* Beacon Queue DMA OK Interrup 7 */
 607 #define IMR_BCNDOK7                             BIT(20)
 608 /* Beacon Queue DMA OK Interrup 6 */
 609 #define IMR_BCNDOK6                             BIT(19)
 610 /* Beacon Queue DMA OK Interrup 5 */
 611 #define IMR_BCNDOK5                             BIT(18)
 612 /* Beacon Queue DMA OK Interrup 4 */
 613 #define IMR_BCNDOK4                             BIT(17)
 614 /* Beacon Queue DMA OK Interrup 3 */
 615 #define IMR_BCNDOK3                             BIT(16)
 616 /* Beacon Queue DMA OK Interrup 2 */
 617 #define IMR_BCNDOK2                             BIT(15)
 618 /* Beacon Queue DMA OK Interrup 1 */
 619 #define IMR_BCNDOK1                             BIT(14)
 620 /* ATIM Window End Extension for Win7 */
 621 #define IMR_ATIMEND_E                           BIT(13)
 622 /* Tx Error Flag Interrupt Status, write 1 clear. */
 623 #define IMR_TXERR                               BIT(11)
 624 /* Rx Error Flag INT Status, Write 1 clear */
 625 #define IMR_RXERR                               BIT(10)
 626 /* Transmit FIFO Overflow */
 627 #define IMR_TXFOVW                              BIT(9)
 628 /* Receive FIFO Overflow */
 629 #define IMR_RXFOVW                              BIT(8)
 630 
 631 #define HWSET_MAX_SIZE                          512
 632 #define   EFUSE_MAX_SECTION                     64
 633 #define   EFUSE_REAL_CONTENT_LEN                256
 634 /* PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte.*/
 635 #define         EFUSE_OOB_PROTECT_BYTES         18
 636 
 637 #define EEPROM_DEFAULT_TSSI                     0x0
 638 #define EEPROM_DEFAULT_TXPOWERDIFF              0x0
 639 #define EEPROM_DEFAULT_CRYSTALCAP               0x5
 640 #define EEPROM_DEFAULT_BOARDTYPE                0x02
 641 #define EEPROM_DEFAULT_TXPOWER                  0x1010
 642 #define EEPROM_DEFAULT_HT2T_TXPWR               0x10
 643 
 644 #define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF      0x3
 645 #define EEPROM_DEFAULT_THERMALMETER             0x18
 646 #define EEPROM_DEFAULT_ANTTXPOWERDIFF           0x0
 647 #define EEPROM_DEFAULT_TXPWDIFF_CRYSTALCAP      0x5
 648 #define EEPROM_DEFAULT_TXPOWERLEVEL             0x22
 649 #define EEPROM_DEFAULT_HT40_2SDIFF              0x0
 650 #define EEPROM_DEFAULT_HT20_DIFF                2
 651 #define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF      0x3
 652 #define EEPROM_DEFAULT_HT40_PWRMAXOFFSET        0
 653 #define EEPROM_DEFAULT_HT20_PWRMAXOFFSET        0
 654 
 655 #define RF_OPTION1                              0x79
 656 #define RF_OPTION2                              0x7A
 657 #define RF_OPTION3                              0x7B
 658 #define RF_OPTION4                              0xC3
 659 
 660 #define EEPROM_DEFAULT_PID                      0x1234
 661 #define EEPROM_DEFAULT_VID                      0x5678
 662 #define EEPROM_DEFAULT_CUSTOMERID               0xAB
 663 #define EEPROM_DEFAULT_SUBCUSTOMERID            0xCD
 664 #define EEPROM_DEFAULT_VERSION                  0
 665 
 666 #define EEPROM_CHANNEL_PLAN_FCC                 0x0
 667 #define EEPROM_CHANNEL_PLAN_IC                  0x1
 668 #define EEPROM_CHANNEL_PLAN_ETSI                0x2
 669 #define EEPROM_CHANNEL_PLAN_SPAIN               0x3
 670 #define EEPROM_CHANNEL_PLAN_FRANCE              0x4
 671 #define EEPROM_CHANNEL_PLAN_MKK                 0x5
 672 #define EEPROM_CHANNEL_PLAN_MKK1                0x6
 673 #define EEPROM_CHANNEL_PLAN_ISRAEL              0x7
 674 #define EEPROM_CHANNEL_PLAN_TELEC               0x8
 675 #define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN       0x9
 676 #define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13       0xA
 677 #define EEPROM_CHANNEL_PLAN_NCC                 0XB
 678 #define EEPROM_CHANNEL_PLAN_BY_HW_MASK          0x80
 679 
 680 #define EEPROM_CID_DEFAULT                      0x0
 681 #define EEPROM_CID_TOSHIBA                      0x4
 682 #define EEPROM_CID_CCX                          0x10
 683 #define EEPROM_CID_QMI                          0x0D
 684 #define EEPROM_CID_WHQL                         0xFE
 685 
 686 #define RTL_EEPROM_ID                           0x8129
 687 
 688 #define EEPROM_HPON                             0x02
 689 #define EEPROM_CLK                              0x06
 690 #define EEPROM_TESTR                            0x08
 691 
 692 #define EEPROM_TXPOWERCCK                       0x10
 693 #define EEPROM_TXPOWERHT40_1S                   0x16
 694 #define EEPROM_TXPOWERHT20DIFF                  0x1B
 695 #define EEPROM_TXPOWER_OFDMDIFF                 0x1B
 696 
 697 #define EEPROM_TX_PWR_INX                       0x10
 698 
 699 #define EEPROM_CHANNELPLAN                      0XB8
 700 #define EEPROM_XTAL_8821AE                      0XB9
 701 #define EEPROM_THERMAL_METER                    0XBA
 702 #define EEPROM_IQK_LCK_88E                      0XBB
 703 
 704 #define EEPROM_RF_BOARD_OPTION                  0xC1
 705 #define EEPROM_RF_FEATURE_OPTION_88E            0xC2
 706 #define EEPROM_RF_BT_SETTING                    0xC3
 707 #define EEPROM_VERSION                          0xC4
 708 #define EEPROM_CUSTOMER_ID                      0xC5
 709 #define EEPROM_RF_ANTENNA_OPT_88E               0xC9
 710 #define EEPROM_RFE_OPTION                       0xCA
 711 
 712 #define EEPROM_MAC_ADDR                         0xD0
 713 #define EEPROM_VID                              0xD6
 714 #define EEPROM_DID                              0xD8
 715 #define EEPROM_SVID                             0xDA
 716 #define EEPROM_SMID                             0xDC
 717 
 718 #define STOPBECON                               BIT(6)
 719 #define STOPHIGHT                               BIT(5)
 720 #define STOPMGT                                 BIT(4)
 721 #define STOPVO                                  BIT(3)
 722 #define STOPVI                                  BIT(2)
 723 #define STOPBE                                  BIT(1)
 724 #define STOPBK                                  BIT(0)
 725 
 726 #define RCR_APPFCS                              BIT(31)
 727 #define RCR_APP_MIC                             BIT(30)
 728 #define RCR_APP_ICV                             BIT(29)
 729 #define RCR_APP_PHYST_RXFF                      BIT(28)
 730 #define RCR_APP_BA_SSN                          BIT(27)
 731 #define RCR_NONQOS_VHT                          BIT(26)
 732 #define RCR_ENMBID                              BIT(24)
 733 #define RCR_LSIGEN                              BIT(23)
 734 #define RCR_MFBEN                               BIT(22)
 735 #define RCR_HTC_LOC_CTRL                        BIT(14)
 736 #define RCR_AMF                                 BIT(13)
 737 #define RCR_ACF                                 BIT(12)
 738 #define RCR_ADF                                 BIT(11)
 739 #define RCR_AICV                                BIT(9)
 740 #define RCR_ACRC32                              BIT(8)
 741 #define RCR_CBSSID_BCN                          BIT(7)
 742 #define RCR_CBSSID_DATA                         BIT(6)
 743 #define RCR_CBSSID                              RCR_CBSSID_DATA
 744 #define RCR_APWRMGT                             BIT(5)
 745 #define RCR_ADD3                                BIT(4)
 746 #define RCR_AB                                  BIT(3)
 747 #define RCR_AM                                  BIT(2)
 748 #define RCR_APM                                 BIT(1)
 749 #define RCR_AAP                                 BIT(0)
 750 #define RCR_MXDMA_OFFSET                        8
 751 #define RCR_FIFO_OFFSET                         13
 752 
 753 #define RSV_CTRL                                0x001C
 754 #define RD_CTRL                                 0x0524
 755 
 756 #define REG_USB_INFO                            0xFE17
 757 #define REG_USB_SPECIAL_OPTION                  0xFE55
 758 #define REG_USB_DMA_AGG_TO                      0xFE5B
 759 #define REG_USB_AGG_TO                          0xFE5C
 760 #define REG_USB_AGG_TH                          0xFE5D
 761 
 762 #define REG_USB_VID                             0xFE60
 763 #define REG_USB_PID                             0xFE62
 764 #define REG_USB_OPTIONAL                        0xFE64
 765 #define REG_USB_CHIRP_K                         0xFE65
 766 #define REG_USB_PHY                             0xFE66
 767 #define REG_USB_MAC_ADDR                        0xFE70
 768 #define REG_USB_HRPWM                           0xFE58
 769 #define REG_USB_HCPWM                           0xFE57
 770 
 771 #define SW18_FPWM                               BIT(3)
 772 
 773 #define ISO_MD2PP                               BIT(0)
 774 #define ISO_UA2USB                              BIT(1)
 775 #define ISO_UD2CORE                             BIT(2)
 776 #define ISO_PA2PCIE                             BIT(3)
 777 #define ISO_PD2CORE                             BIT(4)
 778 #define ISO_IP2MAC                              BIT(5)
 779 #define ISO_DIOP                                BIT(6)
 780 #define ISO_DIOE                                BIT(7)
 781 #define ISO_EB2CORE                             BIT(8)
 782 #define ISO_DIOR                                BIT(9)
 783 
 784 #define PWC_EV25V                               BIT(14)
 785 #define PWC_EV12V                               BIT(15)
 786 
 787 #define FEN_BBRSTB                              BIT(0)
 788 #define FEN_BB_GLB_RSTN                         BIT(1)
 789 #define FEN_USBA                                BIT(2)
 790 #define FEN_UPLL                                BIT(3)
 791 #define FEN_USBD                                BIT(4)
 792 #define FEN_DIO_PCIE                            BIT(5)
 793 #define FEN_PCIEA                               BIT(6)
 794 #define FEN_PPLL                                BIT(7)
 795 #define FEN_PCIED                               BIT(8)
 796 #define FEN_DIOE                                BIT(9)
 797 #define FEN_CPUEN                               BIT(10)
 798 #define FEN_DCORE                               BIT(11)
 799 #define FEN_ELDR                                BIT(12)
 800 #define FEN_DIO_RF                              BIT(13)
 801 #define FEN_HWPDN                               BIT(14)
 802 #define FEN_MREGEN                              BIT(15)
 803 
 804 #define PFM_LDALL                               BIT(0)
 805 #define PFM_ALDN                                BIT(1)
 806 #define PFM_LDKP                                BIT(2)
 807 #define PFM_WOWL                                BIT(3)
 808 #define ENPDN                                   BIT(4)
 809 #define PDN_PL                                  BIT(5)
 810 #define APFM_ONMAC                              BIT(8)
 811 #define APFM_OFF                                BIT(9)
 812 #define APFM_RSM                                BIT(10)
 813 #define AFSM_HSUS                               BIT(11)
 814 #define AFSM_PCIE                               BIT(12)
 815 #define APDM_MAC                                BIT(13)
 816 #define APDM_HOST                               BIT(14)
 817 #define APDM_HPDN                               BIT(15)
 818 #define RDY_MACON                               BIT(16)
 819 #define SUS_HOST                                BIT(17)
 820 #define ROP_ALD                                 BIT(20)
 821 #define ROP_PWR                                 BIT(21)
 822 #define ROP_SPS                                 BIT(22)
 823 #define SOP_MRST                                BIT(25)
 824 #define SOP_FUSE                                BIT(26)
 825 #define SOP_ABG                                 BIT(27)
 826 #define SOP_AMB                                 BIT(28)
 827 #define SOP_RCK                                 BIT(29)
 828 #define SOP_A8M                                 BIT(30)
 829 #define XOP_BTCK                                BIT(31)
 830 
 831 #define ANAD16V_EN                              BIT(0)
 832 #define ANA8M                                   BIT(1)
 833 #define MACSLP                                  BIT(4)
 834 #define LOADER_CLK_EN                           BIT(5)
 835 #define _80M_SSC_DIS                            BIT(7)
 836 #define _80M_SSC_EN_HO                          BIT(8)
 837 #define PHY_SSC_RSTB                            BIT(9)
 838 #define SEC_CLK_EN                              BIT(10)
 839 #define MAC_CLK_EN                              BIT(11)
 840 #define SYS_CLK_EN                              BIT(12)
 841 #define RING_CLK_EN                             BIT(13)
 842 
 843 #define BOOT_FROM_EEPROM                        BIT(4)
 844 #define EEPROM_EN                               BIT(5)
 845 
 846 #define AFE_BGEN                                BIT(0)
 847 #define AFE_MBEN                                BIT(1)
 848 #define MAC_ID_EN                               BIT(7)
 849 
 850 #define WLOCK_ALL                               BIT(0)
 851 #define WLOCK_00                                BIT(1)
 852 #define WLOCK_04                                BIT(2)
 853 #define WLOCK_08                                BIT(3)
 854 #define WLOCK_40                                BIT(4)
 855 #define R_DIS_PRST_0                            BIT(5)
 856 #define R_DIS_PRST_1                            BIT(6)
 857 #define LOCK_ALL_EN                             BIT(7)
 858 
 859 #define RF_EN                                   BIT(0)
 860 #define RF_RSTB                                 BIT(1)
 861 #define RF_SDMRSTB                              BIT(2)
 862 
 863 #define LDA15_EN                                BIT(0)
 864 #define LDA15_STBY                              BIT(1)
 865 #define LDA15_OBUF                              BIT(2)
 866 #define LDA15_REG_VOS                           BIT(3)
 867 #define _LDA15_VOADJ(x)                         (((x) & 0x7) << 4)
 868 
 869 #define LDV12_EN                                BIT(0)
 870 #define LDV12_SDBY                              BIT(1)
 871 #define LPLDO_HSM                               BIT(2)
 872 #define LPLDO_LSM_DIS                           BIT(3)
 873 #define _LDV12_VADJ(x)                          (((x) & 0xF) << 4)
 874 
 875 #define XTAL_EN                                 BIT(0)
 876 #define XTAL_BSEL                               BIT(1)
 877 #define _XTAL_BOSC(x)                           (((x) & 0x3) << 2)
 878 #define _XTAL_CADJ(x)                           (((x) & 0xF) << 4)
 879 #define XTAL_GATE_USB                           BIT(8)
 880 #define _XTAL_USB_DRV(x)                        (((x) & 0x3) << 9)
 881 #define XTAL_GATE_AFE                           BIT(11)
 882 #define _XTAL_AFE_DRV(x)                        (((x) & 0x3) << 12)
 883 #define XTAL_RF_GATE                            BIT(14)
 884 #define _XTAL_RF_DRV(x)                         (((x) & 0x3) << 15)
 885 #define XTAL_GATE_DIG                           BIT(17)
 886 #define _XTAL_DIG_DRV(x)                        (((x) & 0x3) << 18)
 887 #define XTAL_BT_GATE                            BIT(20)
 888 #define _XTAL_BT_DRV(x)                         (((x) & 0x3) << 21)
 889 #define _XTAL_GPIO(x)                           (((x) & 0x7) << 23)
 890 
 891 #define CKDLY_AFE                               BIT(26)
 892 #define CKDLY_USB                               BIT(27)
 893 #define CKDLY_DIG                               BIT(28)
 894 #define CKDLY_BT                                BIT(29)
 895 
 896 #define APLL_EN                                 BIT(0)
 897 #define APLL_320_EN                             BIT(1)
 898 #define APLL_FREF_SEL                           BIT(2)
 899 #define APLL_EDGE_SEL                           BIT(3)
 900 #define APLL_WDOGB                              BIT(4)
 901 #define APLL_LPFEN                              BIT(5)
 902 
 903 #define APLL_REF_CLK_13MHZ                      0x1
 904 #define APLL_REF_CLK_19_2MHZ                    0x2
 905 #define APLL_REF_CLK_20MHZ                      0x3
 906 #define APLL_REF_CLK_25MHZ                      0x4
 907 #define APLL_REF_CLK_26MHZ                      0x5
 908 #define APLL_REF_CLK_38_4MHZ                    0x6
 909 #define APLL_REF_CLK_40MHZ                      0x7
 910 
 911 #define APLL_320EN                              BIT(14)
 912 #define APLL_80EN                               BIT(15)
 913 #define APLL_1MEN                               BIT(24)
 914 
 915 #define ALD_EN                                  BIT(18)
 916 #define EF_PD                                   BIT(19)
 917 #define EF_FLAG                                 BIT(31)
 918 
 919 #define EF_TRPT                                 BIT(7)
 920 #define LDOE25_EN                               BIT(31)
 921 
 922 #define RSM_EN                                  BIT(0)
 923 #define TIMER_EN                                BIT(4)
 924 
 925 #define TRSW0EN                                 BIT(2)
 926 #define TRSW1EN                                 BIT(3)
 927 #define EROM_EN                                 BIT(4)
 928 #define ENBT                                    BIT(5)
 929 #define ENUART                                  BIT(8)
 930 #define UART_910                                BIT(9)
 931 #define ENPMAC                                  BIT(10)
 932 #define SIC_SWRST                               BIT(11)
 933 #define ENSIC                                   BIT(12)
 934 #define SIC_23                                  BIT(13)
 935 #define ENHDP                                   BIT(14)
 936 #define SIC_LBK                                 BIT(15)
 937 
 938 #define LED0PL                                  BIT(4)
 939 #define LED1PL                                  BIT(12)
 940 #define LED0DIS                                 BIT(7)
 941 
 942 #define MCUFWDL_EN                              BIT(0)
 943 #define MCUFWDL_RDY                             BIT(1)
 944 #define FWDL_CHKSUM_RPT                         BIT(2)
 945 #define MACINI_RDY                              BIT(3)
 946 #define BBINI_RDY                               BIT(4)
 947 #define RFINI_RDY                               BIT(5)
 948 #define WINTINI_RDY                             BIT(6)
 949 #define CPRST                                   BIT(23)
 950 
 951 #define XCLK_VLD                                BIT(0)
 952 #define ACLK_VLD                                BIT(1)
 953 #define UCLK_VLD                                BIT(2)
 954 #define PCLK_VLD                                BIT(3)
 955 #define PCIRSTB                                 BIT(4)
 956 #define V15_VLD                                 BIT(5)
 957 #define TRP_B15V_EN                             BIT(7)
 958 #define SIC_IDLE                                BIT(8)
 959 #define BD_MAC2                                 BIT(9)
 960 #define BD_MAC1                                 BIT(10)
 961 #define IC_MACPHY_MODE                          BIT(11)
 962 #define VENDOR_ID                               BIT(19)
 963 #define PAD_HWPD_IDN                            BIT(22)
 964 #define TRP_VAUX_EN                             BIT(23)
 965 #define TRP_BT_EN                               BIT(24)
 966 #define BD_PKG_SEL                              BIT(25)
 967 #define BD_HCI_SEL                              BIT(26)
 968 #define TYPE_ID                                 BIT(27)
 969 
 970 #define CHIP_VER_RTL_MASK                       0xF000
 971 #define CHIP_VER_RTL_SHIFT                      12
 972 
 973 #define REG_LBMODE                              (REG_CR + 3)
 974 
 975 #define HCI_TXDMA_EN                            BIT(0)
 976 #define HCI_RXDMA_EN                            BIT(1)
 977 #define TXDMA_EN                                BIT(2)
 978 #define RXDMA_EN                                BIT(3)
 979 #define PROTOCOL_EN                             BIT(4)
 980 #define SCHEDULE_EN                             BIT(5)
 981 #define MACTXEN                                 BIT(6)
 982 #define MACRXEN                                 BIT(7)
 983 #define ENSWBCN                                 BIT(8)
 984 #define ENSEC                                   BIT(9)
 985 
 986 #define _NETTYPE(x)                             (((x) & 0x3) << 16)
 987 #define MASK_NETTYPE                            0x30000
 988 #define NT_NO_LINK                              0x0
 989 #define NT_LINK_AD_HOC                          0x1
 990 #define NT_LINK_AP                              0x2
 991 #define NT_AS_AP                                0x3
 992 
 993 #define _LBMODE(x)                              (((x) & 0xF) << 24)
 994 #define MASK_LBMODE                             0xF000000
 995 #define LOOPBACK_NORMAL                         0x0
 996 #define LOOPBACK_IMMEDIATELY                    0XB
 997 #define LOOPBACK_MAC_DELAY                      0x3
 998 #define LOOPBACK_PHY                            0x1
 999 #define LOOPBACK_DMA                            0x7
1000 
1001 #define GET_RX_PAGE_SIZE(value)         ((value) & 0xF)
1002 #define GET_TX_PAGE_SIZE(value)         (((value) & 0xF0) >> 4)
1003 #define _PSRX_MASK                              0xF
1004 #define _PSTX_MASK                              0xF0
1005 #define _PSRX(x)                                (x)
1006 #define _PSTX(x)                                ((x) << 4)
1007 
1008 #define PBP_64                                  0x0
1009 #define PBP_128                                 0x1
1010 #define PBP_256                                 0x2
1011 #define PBP_512                                 0x3
1012 #define PBP_1024                                0x4
1013 
1014 #define RXDMA_ARBBW_EN                          BIT(0)
1015 #define RXSHFT_EN                               BIT(1)
1016 #define RXDMA_AGG_EN                            BIT(2)
1017 #define QS_VO_QUEUE                             BIT(8)
1018 #define QS_VI_QUEUE                             BIT(9)
1019 #define QS_BE_QUEUE                             BIT(10)
1020 #define QS_BK_QUEUE                             BIT(11)
1021 #define QS_MANAGER_QUEUE                        BIT(12)
1022 #define QS_HIGH_QUEUE                           BIT(13)
1023 
1024 #define HQSEL_VOQ                               BIT(0)
1025 #define HQSEL_VIQ                               BIT(1)
1026 #define HQSEL_BEQ                               BIT(2)
1027 #define HQSEL_BKQ                               BIT(3)
1028 #define HQSEL_MGTQ                              BIT(4)
1029 #define HQSEL_HIQ                               BIT(5)
1030 
1031 #define _TXDMA_HIQ_MAP(x)                       (((x)&0x3) << 14)
1032 #define _TXDMA_MGQ_MAP(x)                       (((x)&0x3) << 12)
1033 #define _TXDMA_BKQ_MAP(x)                       (((x)&0x3) << 10)
1034 #define _TXDMA_BEQ_MAP(x)                       (((x)&0x3) << 8)
1035 #define _TXDMA_VIQ_MAP(x)                       (((x)&0x3) << 6)
1036 #define _TXDMA_VOQ_MAP(x)                       (((x)&0x3) << 4)
1037 
1038 #define QUEUE_LOW                               1
1039 #define QUEUE_NORMAL                            2
1040 #define QUEUE_HIGH                              3
1041 
1042 #define _LLT_NO_ACTIVE                          0x0
1043 #define _LLT_WRITE_ACCESS                       0x1
1044 #define _LLT_READ_ACCESS                        0x2
1045 
1046 #define _LLT_INIT_DATA(x)                       ((x) & 0xFF)
1047 #define _LLT_INIT_ADDR(x)                       (((x) & 0xFF) << 8)
1048 #define _LLT_OP(x)                              (((x) & 0x3) << 30)
1049 #define _LLT_OP_VALUE(x)                        (((x) >> 30) & 0x3)
1050 
1051 #define BB_WRITE_READ_MASK                      (BIT(31) | BIT(30))
1052 #define BB_WRITE_EN                             BIT(30)
1053 #define BB_READ_EN                              BIT(31)
1054 
1055 #define _HPQ(x)                         ((x) & 0xFF)
1056 #define _LPQ(x)                         (((x) & 0xFF) << 8)
1057 #define _PUBQ(x)                        (((x) & 0xFF) << 16)
1058 #define _NPQ(x)                         ((x) & 0xFF)
1059 
1060 #define HPQ_PUBLIC_DIS                          BIT(24)
1061 #define LPQ_PUBLIC_DIS                          BIT(25)
1062 #define LD_RQPN                                 BIT(31)
1063 
1064 #define BCN_VALID                               BIT(16)
1065 #define BCN_HEAD(x)                     (((x) & 0xFF) << 8)
1066 #define BCN_HEAD_MASK                           0xFF00
1067 
1068 #define BLK_DESC_NUM_SHIFT                      4
1069 #define BLK_DESC_NUM_MASK                       0xF
1070 
1071 #define DROP_DATA_EN                            BIT(9)
1072 
1073 #define EN_AMPDU_RTY_NEW                        BIT(7)
1074 
1075 #define _INIRTSMCS_SEL(x)                       ((x) & 0x3F)
1076 
1077 #define _SPEC_SIFS_CCK(x)                       ((x) & 0xFF)
1078 #define _SPEC_SIFS_OFDM(x)                      (((x) & 0xFF) << 8)
1079 
1080 #define RATE_REG_BITMAP_ALL                     0xFFFFF
1081 
1082 #define _RRSC_BITMAP(x)                         ((x) & 0xFFFFF)
1083 
1084 #define _RRSR_RSC(x)                            (((x) & 0x3) << 21)
1085 #define RRSR_RSC_RESERVED                       0x0
1086 #define RRSR_RSC_UPPER_SUBCHANNEL               0x1
1087 #define RRSR_RSC_LOWER_SUBCHANNEL               0x2
1088 #define RRSR_RSC_DUPLICATE_MODE                 0x3
1089 
1090 #define USE_SHORT_G1                            BIT(20)
1091 
1092 #define _AGGLMT_MCS0(x)                         ((x) & 0xF)
1093 #define _AGGLMT_MCS1(x)                         (((x) & 0xF) << 4)
1094 #define _AGGLMT_MCS2(x)                         (((x) & 0xF) << 8)
1095 #define _AGGLMT_MCS3(x)                         (((x) & 0xF) << 12)
1096 #define _AGGLMT_MCS4(x)                         (((x) & 0xF) << 16)
1097 #define _AGGLMT_MCS5(x)                         (((x) & 0xF) << 20)
1098 #define _AGGLMT_MCS6(x)                         (((x) & 0xF) << 24)
1099 #define _AGGLMT_MCS7(x)                         (((x) & 0xF) << 28)
1100 
1101 #define RETRY_LIMIT_SHORT_SHIFT         8
1102 #define RETRY_LIMIT_LONG_SHIFT          0
1103 
1104 #define _DARF_RC1(x)                    ((x) & 0x1F)
1105 #define _DARF_RC2(x)                    (((x) & 0x1F) << 8)
1106 #define _DARF_RC3(x)                    (((x) & 0x1F) << 16)
1107 #define _DARF_RC4(x)                    (((x) & 0x1F) << 24)
1108 #define _DARF_RC5(x)                    ((x) & 0x1F)
1109 #define _DARF_RC6(x)                    (((x) & 0x1F) << 8)
1110 #define _DARF_RC7(x)                    (((x) & 0x1F) << 16)
1111 #define _DARF_RC8(x)                    (((x) & 0x1F) << 24)
1112 
1113 #define _RARF_RC1(x)                    ((x) & 0x1F)
1114 #define _RARF_RC2(x)                    (((x) & 0x1F) << 8)
1115 #define _RARF_RC3(x)                    (((x) & 0x1F) << 16)
1116 #define _RARF_RC4(x)                    (((x) & 0x1F) << 24)
1117 #define _RARF_RC5(x)                    ((x) & 0x1F)
1118 #define _RARF_RC6(x)                    (((x) & 0x1F) << 8)
1119 #define _RARF_RC7(x)                    (((x) & 0x1F) << 16)
1120 #define _RARF_RC8(x)                    (((x) & 0x1F) << 24)
1121 
1122 #define AC_PARAM_TXOP_LIMIT_OFFSET      16
1123 #define AC_PARAM_ECW_MAX_OFFSET         12
1124 #define AC_PARAM_ECW_MIN_OFFSET         8
1125 #define AC_PARAM_AIFS_OFFSET            0
1126 
1127 #define _AIFS(x)                        (x)
1128 #define _ECW_MAX_MIN(x)                 ((x) << 8)
1129 #define _TXOP_LIMIT(x)                  ((x) << 16)
1130 
1131 #define _BCNIFS(x)                      ((x) & 0xFF)
1132 #define _BCNECW(x)                      ((((x) & 0xF)) << 8)
1133 
1134 #define _LRL(x)                         ((x) & 0x3F)
1135 #define _SRL(x)                         (((x) & 0x3F) << 8)
1136 
1137 #define _SIFS_CCK_CTX(x)                ((x) & 0xFF)
1138 #define _SIFS_CCK_TRX(x)                (((x) & 0xFF) << 8)
1139 
1140 #define _SIFS_OFDM_CTX(x)               ((x) & 0xFF)
1141 #define _SIFS_OFDM_TRX(x)               (((x) & 0xFF) << 8)
1142 
1143 #define _TBTT_PROHIBIT_HOLD(x)          (((x) & 0xFF) << 8)
1144 
1145 #define DIS_EDCA_CNT_DWN                BIT(11)
1146 
1147 #define EN_MBSSID                       BIT(1)
1148 #define EN_TXBCN_RPT                    BIT(2)
1149 #define EN_BCN_FUNCTION                 BIT(3)
1150 
1151 #define TSFTR_RST                       BIT(0)
1152 #define TSFTR1_RST                      BIT(1)
1153 
1154 #define STOP_BCNQ                       BIT(6)
1155 
1156 #define DIS_TSF_UDT0_NORMAL_CHIP        BIT(4)
1157 #define DIS_TSF_UDT0_TEST_CHIP          BIT(5)
1158 
1159 #define ACMHW_HWEN                      BIT(0)
1160 #define ACMHW_BEQEN                     BIT(1)
1161 #define ACMHW_VIQEN                     BIT(2)
1162 #define ACMHW_VOQEN                     BIT(3)
1163 #define ACMHW_BEQSTATUS                 BIT(4)
1164 #define ACMHW_VIQSTATUS                 BIT(5)
1165 #define ACMHW_VOQSTATUS                 BIT(6)
1166 
1167 #define APSDOFF                         BIT(6)
1168 #define APSDOFF_STATUS                  BIT(7)
1169 
1170 #define BW_20MHZ                        BIT(2)
1171 
1172 #define RATE_BITMAP_ALL                 0xFFFFF
1173 
1174 #define RATE_RRSR_CCK_ONLY_1M           0xFFFF1
1175 
1176 #define TSFRST                          BIT(0)
1177 #define DIS_GCLK                        BIT(1)
1178 #define PAD_SEL                         BIT(2)
1179 #define PWR_ST                          BIT(6)
1180 #define PWRBIT_OW_EN                    BIT(7)
1181 #define ACRC                            BIT(8)
1182 #define CFENDFORM                       BIT(9)
1183 #define ICV                             BIT(10)
1184 
1185 #define AAP                             BIT(0)
1186 #define APM                             BIT(1)
1187 #define AM                              BIT(2)
1188 #define AB                              BIT(3)
1189 #define ADD3                            BIT(4)
1190 #define APWRMGT                         BIT(5)
1191 #define CBSSID                          BIT(6)
1192 #define CBSSID_DATA                     BIT(6)
1193 #define CBSSID_BCN                      BIT(7)
1194 #define ACRC32                          BIT(8)
1195 #define AICV                            BIT(9)
1196 #define ADF                             BIT(11)
1197 #define ACF                             BIT(12)
1198 #define AMF                             BIT(13)
1199 #define HTC_LOC_CTRL                    BIT(14)
1200 #define UC_DATA_EN                      BIT(16)
1201 #define BM_DATA_EN                      BIT(17)
1202 #define MFBEN                           BIT(22)
1203 #define LSIGEN                          BIT(23)
1204 #define ENMBID                          BIT(24)
1205 #define APP_BASSN                       BIT(27)
1206 #define APP_PHYSTS                      BIT(28)
1207 #define APP_ICV                         BIT(29)
1208 #define APP_MIC                         BIT(30)
1209 #define APP_FCS                         BIT(31)
1210 
1211 #define _MIN_SPACE(x)                   ((x) & 0x7)
1212 #define _SHORT_GI_PADDING(x)            (((x) & 0x1F) << 3)
1213 
1214 #define RXERR_TYPE_OFDM_PPDU            0
1215 #define RXERR_TYPE_OFDM_FALSE_ALARM     1
1216 #define RXERR_TYPE_OFDM_MPDU_OK         2
1217 #define RXERR_TYPE_OFDM_MPDU_FAIL       3
1218 #define RXERR_TYPE_CCK_PPDU             4
1219 #define RXERR_TYPE_CCK_FALSE_ALARM      5
1220 #define RXERR_TYPE_CCK_MPDU_OK          6
1221 #define RXERR_TYPE_CCK_MPDU_FAIL        7
1222 #define RXERR_TYPE_HT_PPDU              8
1223 #define RXERR_TYPE_HT_FALSE_ALARM       9
1224 #define RXERR_TYPE_HT_MPDU_TOTAL        10
1225 #define RXERR_TYPE_HT_MPDU_OK           11
1226 #define RXERR_TYPE_HT_MPDU_FAIL         12
1227 #define RXERR_TYPE_RX_FULL_DROP         15
1228 
1229 #define RXERR_COUNTER_MASK              0xFFFFF
1230 #define RXERR_RPT_RST                   BIT(27)
1231 #define _RXERR_RPT_SEL(type)            ((type) << 28)
1232 
1233 #define SCR_TXUSEDK                     BIT(0)
1234 #define SCR_RXUSEDK                     BIT(1)
1235 #define SCR_TXENCENABLE                 BIT(2)
1236 #define SCR_RXDECENABLE                 BIT(3)
1237 #define SCR_SKBYA2                      BIT(4)
1238 #define SCR_NOSKMC                      BIT(5)
1239 #define SCR_TXBCUSEDK                   BIT(6)
1240 #define SCR_RXBCUSEDK                   BIT(7)
1241 
1242 #define XCLK_VLD                        BIT(0)
1243 #define ACLK_VLD                        BIT(1)
1244 #define UCLK_VLD                        BIT(2)
1245 #define PCLK_VLD                        BIT(3)
1246 #define PCIRSTB                         BIT(4)
1247 #define V15_VLD                         BIT(5)
1248 #define TRP_B15V_EN                     BIT(7)
1249 #define SIC_IDLE                        BIT(8)
1250 #define BD_MAC2                         BIT(9)
1251 #define BD_MAC1                         BIT(10)
1252 #define IC_MACPHY_MODE                  BIT(11)
1253 #define BT_FUNC                         BIT(16)
1254 #define VENDOR_ID                       BIT(19)
1255 #define PAD_HWPD_IDN                    BIT(22)
1256 #define TRP_VAUX_EN                     BIT(23)
1257 #define TRP_BT_EN                       BIT(24)
1258 #define BD_PKG_SEL                      BIT(25)
1259 #define BD_HCI_SEL                      BIT(26)
1260 #define TYPE_ID                         BIT(27)
1261 
1262 #define USB_IS_HIGH_SPEED               0
1263 #define USB_IS_FULL_SPEED               1
1264 #define USB_SPEED_MASK                  BIT(5)
1265 
1266 #define USB_NORMAL_SIE_EP_MASK          0xF
1267 #define USB_NORMAL_SIE_EP_SHIFT         4
1268 
1269 #define USB_TEST_EP_MASK                0x30
1270 #define USB_TEST_EP_SHIFT               4
1271 
1272 #define USB_AGG_EN                      BIT(3)
1273 
1274 #define MAC_ADDR_LEN                    6
1275 #define LAST_ENTRY_OF_TX_PKT_BUFFER     255
1276 
1277 #define POLLING_LLT_THRESHOLD           20
1278 #define POLLING_READY_TIMEOUT_COUNT     3000
1279 
1280 #define MAX_MSS_DENSITY_2T              0x13
1281 #define MAX_MSS_DENSITY_1T              0x0A
1282 
1283 #define EPROM_CMD_OPERATING_MODE_MASK   ((1<<7)|(1<<6))
1284 #define EPROM_CMD_CONFIG                0x3
1285 #define EPROM_CMD_LOAD                  1
1286 
1287 #define HWSET_MAX_SIZE_92S              HWSET_MAX_SIZE
1288 
1289 #define HAL_8192C_HW_GPIO_WPS_BIT       BIT(2)
1290 
1291 #define RA_LSSIWRITE_8821A              0xc90
1292 #define RB_LSSIWRITE_8821A              0xe90
1293 
1294 #define RA_PIREAD_8821A                 0xd04
1295 #define RB_PIREAD_8821A                 0xd44
1296 #define RA_SIREAD_8821A                 0xd08
1297 #define RB_SIREAD_8821A                 0xd48
1298 
1299 #define RPMAC_RESET                     0x100
1300 #define RPMAC_TXSTART                   0x104
1301 #define RPMAC_TXLEGACYSIG               0x108
1302 #define RPMAC_TXHTSIG1                  0x10c
1303 #define RPMAC_TXHTSIG2                  0x110
1304 #define RPMAC_PHYDEBUG                  0x114
1305 #define RPMAC_TXPACKETNUM               0x118
1306 #define RPMAC_TXIDLE                    0x11c
1307 #define RPMAC_TXMACHEADER0              0x120
1308 #define RPMAC_TXMACHEADER1              0x124
1309 #define RPMAC_TXMACHEADER2              0x128
1310 #define RPMAC_TXMACHEADER3              0x12c
1311 #define RPMAC_TXMACHEADER4              0x130
1312 #define RPMAC_TXMACHEADER5              0x134
1313 #define RPMAC_TXDADATYPE                0x138
1314 #define RPMAC_TXRANDOMSEED              0x13c
1315 #define RPMAC_CCKPLCPPREAMBLE           0x140
1316 #define RPMAC_CCKPLCPHEADER             0x144
1317 #define RPMAC_CCKCRC16                  0x148
1318 #define RPMAC_OFDMRXCRC32OK             0x170
1319 #define RPMAC_OFDMRXCRC32ER             0x174
1320 #define RPMAC_OFDMRXPARITYER            0x178
1321 #define RPMAC_OFDMRXCRC8ER              0x17c
1322 #define RPMAC_CCKCRXRC16ER              0x180
1323 #define RPMAC_CCKCRXRC32ER              0x184
1324 #define RPMAC_CCKCRXRC32OK              0x188
1325 #define RPMAC_TXSTATUS                  0x18c
1326 
1327 #define RFPGA0_RFMOD                    0x800
1328 
1329 #define RFPGA0_TXINFO                   0x804
1330 #define RFPGA0_PSDFUNCTION              0x808
1331 
1332 #define RFPGA0_TXGAINSTAGE              0x80c
1333 
1334 #define RFPGA0_RFTIMING1                0x810
1335 #define RFPGA0_RFTIMING2                0x814
1336 
1337 #define RFPGA0_XA_HSSIPARAMETER1        0x820
1338 #define RFPGA0_XA_HSSIPARAMETER2        0x824
1339 #define RFPGA0_XB_HSSIPARAMETER1        0x828
1340 #define RFPGA0_XB_HSSIPARAMETER2        0x82c
1341 #define RCCAONSEC                       0x838
1342 
1343 #define RFPGA0_XA_LSSIPARAMETER         0x840
1344 #define RFPGA0_XB_LSSIPARAMETER         0x844
1345 #define RL1PEAKTH                       0x848
1346 
1347 #define RFPGA0_RFWAKEUPPARAMETER        0x850
1348 #define RFPGA0_RFSLEEPUPPARAMETER       0x854
1349 
1350 #define RFPGA0_XAB_SWITCHCONTROL        0x858
1351 #define RFPGA0_XCD_SWITCHCONTROL        0x85c
1352 
1353 #define RFPGA0_XA_RFINTERFACEOE         0x860
1354 #define RFC_AREA                        0x860
1355 #define RFPGA0_XB_RFINTERFACEOE         0x864
1356 
1357 #define RFPGA0_XAB_RFINTERFACESW        0x870
1358 #define RFPGA0_XCD_RFINTERFACESW        0x874
1359 
1360 #define RFPGA0_XAB_RFPARAMETER          0x878
1361 #define RFPGA0_XCD_RFPARAMETER          0x87c
1362 
1363 #define RFPGA0_ANALOGPARAMETER1         0x880
1364 #define RFPGA0_ANALOGPARAMETER2         0x884
1365 #define RFPGA0_ANALOGPARAMETER3         0x888
1366 #define RFPGA0_ANALOGPARAMETER4         0x88c
1367 
1368 #define RFPGA0_XA_LSSIREADBACK          0x8a0
1369 #define RFPGA0_XB_LSSIREADBACK          0x8a4
1370 #define RFPGA0_XC_LSSIREADBACK          0x8a8
1371 #define RRFMOD                          0x8ac
1372 #define RHSSIREAD_8821AE                0x8b0
1373 
1374 #define RFPGA0_PSDREPORT                0x8b4
1375 #define TRANSCEIVEA_HSPI_READBACK       0x8b8
1376 #define TRANSCEIVEB_HSPI_READBACK       0x8bc
1377 #define RADC_BUF_CLK                    0x8c4
1378 #define RFPGA0_XAB_RFINTERFACERB        0x8e0
1379 #define RFPGA0_XCD_RFINTERFACERB        0x8e4
1380 
1381 #define RFPGA1_RFMOD                    0x900
1382 
1383 #define RFPGA1_TXBLOCK                  0x904
1384 #define RFPGA1_DEBUGSELECT              0x908
1385 #define RFPGA1_TXINFO                   0x90c
1386 
1387 #define RCCK_SYSTEM                     0xa00
1388 #define BCCK_SYSTEM                     0x10
1389 
1390 #define RCCK0_AFESETTING                0xa04
1391 #define RCCK0_CCA                       0xa08
1392 
1393 #define RCCK0_RXAGC1                    0xa0c
1394 #define RCCK0_RXAGC2                    0xa10
1395 
1396 #define RCCK0_RXHP                      0xa14
1397 
1398 #define RCCK0_DSPPARAMETER1             0xa18
1399 #define RCCK0_DSPPARAMETER2             0xa1c
1400 
1401 #define RCCK0_TXFILTER1                 0xa20
1402 #define RCCK0_TXFILTER2                 0xa24
1403 #define RCCK0_DEBUGPORT                 0xa28
1404 #define RCCK0_FALSEALARMREPORT          0xa2c
1405 #define RCCK0_TRSSIREPORT               0xa50
1406 #define RCCK0_RXREPORT                  0xa54
1407 #define RCCK0_FACOUNTERLOWER            0xa5c
1408 #define RCCK0_FACOUNTERUPPER            0xa58
1409 #define RCCK0_CCA_CNT                   0xa60
1410 
1411 /* PageB(0XB00) */
1412 #define RPDP_ANTA                       0xb00
1413 #define RPDP_ANTA_4                     0xb04
1414 #define RPDP_ANTA_8                     0xb08
1415 #define RPDP_ANTA_C                     0xb0c
1416 #define RPDP_ANTA_10                    0xb10
1417 #define RPDP_ANTA_14                    0xb14
1418 #define RPDP_ANTA_18                    0xb18
1419 #define RPDP_ANTA_1C                    0xb1c
1420 #define RPDP_ANTA_20                    0xb20
1421 #define RPDP_ANTA_24                    0xb24
1422 
1423 #define RCONFIG_PMPD_ANTA               0xb28
1424 #define RCONFIG_RAM64x16                0xb2c
1425 
1426 #define RBNDA                           0xb30
1427 #define RHSSIPAR                        0xb34
1428 
1429 #define RCONFIG_ANTA                    0xb68
1430 #define RCONFIG_ANTB                    0xb6c
1431 
1432 #define RPDP_ANTB                       0xb70
1433 #define RPDP_ANTB_4                     0xb74
1434 #define RPDP_ANTB_8                     0xb78
1435 #define RPDP_ANTB_C                     0xb7c
1436 #define RPDP_ANTB_10                    0xb80
1437 #define RPDP_ANTB_14                    0xb84
1438 #define RPDP_ANTB_18                    0xb88
1439 #define RPDP_ANTB_1C                    0xb8c
1440 #define RPDP_ANTB_20                    0xb90
1441 #define RPDP_ANTB_24                    0xb94
1442 
1443 #define RCONFIG_PMPD_ANTB               0xb98
1444 
1445 #define RBNDB                           0xba0
1446 
1447 #define RAPK                            0xbd8
1448 #define RPM_RX0_ANTA                    0xbdc
1449 #define RPM_RX1_ANTA                    0xbe0
1450 #define RPM_RX2_ANTA                    0xbe4
1451 #define RPM_RX3_ANTA                    0xbe8
1452 #define RPM_RX0_ANTB                    0xbec
1453 #define RPM_RX1_ANTB                    0xbf0
1454 #define RPM_RX2_ANTB                    0xbf4
1455 #define RPM_RX3_ANTB                    0xbf8
1456 
1457 /*RSSI Dump*/
1458 #define         RA_RSSI_DUMP            0XBF0
1459 #define         RB_RSSI_DUMP            0XBF1
1460 #define         RS1_RX_EVM_DUMP         0XBF4
1461 #define         RS2_RX_EVM_DUMP         0XBF5
1462 #define         RA_RX_SNR_DUMP          0XBF6
1463 #define         RB_RX_SNR_DUMP          0XBF7
1464 #define         RA_CFO_SHORT_DUMP       0XBF8
1465 #define         RB_CFO_SHORT_DUMP       0XBFA
1466 #define         RA_CFO_LONG_DUMP        0XBEC
1467 #define         RB_CFO_LONG_DUMP        0XBEE
1468 
1469 /*Page C*/
1470 #define ROFDM0_LSTF                     0xc00
1471 
1472 #define ROFDM0_TRXPATHENABLE            0xc04
1473 #define ROFDM0_TRMUXPAR                 0xc08
1474 #define ROFDM0_TRSWISOLATION            0xc0c
1475 
1476 #define ROFDM0_XARXAFE                  0xc10
1477 #define ROFDM0_XARXIQIMBALANCE          0xc14
1478 #define ROFDM0_XBRXAFE                  0xc18
1479 #define ROFDM0_XBRXIQIMBALANCE          0xc1c
1480 #define ROFDM0_XCRXAFE                  0xc20
1481 #define ROFDM0_XCRXIQIMBANLANCE         0xc24
1482 #define ROFDM0_XDRXAFE                  0xc28
1483 #define ROFDM0_XDRXIQIMBALANCE          0xc2c
1484 
1485 #define ROFDM0_RXDETECTOR1              0xc30
1486 #define ROFDM0_RXDETECTOR2              0xc34
1487 #define ROFDM0_RXDETECTOR3              0xc38
1488 #define ROFDM0_RXDETECTOR4              0xc3c
1489 
1490 #define ROFDM0_RXDSP                    0xc40
1491 #define ROFDM0_CFOANDDAGC               0xc44
1492 #define ROFDM0_CCADROPTHRESHOLD         0xc48
1493 #define ROFDM0_ECCATHRESHOLD            0xc4c
1494 
1495 #define ROFDM0_XAAGCCORE1               0xc50
1496 #define ROFDM0_XAAGCCORE2               0xc54
1497 #define ROFDM0_XBAGCCORE1               0xc58
1498 #define ROFDM0_XBAGCCORE2               0xc5c
1499 #define ROFDM0_XCAGCCORE1               0xc60
1500 #define ROFDM0_XCAGCCORE2               0xc64
1501 #define ROFDM0_XDAGCCORE1               0xc68
1502 #define ROFDM0_XDAGCCORE2               0xc6c
1503 
1504 #define ROFDM0_AGCPARAMETER1            0xc70
1505 #define ROFDM0_AGCPARAMETER2            0xc74
1506 #define ROFDM0_AGCRSSITABLE             0xc78
1507 #define ROFDM0_HTSTFAGC                 0xc7c
1508 
1509 #define ROFDM0_XATXIQIMBALANCE          0xc80
1510 #define ROFDM0_XATXAFE                  0xc84
1511 #define ROFDM0_XBTXIQIMBALANCE          0xc88
1512 #define ROFDM0_XBTXAFE                  0xc8c
1513 #define ROFDM0_XCTXIQIMBALANCE          0xc90
1514 #define ROFDM0_XCTXAFE                  0xc94
1515 #define ROFDM0_XDTXIQIMBALANCE          0xc98
1516 #define ROFDM0_XDTXAFE                  0xc9c
1517 
1518 #define ROFDM0_RXIQEXTANTA              0xca0
1519 #define ROFDM0_TXCOEFF1                 0xca4
1520 #define ROFDM0_TXCOEFF2                 0xca8
1521 #define ROFDM0_TXCOEFF3                 0xcac
1522 #define ROFDM0_TXCOEFF4                 0xcb0
1523 #define ROFDM0_TXCOEFF5                 0xcb4
1524 #define ROFDM0_TXCOEFF6                 0xcb8
1525 
1526 /*Path_A RFE cotrol */
1527 #define RA_RFE_CTRL_8812                0xcb8
1528 /*Path_B RFE control*/
1529 #define RB_RFE_CTRL_8812                0xeb8
1530 
1531 #define ROFDM0_RXHPPARAMETER            0xce0
1532 #define ROFDM0_TXPSEUDONOISEWGT         0xce4
1533 #define ROFDM0_FRAMESYNC                0xcf0
1534 #define ROFDM0_DFSREPORT                0xcf4
1535 
1536 #define ROFDM1_LSTF                     0xd00
1537 #define ROFDM1_TRXPATHENABLE            0xd04
1538 
1539 #define ROFDM1_CF0                      0xd08
1540 #define ROFDM1_CSI1                     0xd10
1541 #define ROFDM1_SBD                      0xd14
1542 #define ROFDM1_CSI2                     0xd18
1543 #define ROFDM1_CFOTRACKING              0xd2c
1544 #define ROFDM1_TRXMESAURE1              0xd34
1545 #define ROFDM1_INTFDET                  0xd3c
1546 #define ROFDM1_PSEUDONOISESTATEAB       0xd50
1547 #define ROFDM1_PSEUDONOISESTATECD       0xd54
1548 #define ROFDM1_RXPSEUDONOISEWGT         0xd58
1549 
1550 #define ROFDM_PHYCOUNTER1               0xda0
1551 #define ROFDM_PHYCOUNTER2               0xda4
1552 #define ROFDM_PHYCOUNTER3               0xda8
1553 
1554 #define ROFDM_SHORTCFOAB                0xdac
1555 #define ROFDM_SHORTCFOCD                0xdb0
1556 #define ROFDM_LONGCFOAB                 0xdb4
1557 #define ROFDM_LONGCFOCD                 0xdb8
1558 #define ROFDM_TAILCF0AB                 0xdbc
1559 #define ROFDM_TAILCF0CD                 0xdc0
1560 #define ROFDM_PWMEASURE1                0xdc4
1561 #define ROFDM_PWMEASURE2                0xdc8
1562 #define ROFDM_BWREPORT                  0xdcc
1563 #define ROFDM_AGCREPORT                 0xdd0
1564 #define ROFDM_RXSNR                     0xdd4
1565 #define ROFDM_RXEVMCSI                  0xdd8
1566 #define ROFDM_SIGREPORT                 0xddc
1567 
1568 #define RTXAGC_A_CCK11_CCK1             0xc20
1569 #define RTXAGC_A_OFDM18_OFDM6           0xc24
1570 #define RTXAGC_A_OFDM54_OFDM24          0xc28
1571 #define RTXAGC_A_MCS03_MCS00            0xc2c
1572 #define RTXAGC_A_MCS07_MCS04            0xc30
1573 #define RTXAGC_A_MCS11_MCS08            0xc34
1574 #define RTXAGC_A_MCS15_MCS12            0xc38
1575 #define RTXAGC_A_NSS1INDEX3_NSS1INDEX0  0xc3c
1576 #define RTXAGC_A_NSS1INDEX7_NSS1INDEX4  0xc40
1577 #define RTXAGC_A_NSS2INDEX1_NSS1INDEX8  0xc44
1578 #define RTXAGC_A_NSS2INDEX5_NSS2INDEX2  0xc48
1579 #define RTXAGC_A_NSS2INDEX9_NSS2INDEX6  0xc4c
1580 #define RTXAGC_B_CCK11_CCK1             0xe20
1581 #define RTXAGC_B_OFDM18_OFDM6           0xe24
1582 #define RTXAGC_B_OFDM54_OFDM24          0xe28
1583 #define RTXAGC_B_MCS03_MCS00            0xe2c
1584 #define RTXAGC_B_MCS07_MCS04            0xe30
1585 #define RTXAGC_B_MCS11_MCS08            0xe34
1586 #define RTXAGC_B_MCS15_MCS12            0xe38
1587 #define RTXAGC_B_NSS1INDEX3_NSS1INDEX0  0xe3c
1588 #define RTXAGC_B_NSS1INDEX7_NSS1INDEX4  0xe40
1589 #define RTXAGC_B_NSS2INDEX1_NSS1INDEX8  0xe44
1590 #define RTXAGC_B_NSS2INDEX5_NSS2INDEX2  0xe48
1591 #define RTXAGC_B_NSS2INDEX9_NSS2INDEX6  0xe4c
1592 
1593 #define RA_TXPWRTRAING                  0xc54
1594 #define RB_TXPWRTRAING                  0xe54
1595 
1596 #define RFPGA0_IQK                      0xe28
1597 #define RTX_IQK_TONE_A                  0xe30
1598 #define RRX_IQK_TONE_A                  0xe34
1599 #define RTX_IQK_PI_A                    0xe38
1600 #define RRX_IQK_PI_A                    0xe3c
1601 
1602 #define RTX_IQK                         0xe40
1603 #define RRX_IQK                         0xe44
1604 #define RIQK_AGC_PTS                    0xe48
1605 #define RIQK_AGC_RSP                    0xe4c
1606 #define RTX_IQK_TONE_B                  0xe50
1607 #define RRX_IQK_TONE_B                  0xe54
1608 #define RTX_IQK_PI_B                    0xe58
1609 #define RRX_IQK_PI_B                    0xe5c
1610 #define RIQK_AGC_CONT                   0xe60
1611 
1612 #define RBLUE_TOOTH                     0xe6c
1613 #define RRX_WAIT_CCA                    0xe70
1614 #define RTX_CCK_RFON                    0xe74
1615 #define RTX_CCK_BBON                    0xe78
1616 #define RTX_OFDM_RFON                   0xe7c
1617 #define RTX_OFDM_BBON                   0xe80
1618 #define RTX_TO_RX                       0xe84
1619 #define RTX_TO_TX                       0xe88
1620 #define RRX_CCK                         0xe8c
1621 
1622 #define RTX_POWER_BEFORE_IQK_A          0xe94
1623 #define RTX_POWER_AFTER_IQK_A           0xe9c
1624 
1625 #define RRX_POWER_BEFORE_IQK_A          0xea0
1626 #define RRX_POWER_BEFORE_IQK_A_2        0xea4
1627 #define RRX_POWER_AFTER_IQK_A           0xea8
1628 #define RRX_POWER_AFTER_IQK_A_2         0xeac
1629 
1630 #define RTX_POWER_BEFORE_IQK_B          0xeb4
1631 #define RTX_POWER_AFTER_IQK_B           0xebc
1632 
1633 #define RRX_POER_BEFORE_IQK_B           0xec0
1634 #define RRX_POER_BEFORE_IQK_B_2         0xec4
1635 #define RRX_POWER_AFTER_IQK_B           0xec8
1636 #define RRX_POWER_AFTER_IQK_B_2         0xecc
1637 
1638 #define RRX_OFDM                        0xed0
1639 #define RRX_WAIT_RIFS                   0xed4
1640 #define RRX_TO_RX                       0xed8
1641 #define RSTANDBY                        0xedc
1642 #define RSLEEP                          0xee0
1643 #define RPMPD_ANAEN                     0xeec
1644 
1645 #define RZEBRA1_HSSIENABLE              0x0
1646 #define RZEBRA1_TRXENABLE1              0x1
1647 #define RZEBRA1_TRXENABLE2              0x2
1648 #define RZEBRA1_AGC                     0x4
1649 #define RZEBRA1_CHARGEPUMP              0x5
1650 #define RZEBRA1_CHANNEL                 0x7
1651 
1652 #define RZEBRA1_TXGAIN                  0x8
1653 #define RZEBRA1_TXLPF                   0x9
1654 #define RZEBRA1_RXLPF                   0xb
1655 #define RZEBRA1_RXHPFCORNER             0xc
1656 
1657 #define RGLOBALCTRL                     0
1658 #define RRTL8256_TXLPF                  19
1659 #define RRTL8256_RXLPF                  11
1660 #define RRTL8258_TXLPF                  0x11
1661 #define RRTL8258_RXLPF                  0x13
1662 #define RRTL8258_RSSILPF                0xa
1663 
1664 #define RF_AC                           0x00
1665 
1666 #define RF_IQADJ_G1                     0x01
1667 #define RF_IQADJ_G2                     0x02
1668 #define RF_POW_TRSW                     0x05
1669 
1670 #define RF_GAIN_RX                      0x06
1671 #define RF_GAIN_TX                      0x07
1672 
1673 #define RF_TXM_IDAC                     0x08
1674 #define RF_BS_IQGEN                     0x0F
1675 
1676 #define RF_MODE1                        0x10
1677 #define RF_MODE2                        0x11
1678 
1679 #define RF_RX_AGC_HP                    0x12
1680 #define RF_TX_AGC                       0x13
1681 #define RF_BIAS                         0x14
1682 #define RF_IPA                          0x15
1683 #define RF_POW_ABILITY                  0x17
1684 #define RF_MODE_AG                      0x18
1685 #define RRFCHANNEL                      0x18
1686 #define RF_CHNLBW                       0x18
1687 #define RF_TOP                          0x19
1688 
1689 #define RF_RX_G1                        0x1A
1690 #define RF_RX_G2                        0x1B
1691 
1692 #define RF_RX_BB2                       0x1C
1693 #define RF_RX_BB1                       0x1D
1694 
1695 #define RF_RCK1                         0x1E
1696 #define RF_RCK2                         0x1F
1697 
1698 #define RF_TX_G1                        0x20
1699 #define RF_TX_G2                        0x21
1700 #define RF_TX_G3                        0x22
1701 
1702 #define RF_TX_BB1                       0x23
1703 #define RF_T_METER                      0x24
1704 #define RF_T_METER_88E                  0x42
1705 #define  RF_T_METER_8812A               0x42
1706 
1707 #define RF_SYN_G1                       0x25
1708 #define RF_SYN_G2                       0x26
1709 #define RF_SYN_G3                       0x27
1710 #define RF_SYN_G4                       0x28
1711 #define RF_SYN_G5                       0x29
1712 #define RF_SYN_G6                       0x2A
1713 #define RF_SYN_G7                       0x2B
1714 #define RF_SYN_G8                       0x2C
1715 
1716 #define RF_RCK_OS                       0x30
1717 #define RF_TXPA_G1                      0x31
1718 #define RF_TXPA_G2                      0x32
1719 #define RF_TXPA_G3                      0x33
1720 
1721 #define RF_TX_BIAS_A                    0x35
1722 #define RF_TX_BIAS_D                    0x36
1723 #define RF_LOBF_9                       0x38
1724 #define RF_RXRF_A3                      0x3C
1725 #define RF_TRSW                         0x3F
1726 
1727 #define RF_TXRF_A2                      0x41
1728 #define RF_TXPA_G4                      0x46
1729 #define RF_TXPA_A4                      0x4B
1730 
1731 #define RF_APK                          0x63
1732 
1733 #define RF_WE_LUT                       0xEF
1734 
1735 #define BBBRESETB                       0x100
1736 #define BGLOBALRESETB                   0x200
1737 #define BOFDMTXSTART                    0x4
1738 #define BCCKTXSTART                     0x8
1739 #define BCRC32DEBUG                     0x100
1740 #define BPMACLOOPBACK                   0x10
1741 #define BTXLSIG                         0xffffff
1742 #define BOFDMTXRATE                     0xf
1743 #define BOFDMTXRESERVED                 0x10
1744 #define BOFDMTXLENGTH                   0x1ffe0
1745 #define BOFDMTXPARITY                   0x20000
1746 #define BTXHTSIG1                       0xffffff
1747 #define BTXHTMCSRATE                    0x7f
1748 #define BTXHTBW                         0x80
1749 #define BTXHTLENGTH                     0xffff00
1750 #define BTXHTSIG2                       0xffffff
1751 #define BTXHTSMOOTHING                  0x1
1752 #define BTXHTSOUNDING                   0x2
1753 #define BTXHTRESERVED                   0x4
1754 #define BTXHTAGGREATION                 0x8
1755 #define BTXHTSTBC                       0x30
1756 #define BTXHTADVANCECODING              0x40
1757 #define BTXHTSHORTGI                    0x80
1758 #define BTXHTNUMBERHT_LTF               0x300
1759 #define BTXHTCRC8                       0x3fc00
1760 #define BCOUNTERRESET                   0x10000
1761 #define BNUMOFOFDMTX                    0xffff
1762 #define BNUMOFCCKTX                     0xffff0000
1763 #define BTXIDLEINTERVAL                 0xffff
1764 #define BOFDMSERVICE                    0xffff0000
1765 #define BTXMACHEADER                    0xffffffff
1766 #define BTXDATAINIT                     0xff
1767 #define BTXHTMODE                       0x100
1768 #define BTXDATATYPE                     0x30000
1769 #define BTXRANDOMSEED                   0xffffffff
1770 #define BCCKTXPREAMBLE                  0x1
1771 #define BCCKTXSFD                       0xffff0000
1772 #define BCCKTXSIG                       0xff
1773 #define BCCKTXSERVICE                   0xff00
1774 #define BCCKLENGTHEXT                   0x8000
1775 #define BCCKTXLENGHT                    0xffff0000
1776 #define BCCKTXCRC16                     0xffff
1777 #define BCCKTXSTATUS                    0x1
1778 #define BOFDMTXSTATUS                   0x2
1779 #define IS_BB_REG_OFFSET_92S(__offset)  \
1780         ((__offset >= 0x800) && (__offset <= 0xfff))
1781 
1782 #define BRFMOD                          0x1
1783 #define BJAPANMODE                      0x2
1784 #define BCCKTXSC                        0x30
1785 /* Block & Path enable*/
1786 #define ROFDMCCKEN                      0x808
1787 #define BCCKEN                          0x10000000
1788 #define BOFDMEN                         0x20000000
1789 /* Rx antenna*/
1790 #define RRXPATH                         0x808
1791 #define BRXPATH                         0xff
1792 /* Tx antenna*/
1793 #define RTXPATH                         0x80c
1794 #define BTXPATH                         0x0fffffff
1795 /* for cck rx path selection*/
1796 #define RCCK_RX                         0xa04
1797 #define BCCK_RX                         0x0c000000
1798 /* Use LSIG for VHT length*/
1799 #define RVHTLEN_USE_LSIG                0x8c3
1800 
1801 #define BOFDMRXADCPHASE                 0x10000
1802 #define BOFDMTXDACPHASE                 0x40000
1803 #define BXATXAGC                        0x3f
1804 
1805 #define BXBTXAGC                        0xf00
1806 #define BXCTXAGC                        0xf000
1807 #define BXDTXAGC                        0xf0000
1808 
1809 #define BPASTART                        0xf0000000
1810 #define BTRSTART                        0x00f00000
1811 #define BRFSTART                        0x0000f000
1812 #define BBBSTART                        0x000000f0
1813 #define BBBCCKSTART                     0x0000000f
1814 #define BPAEND                          0xf
1815 #define BTREND                          0x0f000000
1816 #define BRFEND                          0x000f0000
1817 #define BCCAMASK                        0x000000f0
1818 #define BR2RCCAMASK                     0x00000f00
1819 #define BHSSI_R2TDELAY                  0xf8000000
1820 #define BHSSI_T2RDELAY                  0xf80000
1821 #define BCONTXHSSI                      0x400
1822 #define BIGFROMCCK                      0x200
1823 #define BAGCADDRESS                     0x3f
1824 #define BRXHPTX                         0x7000
1825 #define BRXHP2RX                        0x38000
1826 #define BRXHPCCKINI                     0xc0000
1827 #define BAGCTXCODE                      0xc00000
1828 #define BAGCRXCODE                      0x300000
1829 
1830 #define B3WIREDATALENGTH                0x800
1831 #define B3WIREADDREAALENGTH             0x400
1832 
1833 #define B3WIRERFPOWERDOWN               0x1
1834 #define B5GPAPEPOLARITY                 0x40000000
1835 #define B2GPAPEPOLARITY                 0x80000000
1836 #define BRFSW_TXDEFAULTANT              0x3
1837 #define BRFSW_TXOPTIONANT               0x30
1838 #define BRFSW_RXDEFAULTANT              0x300
1839 #define BRFSW_RXOPTIONANT               0x3000
1840 #define BRFSI_3WIREDATA                 0x1
1841 #define BRFSI_3WIRECLOCK                0x2
1842 #define BRFSI_3WIRELOAD                 0x4
1843 #define BRFSI_3WIRERW                   0x8
1844 #define BRFSI_3WIRE                     0xf
1845 
1846 #define BRFSI_RFENV                     0x10
1847 
1848 #define BRFSI_TRSW                      0x20
1849 #define BRFSI_TRSWB                     0x40
1850 #define BRFSI_ANTSW                     0x100
1851 #define BRFSI_ANTSWB                    0x200
1852 #define BRFSI_PAPE                      0x400
1853 #define BRFSI_PAPE5G                    0x800
1854 #define BBANDSELECT                     0x1
1855 #define BHTSIG2_GI                      0x80
1856 #define BHTSIG2_SMOOTHING               0x01
1857 #define BHTSIG2_SOUNDING                0x02
1858 #define BHTSIG2_AGGREATON               0x08
1859 #define BHTSIG2_STBC                    0x30
1860 #define BHTSIG2_ADVCODING               0x40
1861 #define BHTSIG2_NUMOFHTLTF              0x300
1862 #define BHTSIG2_CRC8                    0x3fc
1863 #define BHTSIG1_MCS                     0x7f
1864 #define BHTSIG1_BANDWIDTH               0x80
1865 #define BHTSIG1_HTLENGTH                0xffff
1866 #define BLSIG_RATE                      0xf
1867 #define BLSIG_RESERVED                  0x10
1868 #define BLSIG_LENGTH                    0x1fffe
1869 #define BLSIG_PARITY                    0x20
1870 #define BCCKRXPHASE                     0x4
1871 
1872 #define BLSSIREADADDRESS                0x7f800000
1873 #define BLSSIREADEDGE                   0x80000000
1874 
1875 #define BLSSIREADBACKDATA               0xfffff
1876 
1877 #define BLSSIREADOKFLAG                 0x1000
1878 #define BCCKSAMPLERATE                  0x8
1879 #define BREGULATOR0STANDBY              0x1
1880 #define BREGULATORPLLSTANDBY            0x2
1881 #define BREGULATOR1STANDBY              0x4
1882 #define BPLLPOWERUP                     0x8
1883 #define BDPLLPOWERUP                    0x10
1884 #define BDA10POWERUP                    0x20
1885 #define BAD7POWERUP                     0x200
1886 #define BDA6POWERUP                     0x2000
1887 #define BXTALPOWERUP                    0x4000
1888 #define B40MDCLKPOWERUP                 0x8000
1889 #define BDA6DEBUGMODE                   0x20000
1890 #define BDA6SWING                       0x380000
1891 
1892 #define BADCLKPHASE                     0x4000000
1893 #define B80MCLKDELAY                    0x18000000
1894 #define BAFEWATCHDOGENABLE              0x20000000
1895 
1896 #define BXTALCAP01                      0xc0000000
1897 #define BXTALCAP23                      0x3
1898 #define BXTALCAP92X                     0x0f000000
1899 #define BXTALCAP                        0x0f000000
1900 
1901 #define BINTDIFCLKENABLE                0x400
1902 #define BEXTSIGCLKENABLE                0x800
1903 #define BBANDGAP_MBIAS_POWERUP          0x10000
1904 #define BAD11SH_GAIN                    0xc0000
1905 #define BAD11NPUT_RANGE                 0x700000
1906 #define BAD110P_CURRENT                 0x3800000
1907 #define BLPATH_LOOPBACK                 0x4000000
1908 #define BQPATH_LOOPBACK                 0x8000000
1909 #define BAFE_LOOPBACK                   0x10000000
1910 #define BDA10_SWING                     0x7e0
1911 #define BDA10_REVERSE                   0x800
1912 #define BDA_CLK_SOURCE                  0x1000
1913 #define BDA7INPUT_RANGE                 0x6000
1914 #define BDA7_GAIN                       0x38000
1915 #define BDA7OUTPUT_CM_MODE              0x40000
1916 #define BDA7INPUT_CM_MODE               0x380000
1917 #define BDA7CURRENT                     0xc00000
1918 #define BREGULATOR_ADJUST               0x7000000
1919 #define BAD11POWERUP_ATTX               0x1
1920 #define BDA10PS_ATTX                    0x10
1921 #define BAD11POWERUP_ATRX               0x100
1922 #define BDA10PS_ATRX                    0x1000
1923 #define BCCKRX_AGC_FORMAT               0x200
1924 #define BPSDFFT_SAMPLE_POINT            0xc000
1925 #define BPSD_AVERAGE_NUM                0x3000
1926 #define BIQPATH_CONTROL                 0xc00
1927 #define BPSD_FREQ                       0x3ff
1928 #define BPSD_ANTENNA_PATH               0x30
1929 #define BPSD_IQ_SWITCH                  0x40
1930 #define BPSD_RX_TRIGGER                 0x400000
1931 #define BPSD_TX_TRIGGER                 0x80000000
1932 #define BPSD_SINE_TONE_SCALE            0x7f000000
1933 #define BPSD_REPORT                     0xffff
1934 
1935 #define BOFDM_TXSC                      0x30000000
1936 #define BCCK_TXON                       0x1
1937 #define BOFDM_TXON                      0x2
1938 #define BDEBUG_PAGE                     0xfff
1939 #define BDEBUG_ITEM                     0xff
1940 #define BANTL                           0x10
1941 #define BANT_NONHT                      0x100
1942 #define BANT_HT1                        0x1000
1943 #define BANT_HT2                        0x10000
1944 #define BANT_HT1S1                      0x100000
1945 #define BANT_NONHTS1                    0x1000000
1946 
1947 #define BCCK_BBMODE                     0x3
1948 #define BCCK_TXPOWERSAVING              0x80
1949 #define BCCK_RXPOWERSAVING              0x40
1950 
1951 #define BCCK_SIDEBAND                   0x10
1952 
1953 #define BCCK_SCRAMBLE                   0x8
1954 #define BCCK_ANTDIVERSITY               0x8000
1955 #define BCCK_CARRIER_RECOVERY           0x4000
1956 #define BCCK_TXRATE                     0x3000
1957 #define BCCK_DCCANCEL                   0x0800
1958 #define BCCK_ISICANCEL                  0x0400
1959 #define BCCK_MATCH_FILTER               0x0200
1960 #define BCCK_EQUALIZER                  0x0100
1961 #define BCCK_PREAMBLE_DETECT            0x800000
1962 #define BCCK_FAST_FALSECCA              0x400000
1963 #define BCCK_CH_ESTSTART                0x300000
1964 #define BCCK_CCA_COUNT                  0x080000
1965 #define BCCK_CS_LIM                     0x070000
1966 #define BCCK_BIST_MODE                  0x80000000
1967 #define BCCK_CCAMASK                    0x40000000
1968 #define BCCK_TX_DAC_PHASE               0x4
1969 #define BCCK_RX_ADC_PHASE               0x20000000
1970 #define BCCKR_CP_MODE                   0x0100
1971 #define BCCK_TXDC_OFFSET                0xf0
1972 #define BCCK_RXDC_OFFSET                0xf
1973 #define BCCK_CCA_MODE                   0xc000
1974 #define BCCK_FALSECS_LIM                0x3f00
1975 #define BCCK_CS_RATIO                   0xc00000
1976 #define BCCK_CORGBIT_SEL                0x300000
1977 #define BCCK_PD_LIM                     0x0f0000
1978 #define BCCK_NEWCCA                     0x80000000
1979 #define BCCK_RXHP_OF_IG                 0x8000
1980 #define BCCK_RXIG                       0x7f00
1981 #define BCCK_LNA_POLARITY               0x800000
1982 #define BCCK_RX1ST_BAIN                 0x7f0000
1983 #define BCCK_RF_EXTEND                  0x20000000
1984 #define BCCK_RXAGC_SATLEVEL             0x1f000000
1985 #define BCCK_RXAGC_SATCOUNT             0xe0
1986 #define BCCKRXRFSETTLE                  0x1f
1987 #define BCCK_FIXED_RXAGC                0x8000
1988 #define BCCK_ANTENNA_POLARITY           0x2000
1989 #define BCCK_TXFILTER_TYPE              0x0c00
1990 #define BCCK_RXAGC_REPORTTYPE           0x0300
1991 #define BCCK_RXDAGC_EN                  0x80000000
1992 #define BCCK_RXDAGC_PERIOD              0x20000000
1993 #define BCCK_RXDAGC_SATLEVEL            0x1f000000
1994 #define BCCK_TIMING_RECOVERY            0x800000
1995 #define BCCK_TXC0                       0x3f0000
1996 #define BCCK_TXC1                       0x3f000000
1997 #define BCCK_TXC2                       0x3f
1998 #define BCCK_TXC3                       0x3f00
1999 #define BCCK_TXC4                       0x3f0000
2000 #define BCCK_TXC5                       0x3f000000
2001 #define BCCK_TXC6                       0x3f
2002 #define BCCK_TXC7                       0x3f00
2003 #define BCCK_DEBUGPORT                  0xff0000
2004 #define BCCK_DAC_DEBUG                  0x0f000000
2005 #define BCCK_FALSEALARM_ENABLE          0x8000
2006 #define BCCK_FALSEALARM_READ            0x4000
2007 #define BCCK_TRSSI                      0x7f
2008 #define BCCK_RXAGC_REPORT               0xfe
2009 #define BCCK_RXREPORT_ANTSEL            0x80000000
2010 #define BCCK_RXREPORT_MFOFF             0x40000000
2011 #define BCCK_RXREPORT_SQLOSS            0x20000000
2012 #define BCCK_RXREPORT_PKTLOSS           0x10000000
2013 #define BCCK_RXREPORT_LOCKEDBIT         0x08000000
2014 #define BCCK_RXREPORT_RATEERROR         0x04000000
2015 #define BCCK_RXREPORT_RXRATE            0x03000000
2016 #define BCCK_RXFA_COUNTER_LOWER         0xff
2017 #define BCCK_RXFA_COUNTER_UPPER         0xff000000
2018 #define BCCK_RXHPAGC_START              0xe000
2019 #define BCCK_RXHPAGC_FINAL              0x1c00
2020 #define BCCK_RXFALSEALARM_ENABLE        0x8000
2021 #define BCCK_FACOUNTER_FREEZE           0x4000
2022 #define BCCK_TXPATH_SEL                 0x10000000
2023 #define BCCK_DEFAULT_RXPATH             0xc000000
2024 #define BCCK_OPTION_RXPATH              0x3000000
2025 
2026 #define BNUM_OFSTF                      0x3
2027 #define BSHIFT_L                        0xc0
2028 #define BGI_TH                          0xc
2029 #define BRXPATH_A                       0x1
2030 #define BRXPATH_B                       0x2
2031 #define BRXPATH_C                       0x4
2032 #define BRXPATH_D                       0x8
2033 #define BTXPATH_A                       0x1
2034 #define BTXPATH_B                       0x2
2035 #define BTXPATH_C                       0x4
2036 #define BTXPATH_D                       0x8
2037 #define BTRSSI_FREQ                     0x200
2038 #define BADC_BACKOFF                    0x3000
2039 #define BDFIR_BACKOFF                   0xc000
2040 #define BTRSSI_LATCH_PHASE              0x10000
2041 #define BRX_LDC_OFFSET                  0xff
2042 #define BRX_QDC_OFFSET                  0xff00
2043 #define BRX_DFIR_MODE                   0x1800000
2044 #define BRX_DCNF_TYPE                   0xe000000
2045 #define BRXIQIMB_A                      0x3ff
2046 #define BRXIQIMB_B                      0xfc00
2047 #define BRXIQIMB_C                      0x3f0000
2048 #define BRXIQIMB_D                      0xffc00000
2049 #define BDC_DC_NOTCH                    0x60000
2050 #define BRXNB_NOTCH                     0x1f000000
2051 #define BPD_TH                          0xf
2052 #define BPD_TH_OPT2                     0xc000
2053 #define BPWED_TH                        0x700
2054 #define BIFMF_WIN_L                     0x800
2055 #define BPD_OPTION                      0x1000
2056 #define BMF_WIN_L                       0xe000
2057 #define BBW_SEARCH_L                    0x30000
2058 #define BWIN_ENH_L                      0xc0000
2059 #define BBW_TH                          0x700000
2060 #define BED_TH2                         0x3800000
2061 #define BBW_OPTION                      0x4000000
2062 #define BRADIO_TH                       0x18000000
2063 #define BWINDOW_L                       0xe0000000
2064 #define BSBD_OPTION                     0x1
2065 #define BFRAME_TH                       0x1c
2066 #define BFS_OPTION                      0x60
2067 #define BDC_SLOPE_CHECK                 0x80
2068 #define BFGUARD_COUNTER_DC_L            0xe00
2069 #define BFRAME_WEIGHT_SHORT             0x7000
2070 #define BSUB_TUNE                       0xe00000
2071 #define BFRAME_DC_LENGTH                0xe000000
2072 #define BSBD_START_OFFSET               0x30000000
2073 #define BFRAME_TH_2                     0x7
2074 #define BFRAME_GI2_TH                   0x38
2075 #define BGI2_SYNC_EN                    0x40
2076 #define BSARCH_SHORT_EARLY              0x300
2077 #define BSARCH_SHORT_LATE               0xc00
2078 #define BSARCH_GI2_LATE                 0x70000
2079 #define BCFOANTSUM                      0x1
2080 #define BCFOACC                         0x2
2081 #define BCFOSTARTOFFSET                 0xc
2082 #define BCFOLOOPBACK                    0x70
2083 #define BCFOSUMWEIGHT                   0x80
2084 #define BDAGCENABLE                     0x10000
2085 #define BTXIQIMB_A                      0x3ff
2086 #define BTXIQIMB_b                      0xfc00
2087 #define BTXIQIMB_C                      0x3f0000
2088 #define BTXIQIMB_D                      0xffc00000
2089 #define BTXIDCOFFSET                    0xff
2090 #define BTXIQDCOFFSET                   0xff00
2091 #define BTXDFIRMODE                     0x10000
2092 #define BTXPESUDO_NOISEON               0x4000000
2093 #define BTXPESUDO_NOISE_A               0xff
2094 #define BTXPESUDO_NOISE_B               0xff00
2095 #define BTXPESUDO_NOISE_C               0xff0000
2096 #define BTXPESUDO_NOISE_D               0xff000000
2097 #define BCCA_DROPOPTION                 0x20000
2098 #define BCCA_DROPTHRES                  0xfff00000
2099 #define BEDCCA_H                        0xf
2100 #define BEDCCA_L                        0xf0
2101 #define BLAMBDA_ED                      0x300
2102 #define BRX_INITIALGAIN                 0x7f
2103 #define BRX_ANTDIV_EN                   0x80
2104 #define BRX_AGC_ADDRESS_FOR_LNA         0x7f00
2105 #define BRX_HIGHPOWER_FLOW              0x8000
2106 #define BRX_AGC_FREEZE_THRES            0xc0000
2107 #define BRX_FREEZESTEP_AGC1             0x300000
2108 #define BRX_FREEZESTEP_AGC2             0xc00000
2109 #define BRX_FREEZESTEP_AGC3             0x3000000
2110 #define BRX_FREEZESTEP_AGC0             0xc000000
2111 #define BRXRSSI_CMP_EN                  0x10000000
2112 #define BRXQUICK_AGCEN                  0x20000000
2113 #define BRXAGC_FREEZE_THRES_MODE        0x40000000
2114 #define BRX_OVERFLOW_CHECKTYPE          0x80000000
2115 #define BRX_AGCSHIFT                    0x7f
2116 #define BTRSW_TRI_ONLY                  0x80
2117 #define BPOWER_THRES                    0x300
2118 #define BRXAGC_EN                       0x1
2119 #define BRXAGC_TOGETHER_EN              0x2
2120 #define BRXAGC_MIN                      0x4
2121 #define BRXHP_INI                       0x7
2122 #define BRXHP_TRLNA                     0x70
2123 #define BRXHP_RSSI                      0x700
2124 #define BRXHP_BBP1                      0x7000
2125 #define BRXHP_BBP2                      0x70000
2126 #define BRXHP_BBP3                      0x700000
2127 #define BRSSI_H                         0x7f0000
2128 #define BRSSI_GEN                       0x7f000000
2129 #define BRXSETTLE_TRSW                  0x7
2130 #define BRXSETTLE_LNA                   0x38
2131 #define BRXSETTLE_RSSI                  0x1c0
2132 #define BRXSETTLE_BBP                   0xe00
2133 #define BRXSETTLE_RXHP                  0x7000
2134 #define BRXSETTLE_ANTSW_RSSI            0x38000
2135 #define BRXSETTLE_ANTSW                 0xc0000
2136 #define BRXPROCESS_TIME_DAGC            0x300000
2137 #define BRXSETTLE_HSSI                  0x400000
2138 #define BRXPROCESS_TIME_BBPPW           0x800000
2139 #define BRXANTENNA_POWER_SHIFT          0x3000000
2140 #define BRSSI_TABLE_SELECT              0xc000000
2141 #define BRXHP_FINAL                     0x7000000
2142 #define BRXHPSETTLE_BBP                 0x7
2143 #define BRXHTSETTLE_HSSI                0x8
2144 #define BRXHTSETTLE_RXHP                0x70
2145 #define BRXHTSETTLE_BBPPW               0x80
2146 #define BRXHTSETTLE_IDLE                0x300
2147 #define BRXHTSETTLE_RESERVED            0x1c00
2148 #define BRXHT_RXHP_EN                   0x8000
2149 #define BRXAGC_FREEZE_THRES             0x30000
2150 #define BRXAGC_TOGETHEREN               0x40000
2151 #define BRXHTAGC_MIN                    0x80000
2152 #define BRXHTAGC_EN                     0x100000
2153 #define BRXHTDAGC_EN                    0x200000
2154 #define BRXHT_RXHP_BBP                  0x1c00000
2155 #define BRXHT_RXHP_FINAL                0xe0000000
2156 #define BRXPW_RADIO_TH                  0x3
2157 #define BRXPW_RADIO_EN                  0x4
2158 #define BRXMF_HOLD                      0x3800
2159 #define BRXPD_DELAY_TH1                 0x38
2160 #define BRXPD_DELAY_TH2                 0x1c0
2161 #define BRXPD_DC_COUNT_MAX              0x600
2162 #define BRXPD_DELAY_TH                  0x8000
2163 #define BRXPROCESS_DELAY                0xf0000
2164 #define BRXSEARCHRANGE_GI2_EARLY        0x700000
2165 #define BRXFRAME_FUARD_COUNTER_L        0x3800000
2166 #define BRXSGI_GUARD_L                  0xc000000
2167 #define BRXSGI_SEARCH_L                 0x30000000
2168 #define BRXSGI_TH                       0xc0000000
2169 #define BDFSCNT0                        0xff
2170 #define BDFSCNT1                        0xff00
2171 #define BDFSFLAG                        0xf0000
2172 #define BMF_WEIGHT_SUM                  0x300000
2173 #define BMINIDX_TH                      0x7f000000
2174 #define BDAFORMAT                       0x40000
2175 #define BTXCH_EMU_ENABLE                0x01000000
2176 #define BTRSW_ISOLATION_A               0x7f
2177 #define BTRSW_ISOLATION_B               0x7f00
2178 #define BTRSW_ISOLATION_C               0x7f0000
2179 #define BTRSW_ISOLATION_D               0x7f000000
2180 #define BEXT_LNA_GAIN                   0x7c00
2181 
2182 #define BSTBC_EN                        0x4
2183 #define BANTENNA_MAPPING                0x10
2184 #define BNSS                            0x20
2185 #define BCFO_ANTSUM_ID                  0x200
2186 #define BPHY_COUNTER_RESET              0x8000000
2187 #define BCFO_REPORT_GET                 0x4000000
2188 #define BOFDM_CONTINUE_TX               0x10000000
2189 #define BOFDM_SINGLE_CARRIER            0x20000000
2190 #define BOFDM_SINGLE_TONE               0x40000000
2191 #define BHT_DETECT                      0x100
2192 #define BCFOEN                          0x10000
2193 #define BCFOVALUE                       0xfff00000
2194 #define BSIGTONE_RE                     0x3f
2195 #define BSIGTONE_IM                     0x7f00
2196 #define BCOUNTER_CCA                    0xffff
2197 #define BCOUNTER_PARITYFAIL             0xffff0000
2198 #define BCOUNTER_RATEILLEGAL            0xffff
2199 #define BCOUNTER_CRC8FAIL               0xffff0000
2200 #define BCOUNTER_MCSNOSUPPORT           0xffff
2201 #define BCOUNTER_FASTSYNC               0xffff
2202 #define BSHORTCFO                       0xfff
2203 #define BSHORTCFOT_LENGTH               12
2204 #define BSHORTCFOF_LENGTH               11
2205 #define BLONGCFO                        0x7ff
2206 #define BLONGCFOT_LENGTH                11
2207 #define BLONGCFOF_LENGTH                11
2208 #define BTAILCFO                        0x1fff
2209 #define BTAILCFOT_LENGTH                13
2210 #define BTAILCFOF_LENGTH                12
2211 #define BNOISE_EN_PWDB                  0xffff
2212 #define BCC_POWER_DB                    0xffff0000
2213 #define BMOISE_PWDB                     0xffff
2214 #define BPOWERMEAST_LENGTH              10
2215 #define BPOWERMEASF_LENGTH              3
2216 #define BRX_HT_BW                       0x1
2217 #define BRXSC                           0x6
2218 #define BRX_HT                          0x8
2219 #define BNB_INTF_DET_ON                 0x1
2220 #define BINTF_WIN_LEN_CFG               0x30
2221 #define BNB_INTF_TH_CFG                 0x1c0
2222 #define BRFGAIN                         0x3f
2223 #define BTABLESEL                       0x40
2224 #define BTRSW                           0x80
2225 #define BRXSNR_A                        0xff
2226 #define BRXSNR_B                        0xff00
2227 #define BRXSNR_C                        0xff0000
2228 #define BRXSNR_D                        0xff000000
2229 #define BSNR_EVMT_LENGTH                8
2230 #define BSNR_EVMF_LENGTH                1
2231 #define BCSI1ST                         0xff
2232 #define BCSI2ND                         0xff00
2233 #define BRXEVM1ST                       0xff0000
2234 #define BRXEVM2ND                       0xff000000
2235 #define BSIGEVM                         0xff
2236 #define BPWDB                           0xff00
2237 #define BSGIEN                          0x10000
2238 
2239 #define BSFACTOR_QMA1                   0xf
2240 #define BSFACTOR_QMA2                   0xf0
2241 #define BSFACTOR_QMA3                   0xf00
2242 #define BSFACTOR_QMA4                   0xf000
2243 #define BSFACTOR_QMA5                   0xf0000
2244 #define BSFACTOR_QMA6                   0xf0000
2245 #define BSFACTOR_QMA7                   0xf00000
2246 #define BSFACTOR_QMA8                   0xf000000
2247 #define BSFACTOR_QMA9                   0xf0000000
2248 #define BCSI_SCHEME                     0x100000
2249 
2250 #define BNOISE_LVL_TOP_SET              0x3
2251 #define BCHSMOOTH                       0x4
2252 #define BCHSMOOTH_CFG1                  0x38
2253 #define BCHSMOOTH_CFG2                  0x1c0
2254 #define BCHSMOOTH_CFG3                  0xe00
2255 #define BCHSMOOTH_CFG4                  0x7000
2256 #define BMRCMODE                        0x800000
2257 #define BTHEVMCFG                       0x7000000
2258 
2259 #define BLOOP_FIT_TYPE                  0x1
2260 #define BUPD_CFO                        0x40
2261 #define BUPD_CFO_OFFDATA                0x80
2262 #define BADV_UPD_CFO                    0x100
2263 #define BADV_TIME_CTRL                  0x800
2264 #define BUPD_CLKO                       0x1000
2265 #define BFC                             0x6000
2266 #define BTRACKING_MODE                  0x8000
2267 #define BPHCMP_ENABLE                   0x10000
2268 #define BUPD_CLKO_LTF                   0x20000
2269 #define BCOM_CH_CFO                     0x40000
2270 #define BCSI_ESTI_MODE                  0x80000
2271 #define BADV_UPD_EQZ                    0x100000
2272 #define BUCHCFG                         0x7000000
2273 #define BUPDEQZ                         0x8000000
2274 
2275 #define BRX_PESUDO_NOISE_ON             0x20000000
2276 #define BRX_PESUDO_NOISE_A              0xff
2277 #define BRX_PESUDO_NOISE_B              0xff00
2278 #define BRX_PESUDO_NOISE_C              0xff0000
2279 #define BRX_PESUDO_NOISE_D              0xff000000
2280 #define BRX_PESUDO_NOISESTATE_A         0xffff
2281 #define BRX_PESUDO_NOISESTATE_B         0xffff0000
2282 #define BRX_PESUDO_NOISESTATE_C         0xffff
2283 #define BRX_PESUDO_NOISESTATE_D         0xffff0000
2284 
2285 #define BZEBRA1_HSSIENABLE              0x8
2286 #define BZEBRA1_TRXCONTROL              0xc00
2287 #define BZEBRA1_TRXGAINSETTING          0x07f
2288 #define BZEBRA1_RXCOUNTER               0xc00
2289 #define BZEBRA1_TXCHANGEPUMP            0x38
2290 #define BZEBRA1_RXCHANGEPUMP            0x7
2291 #define BZEBRA1_CHANNEL_NUM             0xf80
2292 #define BZEBRA1_TXLPFBW                 0x400
2293 #define BZEBRA1_RXLPFBW                 0x600
2294 
2295 #define BRTL8256REG_MODE_CTRL1          0x100
2296 #define BRTL8256REG_MODE_CTRL0          0x40
2297 #define BRTL8256REG_TXLPFBW             0x18
2298 #define BRTL8256REG_RXLPFBW             0x600
2299 
2300 #define BRTL8258_TXLPFBW                0xc
2301 #define BRTL8258_RXLPFBW                0xc00
2302 #define BRTL8258_RSSILPFBW              0xc0
2303 
2304 #define BBYTE0                          0x1
2305 #define BBYTE1                          0x2
2306 #define BBYTE2                          0x4
2307 #define BBYTE3                          0x8
2308 #define BWORD0                          0x3
2309 #define BWORD1                          0xc
2310 #define BWORD                           0xf
2311 
2312 #define MASKBYTE0                       0xff
2313 #define MASKBYTE1                       0xff00
2314 #define MASKBYTE2                       0xff0000
2315 #define MASKBYTE3                       0xff000000
2316 #define MASKHWORD                       0xffff0000
2317 #define MASKLWORD                       0x0000ffff
2318 #define MASKDWORD                       0xffffffff
2319 #define MASK12BITS                      0xfff
2320 #define MASKH4BITS                      0xf0000000
2321 #define MASKOFDM_D                      0xffc00000
2322 #define MASKCCK                         0x3f3f3f3f
2323 
2324 #define MASK4BITS                       0x0f
2325 #define MASK20BITS                      0xfffff
2326 #define RFREG_OFFSET_MASK               0xfffff
2327 
2328 #define BENABLE                         0x1
2329 #define BDISABLE                        0x0
2330 
2331 #define LEFT_ANTENNA                    0x0
2332 #define RIGHT_ANTENNA                   0x1
2333 
2334 #define TCHECK_TXSTATUS                 500
2335 #define TUPDATE_RXCOUNTER               100
2336 
2337 #define REG_UN_used_register            0x01bf
2338 
2339 /* Path_A RFE cotrol pinmux*/
2340 #define         RA_RFE_PINMUX           0xcb0
2341 /* Path_B RFE control pinmux*/
2342 #define         RB_RFE_PINMUX           0xeb0
2343 
2344 #define         RA_RFE_INV              0xcb4
2345 #define         RB_RFE_INV              0xeb4
2346 
2347 /* RXIQC */
2348 /*RxIQ imblance matrix coeff. A & B*/
2349 #define RA_RXIQC_AB                     0xc10
2350 /*RxIQ imblance matrix coeff. C & D*/
2351 #define RA_RXIQC_CD                     0xc14
2352 /* Pah_A TX scaling factor*/
2353 #define RA_TXSCALE                      0xc1c
2354 /* Path_B TX scaling factor*/
2355 #define RB_TXSCALE                      0xe1c
2356 /*RxIQ imblance matrix coeff. A & B*/
2357 #define RB_RXIQC_AB                     0xe10
2358 /*RxIQ imblance matrix coeff. C & D*/
2359 #define RB_RXIQC_CD                     0xe14
2360 /*bit mask for IQC matrix element A & C*/
2361 #define RXIQC_AC                        0x02ff
2362  /*bit mask for IQC matrix element A & C*/
2363 #define RXIQC_BD                        0x02ff0000
2364 
2365 /* 2 EFUSE_TEST (For RTL8723 partially) */
2366 #define EFUSE_SEL(x)                    (((x) & 0x3) << 8)
2367 #define EFUSE_SEL_MASK                  0x300
2368 #define EFUSE_WIFI_SEL_0                0x0
2369 
2370 /*REG_MULTI_FUNC_CTRL(For RTL8723 Only)*/
2371 /* Enable GPIO[9] as WiFi HW PDn source*/
2372 #define WL_HWPDN_EN                     BIT(0)
2373 /* WiFi HW PDn polarity control*/
2374 #define WL_HWPDN_SL                     BIT(1)
2375 /* WiFi function enable */
2376 #define WL_FUNC_EN                      BIT(2)
2377 /* Enable GPIO[9] as WiFi RF HW PDn source */
2378 #define WL_HWROF_EN                     BIT(3)
2379 /* Enable GPIO[11] as BT HW PDn source */
2380 #define BT_HWPDN_EN                     BIT(16)
2381 /* BT HW PDn polarity control */
2382 #define BT_HWPDN_SL                     BIT(17)
2383 /* BT function enable */
2384 #define BT_FUNC_EN                      BIT(18)
2385 /* Enable GPIO[11] as BT/GPS RF HW PDn source */
2386 #define BT_HWROF_EN                     BIT(19)
2387 /* Enable GPIO[10] as GPS HW PDn source */
2388 #define GPS_HWPDN_EN                    BIT(20)
2389 /* GPS HW PDn polarity control */
2390 #define GPS_HWPDN_SL                    BIT(21)
2391 /* GPS function enable */
2392 #define GPS_FUNC_EN                     BIT(22)
2393 
2394 #define BMASKBYTE0                      0xff
2395 #define BMASKBYTE1                      0xff00
2396 #define BMASKBYTE2                      0xff0000
2397 #define BMASKBYTE3                      0xff000000
2398 #define BMASKHWORD                      0xffff0000
2399 #define BMASKLWORD                      0x0000ffff
2400 #define BMASKDWORD                      0xffffffff
2401 #define BMASK12BITS                     0xfff
2402 #define BMASKH4BITS                     0xf0000000
2403 #define BMASKOFDM_D                     0xffc00000
2404 #define BMASKCCK                        0x3f3f3f3f
2405 #define BMASKRFEINV                     0x3ff00000
2406 
2407 #define BRFREGOFFSETMASK                0xfffff
2408 
2409 #define ODM_REG_CCK_RPT_FORMAT_11AC     0x804
2410 #define ODM_REG_BB_RX_PATH_11AC         0x808
2411 /*PAGE 9*/
2412 #define ODM_REG_OFDM_FA_RST_11AC        0x9A4
2413 /*PAGE A*/
2414 #define ODM_REG_CCK_CCA_11AC            0xA0A
2415 #define ODM_REG_CCK_FA_RST_11AC         0xA2C
2416 #define ODM_REG_CCK_FA_11AC             0xA5C
2417 /*PAGE C*/
2418 #define ODM_REG_IGI_A_11AC              0xC50
2419 /*PAGE E*/
2420 #define ODM_REG_IGI_B_11AC              0xE50
2421 /*PAGE F*/
2422 #define ODM_REG_OFDM_FA_11AC            0xF48
2423 
2424 /* 2 MAC REG LIST */
2425 
2426 /* DIG Related */
2427 #define ODM_BIT_IGI_11AC                0xFFFFFFFF
2428 #define ODM_BIT_CCK_RPT_FORMAT_11AC     BIT16
2429 #define ODM_BIT_BB_RX_PATH_11AC         0xF
2430 
2431 enum AGGRE_SIZE {
2432         HT_AGG_SIZE_8K = 0,
2433         HT_AGG_SIZE_16K = 1,
2434         HT_AGG_SIZE_32K = 2,
2435         HT_AGG_SIZE_64K = 3,
2436         VHT_AGG_SIZE_128K = 4,
2437         VHT_AGG_SIZE_256K = 5,
2438         VHT_AGG_SIZE_512K = 6,
2439         VHT_AGG_SIZE_1024K = 7,
2440 };
2441 
2442 #define REG_AMPDU_MAX_LENGTH_8812       0x0458
2443 
2444 #endif

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