1
2
3
4 #ifndef __RTL8821AE_DM_H__
5 #define __RTL8821AE_DM_H__
6
7 #define MAIN_ANT 0
8 #define AUX_ANT 1
9 #define MAIN_ANT_CG_TRX 1
10 #define AUX_ANT_CG_TRX 0
11 #define MAIN_ANT_CGCS_RX 0
12 #define AUX_ANT_CGCS_RX 1
13
14 #define TXSCALE_TABLE_SIZE 37
15
16
17 #define DM_REG_RF_MODE_11N 0x00
18 #define DM_REG_RF_0B_11N 0x0B
19 #define DM_REG_CHNBW_11N 0x18
20 #define DM_REG_T_METER_11N 0x24
21 #define DM_REG_RF_25_11N 0x25
22 #define DM_REG_RF_26_11N 0x26
23 #define DM_REG_RF_27_11N 0x27
24 #define DM_REG_RF_2B_11N 0x2B
25 #define DM_REG_RF_2C_11N 0x2C
26 #define DM_REG_RXRF_A3_11N 0x3C
27 #define DM_REG_T_METER_92D_11N 0x42
28 #define DM_REG_T_METER_88E_11N 0x42
29
30
31
32 #define DM_REG_BB_CTRL_11N 0x800
33 #define DM_REG_RF_PIN_11N 0x804
34 #define DM_REG_PSD_CTRL_11N 0x808
35 #define DM_REG_TX_ANT_CTRL_11N 0x80C
36 #define DM_REG_BB_PWR_SAV5_11N 0x818
37 #define DM_REG_CCK_RPT_FORMAT_11N 0x824
38 #define DM_REG_RX_DEFUALT_A_11N 0x858
39 #define DM_REG_RX_DEFUALT_B_11N 0x85A
40 #define DM_REG_BB_PWR_SAV3_11N 0x85C
41 #define DM_REG_ANTSEL_CTRL_11N 0x860
42 #define DM_REG_RX_ANT_CTRL_11N 0x864
43 #define DM_REG_PIN_CTRL_11N 0x870
44 #define DM_REG_BB_PWR_SAV1_11N 0x874
45 #define DM_REG_ANTSEL_PATH_11N 0x878
46 #define DM_REG_BB_3WIRE_11N 0x88C
47 #define DM_REG_SC_CNT_11N 0x8C4
48 #define DM_REG_PSD_DATA_11N 0x8B4
49
50 #define DM_REG_ANT_MAPPING1_11N 0x914
51 #define DM_REG_ANT_MAPPING2_11N 0x918
52
53 #define DM_REG_CCK_ANTDIV_PARA1_11N 0xA00
54 #define DM_REG_CCK_CCA_11N 0xA0A
55 #define DM_REG_CCK_CCA_11AC 0xA0A
56 #define DM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
57 #define DM_REG_CCK_ANTDIV_PARA3_11N 0xA10
58 #define DM_REG_CCK_ANTDIV_PARA4_11N 0xA14
59 #define DM_REG_CCK_FILTER_PARA1_11N 0xA22
60 #define DM_REG_CCK_FILTER_PARA2_11N 0xA23
61 #define DM_REG_CCK_FILTER_PARA3_11N 0xA24
62 #define DM_REG_CCK_FILTER_PARA4_11N 0xA25
63 #define DM_REG_CCK_FILTER_PARA5_11N 0xA26
64 #define DM_REG_CCK_FILTER_PARA6_11N 0xA27
65 #define DM_REG_CCK_FILTER_PARA7_11N 0xA28
66 #define DM_REG_CCK_FILTER_PARA8_11N 0xA29
67 #define DM_REG_CCK_FA_RST_11N 0xA2C
68 #define DM_REG_CCK_FA_MSB_11N 0xA58
69 #define DM_REG_CCK_FA_LSB_11N 0xA5C
70 #define DM_REG_CCK_CCA_CNT_11N 0xA60
71 #define DM_REG_BB_PWR_SAV4_11N 0xA74
72
73 #define DM_REG_LNA_SWITCH_11N 0XB2C
74 #define DM_REG_PATH_SWITCH_11N 0XB30
75 #define DM_REG_RSSI_CTRL_11N 0XB38
76 #define DM_REG_CONFIG_ANTA_11N 0XB68
77 #define DM_REG_RSSI_BT_11N 0XB9C
78
79 #define DM_REG_OFDM_FA_HOLDC_11N 0xC00
80 #define DM_REG_RX_PATH_11N 0xC04
81 #define DM_REG_TRMUX_11N 0xC08
82 #define DM_REG_OFDM_FA_RSTC_11N 0xC0C
83 #define DM_REG_RXIQI_MATRIX_11N 0xC14
84 #define DM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
85 #define DM_REG_IGI_A_11N 0xC50
86 #define DM_REG_IGI_A_11AC 0xC50
87 #define DM_REG_ANTDIV_PARA2_11N 0xC54
88 #define DM_REG_IGI_B_11N 0xC58
89 #define DM_REG_IGI_B_11AC 0xE50
90 #define DM_REG_ANTDIV_PARA3_11N 0xC5C
91 #define DM_REG_BB_PWR_SAV2_11N 0xC70
92 #define DM_REG_RX_OFF_11N 0xC7C
93 #define DM_REG_TXIQK_MATRIXA_11N 0xC80
94 #define DM_REG_TXIQK_MATRIXB_11N 0xC88
95 #define DM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
96 #define DM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
97 #define DM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
98 #define DM_REG_ANTDIV_PARA1_11N 0xCA4
99 #define DM_REG_OFDM_FA_TYPE1_11N 0xCF0
100
101 #define DM_REG_OFDM_FA_RSTD_11N 0xD00
102 #define DM_REG_OFDM_FA_TYPE2_11N 0xDA0
103 #define DM_REG_OFDM_FA_TYPE3_11N 0xDA4
104 #define DM_REG_OFDM_FA_TYPE4_11N 0xDA8
105
106 #define DM_REG_TXAGC_A_6_18_11N 0xE00
107 #define DM_REG_TXAGC_A_24_54_11N 0xE04
108 #define DM_REG_TXAGC_A_1_MCS32_11N 0xE08
109 #define DM_REG_TXAGC_A_MCS0_3_11N 0xE10
110 #define DM_REG_TXAGC_A_MCS4_7_11N 0xE14
111 #define DM_REG_TXAGC_A_MCS8_11_11N 0xE18
112 #define DM_REG_TXAGC_A_MCS12_15_11N 0xE1C
113 #define DM_REG_FPGA0_IQK_11N 0xE28
114 #define DM_REG_TXIQK_TONE_A_11N 0xE30
115 #define DM_REG_RXIQK_TONE_A_11N 0xE34
116 #define DM_REG_TXIQK_PI_A_11N 0xE38
117 #define DM_REG_RXIQK_PI_A_11N 0xE3C
118 #define DM_REG_TXIQK_11N 0xE40
119 #define DM_REG_RXIQK_11N 0xE44
120 #define DM_REG_IQK_AGC_PTS_11N 0xE48
121 #define DM_REG_IQK_AGC_RSP_11N 0xE4C
122 #define DM_REG_BLUETOOTH_11N 0xE6C
123 #define DM_REG_RX_WAIT_CCA_11N 0xE70
124 #define DM_REG_TX_CCK_RFON_11N 0xE74
125 #define DM_REG_TX_CCK_BBON_11N 0xE78
126 #define DM_REG_OFDM_RFON_11N 0xE7C
127 #define DM_REG_OFDM_BBON_11N 0xE80
128 #define DM_REG_TX2RX_11N 0xE84
129 #define DM_REG_TX2TX_11N 0xE88
130 #define DM_REG_RX_CCK_11N 0xE8C
131 #define DM_REG_RX_OFDM_11N 0xED0
132 #define DM_REG_RX_WAIT_RIFS_11N 0xED4
133 #define DM_REG_RX2RX_11N 0xED8
134 #define DM_REG_STANDBY_11N 0xEDC
135 #define DM_REG_SLEEP_11N 0xEE0
136 #define DM_REG_PMPD_ANAEN_11N 0xEEC
137
138
139 #define DM_REG_BB_RST_11N 0x02
140 #define DM_REG_ANTSEL_PIN_11N 0x4C
141 #define DM_REG_EARLY_MODE_11N 0x4D0
142 #define DM_REG_RSSI_MONITOR_11N 0x4FE
143 #define DM_REG_EDCA_VO_11N 0x500
144 #define DM_REG_EDCA_VI_11N 0x504
145 #define DM_REG_EDCA_BE_11N 0x508
146 #define DM_REG_EDCA_BK_11N 0x50C
147 #define DM_REG_TXPAUSE_11N 0x522
148 #define DM_REG_RESP_TX_11N 0x6D8
149 #define DM_REG_ANT_TRAIN_PARA1_11N 0x7b0
150 #define DM_REG_ANT_TRAIN_PARA2_11N 0x7b4
151
152
153 #define DM_BIT_IGI_11N 0x0000007F
154 #define DM_BIT_IGI_11AC 0xFFFFFFFF
155
156 #define HAL_DM_DIG_DISABLE BIT(0)
157 #define HAL_DM_HIPWR_DISABLE BIT(1)
158
159 #define OFDM_TABLE_LENGTH 43
160 #define CCK_TABLE_LENGTH 33
161
162 #define OFDM_TABLE_SIZE 37
163 #define CCK_TABLE_SIZE 33
164
165 #define BW_AUTO_SWITCH_HIGH_LOW 25
166 #define BW_AUTO_SWITCH_LOW_HIGH 30
167
168 #define DM_DIG_FA_UPPER 0x3e
169 #define DM_DIG_FA_LOWER 0x1e
170 #define DM_DIG_FA_TH0 200
171 #define DM_DIG_FA_TH1 0x300
172 #define DM_DIG_FA_TH2 0x400
173
174 #define RXPATHSELECTION_SS_TH_LOW 30
175 #define RXPATHSELECTION_DIFF_TH 18
176
177 #define DM_RATR_STA_INIT 0
178 #define DM_RATR_STA_HIGH 1
179 #define DM_RATR_STA_MIDDLE 2
180 #define DM_RATR_STA_LOW 3
181
182 #define CTS2SELF_THVAL 30
183 #define REGC38_TH 20
184
185 #define WAIOTTHVAL 25
186
187 #define TXHIGHPWRLEVEL_NORMAL 0
188 #define TXHIGHPWRLEVEL_LEVEL1 1
189 #define TXHIGHPWRLEVEL_LEVEL2 2
190 #define TXHIGHPWRLEVEL_BT1 3
191 #define TXHIGHPWRLEVEL_BT2 4
192
193 #define DM_TYPE_BYFW 0
194 #define DM_TYPE_BYDRIVER 1
195
196 #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
197 #define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
198 #define TXPWRTRACK_MAX_IDX 6
199
200
201 #define ATC_STATUS_OFF 0x0
202 #define ATC_STATUS_ON 0x1
203 #define CFO_THRESHOLD_XTAL 10
204 #define CFO_THRESHOLD_ATC 80
205
206 #define AVG_THERMAL_NUM_8812A 4
207 #define TXPWR_TRACK_TABLE_SIZE 30
208 #define MAX_PATH_NUM_8812A 2
209 #define MAX_PATH_NUM_8821A 1
210
211 enum FAT_STATE {
212 FAT_NORMAL_STATE = 0,
213 FAT_TRAINING_STATE = 1,
214 };
215
216 enum tag_dynamic_init_gain_operation_type_definition {
217 DIG_TYPE_THRESH_HIGH = 0,
218 DIG_TYPE_THRESH_LOW = 1,
219 DIG_TYPE_BACKOFF = 2,
220 DIG_TYPE_RX_GAIN_MIN = 3,
221 DIG_TYPE_RX_GAIN_MAX = 4,
222 DIG_TYPE_ENABLE = 5,
223 DIG_TYPE_DISABLE = 6,
224 DIG_OP_TYPE_MAX
225 };
226
227 enum dm_1r_cca_e {
228 CCA_1R = 0,
229 CCA_2R = 1,
230 CCA_MAX = 2,
231 };
232
233 enum dm_rf_e {
234 RF_SAVE = 0,
235 RF_NORMAL = 1,
236 RF_MAX = 2,
237 };
238
239 enum dm_sw_ant_switch_e {
240 ANS_ANTENNA_B = 1,
241 ANS_ANTENNA_A = 2,
242 ANS_ANTENNA_MAX = 3,
243 };
244
245 enum pwr_track_control_method {
246 BBSWING,
247 TXAGC,
248 MIX_MODE
249 };
250
251 #define BT_RSSI_STATE_NORMAL_POWER BIT_OFFSET_LEN_MASK_32(0, 1)
252 #define BT_RSSI_STATE_AMDPU_OFF BIT_OFFSET_LEN_MASK_32(1, 1)
253 #define BT_RSSI_STATE_SPECIAL_LOW BIT_OFFSET_LEN_MASK_32(2, 1)
254 #define BT_RSSI_STATE_BG_EDCA_LOW BIT_OFFSET_LEN_MASK_32(3, 1)
255 #define BT_RSSI_STATE_TXPOWER_LOW BIT_OFFSET_LEN_MASK_32(4, 1)
256 #define GET_UNDECORATED_AVERAGE_RSSI(_priv) \
257 ((((struct rtl_priv *)(_priv))->mac80211.opmode == \
258 NL80211_IFTYPE_ADHOC) ? \
259 (((struct rtl_priv *)(_priv))->dm.entry_min_undec_sm_pwdb) : \
260 (((struct rtl_priv *)(_priv))->dm.undec_sm_pwdb))
261
262 void rtl8821ae_dm_set_tx_ant_by_tx_info(struct ieee80211_hw *hw,
263 u8 *pdesc, u32 mac_id);
264 void rtl8821ae_dm_ant_sel_statistics(struct ieee80211_hw *hw,
265 u8 antsel_tr_mux, u32 mac_id,
266 u32 rx_pwdb_all);
267 void rtl8821ae_dm_fast_antenna_training_callback(unsigned long data);
268 void rtl8821ae_dm_init(struct ieee80211_hw *hw);
269 void rtl8821ae_dm_watchdog(struct ieee80211_hw *hw);
270 void rtl8821ae_dm_write_dig(struct ieee80211_hw *hw, u8 current_igi);
271 void rtl8821ae_dm_init_edca_turbo(struct ieee80211_hw *hw);
272 void rtl8821ae_dm_check_txpower_tracking_thermalmeter(struct ieee80211_hw *hw);
273 void rtl8821ae_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
274 void rtl8821ae_dm_txpower_track_adjust(struct ieee80211_hw *hw,
275 u8 type, u8 *pdirection,
276 u32 *poutwrite_val);
277 void rtl8821ae_dm_clear_txpower_tracking_state(struct ieee80211_hw *hw);
278 void rtl8821ae_dm_write_cck_cca_thres(struct ieee80211_hw *hw, u8 current_cca);
279 void rtl8821ae_dm_initialize_txpower_tracking_thermalmeter(struct ieee80211_hw *hw);
280 void rtl8812ae_dm_txpwr_track_set_pwr(struct ieee80211_hw *hw,
281 enum pwr_track_control_method method,
282 u8 rf_path,
283 u8 channel_mapped_index);
284 void rtl8821ae_dm_txpwr_track_set_pwr(struct ieee80211_hw *hw,
285 enum pwr_track_control_method method,
286 u8 rf_path, u8 channel_mapped_index);
287
288 void rtl8821ae_dm_update_init_rate(struct ieee80211_hw *hw, u8 rate);
289 u8 rtl8821ae_hw_rate_to_mrate(struct ieee80211_hw *hw, u8 rate);
290 void rtl8812ae_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw);
291 void rtl8821ae_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw);
292
293 #endif