drivers/net/wireless/realtek/rtlwifi/rtl8192se/def.h

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   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright(c) 2009-2012  Realtek Corporation.*/
   3 
   4 #ifndef __REALTEK_92S_DEF_H__
   5 #define __REALTEK_92S_DEF_H__
   6 
   7 #define RX_MPDU_QUEUE                           0
   8 #define RX_CMD_QUEUE                            1
   9 
  10 #define SHORT_SLOT_TIME                         9
  11 #define NON_SHORT_SLOT_TIME                     20
  12 
  13 /* Queue Select Value in TxDesc */
  14 #define QSLT_BK                                 0x2
  15 #define QSLT_BE                                 0x0
  16 #define QSLT_VI                                 0x5
  17 #define QSLT_VO                                 0x6
  18 #define QSLT_BEACON                             0x10
  19 #define QSLT_HIGH                               0x11
  20 #define QSLT_MGNT                               0x12
  21 #define QSLT_CMD                                0x13
  22 
  23 /* Tx Desc */
  24 #define TX_DESC_SIZE_RTL8192S                   (16 * 4)
  25 #define TX_CMDDESC_SIZE_RTL8192S                (16 * 4)
  26 
  27 /* Define a macro that takes a le32 word, converts it to host ordering,
  28  * right shifts by a specified count, creates a mask of the specified
  29  * bit count, and extracts that number of bits.
  30  */
  31 
  32 #define SHIFT_AND_MASK_LE(__pdesc, __shift, __mask)             \
  33         ((le32_to_cpu(*(((__le32 *)(__pdesc)))) >> (__shift)) & \
  34         BIT_LEN_MASK_32(__mask))
  35 
  36 /* Define a macro that clears a bit field in an le32 word and
  37  * sets the specified value into that bit field. The resulting
  38  * value remains in le32 ordering; however, it is properly converted
  39  * to host ordering for the clear and set operations before conversion
  40  * back to le32.
  41  */
  42 
  43 #define SET_BITS_OFFSET_LE(__pdesc, __shift, __len, __val)      \
  44         (*(__le32 *)(__pdesc) =                                 \
  45         (cpu_to_le32((le32_to_cpu(*((__le32 *)(__pdesc))) &     \
  46         (~(BIT_OFFSET_LEN_MASK_32((__shift), __len)))) |        \
  47         (((u32)(__val) & BIT_LEN_MASK_32(__len)) << (__shift)))));
  48 
  49 /* macros to read/write various fields in RX or TX descriptors */
  50 
  51 /* Dword 0 */
  52 #define SET_TX_DESC_PKT_SIZE(__pdesc, __val)                    \
  53         SET_BITS_OFFSET_LE(__pdesc, 0, 16, __val)
  54 #define SET_TX_DESC_OFFSET(__pdesc, __val)                      \
  55         SET_BITS_OFFSET_LE(__pdesc, 16, 8, __val)
  56 #define SET_TX_DESC_TYPE(__pdesc, __val)                        \
  57         SET_BITS_OFFSET_LE(__pdesc, 24, 2, __val)
  58 #define SET_TX_DESC_LAST_SEG(__pdesc, __val)                    \
  59         SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val)
  60 #define SET_TX_DESC_FIRST_SEG(__pdesc, __val)                   \
  61         SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val)
  62 #define SET_TX_DESC_LINIP(__pdesc, __val)                       \
  63         SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val)
  64 #define SET_TX_DESC_AMSDU(__pdesc, __val)                       \
  65         SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val)
  66 #define SET_TX_DESC_GREEN_FIELD(__pdesc, __val)                 \
  67         SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
  68 #define SET_TX_DESC_OWN(__pdesc, __val)                         \
  69         SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
  70 
  71 #define GET_TX_DESC_OWN(__pdesc)                                \
  72         SHIFT_AND_MASK_LE(__pdesc, 31, 1)
  73 
  74 /* Dword 1 */
  75 #define SET_TX_DESC_MACID(__pdesc, __val)                       \
  76         SET_BITS_OFFSET_LE(__pdesc + 4, 0, 5, __val)
  77 #define SET_TX_DESC_MORE_DATA(__pdesc, __val)                   \
  78         SET_BITS_OFFSET_LE(__pdesc + 4, 5, 1, __val)
  79 #define SET_TX_DESC_MORE_FRAG(__pdesc, __val)                   \
  80         SET_BITS_OFFSET_LE(__pdesc + 4, 6, 1, __val)
  81 #define SET_TX_DESC_PIFS(__pdesc, __val)                        \
  82         SET_BITS_OFFSET_LE(__pdesc + 4, 7, 1, __val)
  83 #define SET_TX_DESC_QUEUE_SEL(__pdesc, __val)                   \
  84         SET_BITS_OFFSET_LE(__pdesc + 4, 8, 5, __val)
  85 #define SET_TX_DESC_ACK_POLICY(__pdesc, __val)                  \
  86         SET_BITS_OFFSET_LE(__pdesc + 4, 13, 2, __val)
  87 #define SET_TX_DESC_NO_ACM(__pdesc, __val)                      \
  88         SET_BITS_OFFSET_LE(__pdesc + 4, 15, 1, __val)
  89 #define SET_TX_DESC_NON_QOS(__pdesc, __val)                     \
  90         SET_BITS_OFFSET_LE(__pdesc + 4, 16, 1, __val)
  91 #define SET_TX_DESC_KEY_ID(__pdesc, __val)                      \
  92         SET_BITS_OFFSET_LE(__pdesc + 4, 17, 2, __val)
  93 #define SET_TX_DESC_OUI(__pdesc, __val)                         \
  94         SET_BITS_OFFSET_LE(__pdesc + 4, 19, 1, __val)
  95 #define SET_TX_DESC_PKT_TYPE(__pdesc, __val)                    \
  96         SET_BITS_OFFSET_LE(__pdesc + 4, 20, 1, __val)
  97 #define SET_TX_DESC_EN_DESC_ID(__pdesc, __val)                  \
  98         SET_BITS_OFFSET_LE(__pdesc + 4, 21, 1, __val)
  99 #define SET_TX_DESC_SEC_TYPE(__pdesc, __val)                    \
 100         SET_BITS_OFFSET_LE(__pdesc + 4, 22, 2, __val)
 101 #define SET_TX_DESC_WDS(__pdesc, __val)                         \
 102         SET_BITS_OFFSET_LE(__pdesc + 4, 24, 1, __val)
 103 #define SET_TX_DESC_HTC(__pdesc, __val)                         \
 104         SET_BITS_OFFSET_LE(__pdesc + 4, 25, 1, __val)
 105 #define SET_TX_DESC_PKT_OFFSET(__pdesc, __val)                  \
 106         SET_BITS_OFFSET_LE(__pdesc + 4, 26, 5, __val)
 107 #define SET_TX_DESC_HWPC(__pdesc, __val)                        \
 108         SET_BITS_OFFSET_LE(__pdesc + 4, 27, 1, __val)
 109 
 110 /* Dword 2 */
 111 #define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val)            \
 112         SET_BITS_OFFSET_LE(__pdesc + 8, 0, 6, __val)
 113 #define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val)          \
 114         SET_BITS_OFFSET_LE(__pdesc + 8, 6, 1, __val)
 115 #define SET_TX_DESC_TSFL(__pdesc, __val)                        \
 116         SET_BITS_OFFSET_LE(__pdesc + 8, 7, 5, __val)
 117 #define SET_TX_DESC_RTS_RETRY_COUNT(__pdesc, __val)             \
 118         SET_BITS_OFFSET_LE(__pdesc + 8, 12, 6, __val)
 119 #define SET_TX_DESC_DATA_RETRY_COUNT(__pdesc, __val)            \
 120         SET_BITS_OFFSET_LE(__pdesc + 8, 18, 6, __val)
 121 #define SET_TX_DESC_RSVD_MACID(__pdesc, __val)                  \
 122         SET_BITS_OFFSET_LE(((__pdesc) + 8), 24, 5, __val)
 123 #define SET_TX_DESC_AGG_ENABLE(__pdesc, __val)                  \
 124         SET_BITS_OFFSET_LE(__pdesc + 8, 29, 1, __val)
 125 #define SET_TX_DESC_AGG_BREAK(__pdesc, __val)                   \
 126         SET_BITS_OFFSET_LE(__pdesc + 8, 30, 1, __val)
 127 #define SET_TX_DESC_OWN_MAC(__pdesc, __val)                     \
 128         SET_BITS_OFFSET_LE(__pdesc + 8, 31, 1, __val)
 129 
 130 /* Dword 3 */
 131 #define SET_TX_DESC_NEXT_HEAP_PAGE(__pdesc, __val)              \
 132         SET_BITS_OFFSET_LE(__pdesc + 12, 0, 8, __val)
 133 #define SET_TX_DESC_TAIL_PAGE(__pdesc, __val)                   \
 134         SET_BITS_OFFSET_LE(__pdesc + 12, 8, 8, __val)
 135 #define SET_TX_DESC_SEQ(__pdesc, __val)                         \
 136         SET_BITS_OFFSET_LE(__pdesc + 12, 16, 12, __val)
 137 #define SET_TX_DESC_FRAG(__pdesc, __val)                        \
 138         SET_BITS_OFFSET_LE(__pdesc + 12, 28, 4, __val)
 139 
 140 /* Dword 4 */
 141 #define SET_TX_DESC_RTS_RATE(__pdesc, __val)                    \
 142         SET_BITS_OFFSET_LE(__pdesc + 16, 0, 6, __val)
 143 #define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val)              \
 144         SET_BITS_OFFSET_LE(__pdesc + 16, 6, 1, __val)
 145 #define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val)           \
 146         SET_BITS_OFFSET_LE(__pdesc + 16, 7, 4, __val)
 147 #define SET_TX_DESC_CTS_ENABLE(__pdesc, __val)                  \
 148         SET_BITS_OFFSET_LE(__pdesc + 16, 11, 1, __val)
 149 #define SET_TX_DESC_RTS_ENABLE(__pdesc, __val)                  \
 150         SET_BITS_OFFSET_LE(__pdesc + 16, 12, 1, __val)
 151 #define SET_TX_DESC_RA_BRSR_ID(__pdesc, __val)                  \
 152         SET_BITS_OFFSET_LE(__pdesc + 16, 13, 3, __val)
 153 #define SET_TX_DESC_TXHT(__pdesc, __val)                        \
 154         SET_BITS_OFFSET_LE(__pdesc + 16, 16, 1, __val)
 155 #define SET_TX_DESC_TX_SHORT(__pdesc, __val)                    \
 156         SET_BITS_OFFSET_LE(__pdesc + 16, 17, 1, __val)
 157 #define SET_TX_DESC_TX_BANDWIDTH(__pdesc, __val)                \
 158         SET_BITS_OFFSET_LE(__pdesc + 16, 18, 1, __val)
 159 #define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val)              \
 160         SET_BITS_OFFSET_LE(__pdesc + 16, 19, 2, __val)
 161 #define SET_TX_DESC_TX_STBC(__pdesc, __val)                     \
 162         SET_BITS_OFFSET_LE(__pdesc + 16, 21, 2, __val)
 163 #define SET_TX_DESC_TX_REVERSE_DIRECTION(__pdesc, __val)        \
 164         SET_BITS_OFFSET_LE(__pdesc + 16, 23, 1, __val)
 165 #define SET_TX_DESC_RTS_HT(__pdesc, __val)                      \
 166         SET_BITS_OFFSET_LE(__pdesc + 16, 24, 1, __val)
 167 #define SET_TX_DESC_RTS_SHORT(__pdesc, __val)                   \
 168         SET_BITS_OFFSET_LE(__pdesc + 16, 25, 1, __val)
 169 #define SET_TX_DESC_RTS_BANDWIDTH(__pdesc, __val)               \
 170         SET_BITS_OFFSET_LE(__pdesc + 16, 26, 1, __val)
 171 #define SET_TX_DESC_RTS_SUB_CARRIER(__pdesc, __val)             \
 172         SET_BITS_OFFSET_LE(__pdesc + 16, 27, 2, __val)
 173 #define SET_TX_DESC_RTS_STBC(__pdesc, __val)                    \
 174         SET_BITS_OFFSET_LE(__pdesc + 16, 29, 2, __val)
 175 #define SET_TX_DESC_USER_RATE(__pdesc, __val)                   \
 176         SET_BITS_OFFSET_LE(__pdesc + 16, 31, 1, __val)
 177 
 178 /* Dword 5 */
 179 #define SET_TX_DESC_PACKET_ID(__pdesc, __val)                   \
 180         SET_BITS_OFFSET_LE(__pdesc + 20, 0, 9, __val)
 181 #define SET_TX_DESC_TX_RATE(__pdesc, __val)                     \
 182         SET_BITS_OFFSET_LE(__pdesc + 20, 9, 6, __val)
 183 #define SET_TX_DESC_DISABLE_FB(__pdesc, __val)                  \
 184         SET_BITS_OFFSET_LE(__pdesc + 20, 15, 1, __val)
 185 #define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val)          \
 186         SET_BITS_OFFSET_LE(__pdesc + 20, 16, 5, __val)
 187 #define SET_TX_DESC_TX_AGC(__pdesc, __val)                      \
 188         SET_BITS_OFFSET_LE(__pdesc + 20, 21, 11, __val)
 189 
 190 /* Dword 6 */
 191 #define SET_TX_DESC_IP_CHECK_SUM(__pdesc, __val)                \
 192         SET_BITS_OFFSET_LE(__pdesc + 24, 0, 16, __val)
 193 #define SET_TX_DESC_TCP_CHECK_SUM(__pdesc, __val)               \
 194         SET_BITS_OFFSET_LE(__pdesc + 24, 16, 16, __val)
 195 
 196 /* Dword 7 */
 197 #define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val)              \
 198         SET_BITS_OFFSET_LE(__pdesc + 28, 0, 16, __val)
 199 #define SET_TX_DESC_IP_HEADER_OFFSET(__pdesc, __val)            \
 200         SET_BITS_OFFSET_LE(__pdesc + 28, 16, 8, __val)
 201 #define SET_TX_DESC_TCP_ENABLE(__pdesc, __val)                  \
 202         SET_BITS_OFFSET_LE(__pdesc + 28, 31, 1, __val)
 203 
 204 /* Dword 8 */
 205 #define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val)           \
 206         SET_BITS_OFFSET_LE(__pdesc + 32, 0, 32, __val)
 207 #define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc)                  \
 208         SHIFT_AND_MASK_LE(__pdesc + 32, 0, 32)
 209 
 210 /* Dword 9 */
 211 #define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val)           \
 212         SET_BITS_OFFSET_LE(__pdesc + 36, 0, 32, __val)
 213 
 214 /* Because the PCI Tx descriptors are chaied at the
 215  * initialization and all the NextDescAddresses in
 216  * these descriptors cannot not be cleared (,or
 217  * driver/HW cannot find the next descriptor), the
 218  * offset 36 (NextDescAddresses) is reserved when
 219  * the desc is cleared. */
 220 #define TX_DESC_NEXT_DESC_OFFSET                        36
 221 #define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size)               \
 222         memset(__pdesc, 0, min_t(size_t, _size, TX_DESC_NEXT_DESC_OFFSET))
 223 
 224 /* Rx Desc */
 225 #define RX_STATUS_DESC_SIZE                             24
 226 #define RX_DRV_INFO_SIZE_UNIT                           8
 227 
 228 /* DWORD 0 */
 229 #define SET_RX_STATUS_DESC_PKT_LEN(__pdesc, __val)              \
 230         SET_BITS_OFFSET_LE(__pdesc, 0, 14, __val)
 231 #define SET_RX_STATUS_DESC_CRC32(__pdesc, __val)                \
 232         SET_BITS_OFFSET_LE(__pdesc, 14, 1, __val)
 233 #define SET_RX_STATUS_DESC_ICV(__pdesc, __val)                  \
 234         SET_BITS_OFFSET_LE(__pdesc, 15, 1, __val)
 235 #define SET_RX_STATUS_DESC_DRVINFO_SIZE(__pdesc, __val)         \
 236         SET_BITS_OFFSET_LE(__pdesc, 16, 4, __val)
 237 #define SET_RX_STATUS_DESC_SECURITY(__pdesc, __val)             \
 238         SET_BITS_OFFSET_LE(__pdesc, 20, 3, __val)
 239 #define SET_RX_STATUS_DESC_QOS(__pdesc, __val)                  \
 240         SET_BITS_OFFSET_LE(__pdesc, 23, 1, __val)
 241 #define SET_RX_STATUS_DESC_SHIFT(__pdesc, __val)                \
 242         SET_BITS_OFFSET_LE(__pdesc, 24, 2, __val)
 243 #define SET_RX_STATUS_DESC_PHY_STATUS(__pdesc, __val)           \
 244         SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val)
 245 #define SET_RX_STATUS_DESC_SWDEC(__pdesc, __val)                \
 246         SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val)
 247 #define SET_RX_STATUS_DESC_LAST_SEG(__pdesc, __val)             \
 248         SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val)
 249 #define SET_RX_STATUS_DESC_FIRST_SEG(__pdesc, __val)            \
 250         SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val)
 251 #define SET_RX_STATUS_DESC_EOR(__pdesc, __val)                  \
 252         SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
 253 #define SET_RX_STATUS_DESC_OWN(__pdesc, __val)                  \
 254         SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
 255 
 256 #define GET_RX_STATUS_DESC_PKT_LEN(__pdesc)                     \
 257         SHIFT_AND_MASK_LE(__pdesc, 0, 14)
 258 #define GET_RX_STATUS_DESC_CRC32(__pdesc)                       \
 259         SHIFT_AND_MASK_LE(__pdesc, 14, 1)
 260 #define GET_RX_STATUS_DESC_ICV(__pdesc)                         \
 261         SHIFT_AND_MASK_LE(__pdesc, 15, 1)
 262 #define GET_RX_STATUS_DESC_DRVINFO_SIZE(__pdesc)                \
 263         SHIFT_AND_MASK_LE(__pdesc, 16, 4)
 264 #define GET_RX_STATUS_DESC_SECURITY(__pdesc)                    \
 265         SHIFT_AND_MASK_LE(__pdesc, 20, 3)
 266 #define GET_RX_STATUS_DESC_QOS(__pdesc)                         \
 267         SHIFT_AND_MASK_LE(__pdesc, 23, 1)
 268 #define GET_RX_STATUS_DESC_SHIFT(__pdesc)                       \
 269         SHIFT_AND_MASK_LE(__pdesc, 24, 2)
 270 #define GET_RX_STATUS_DESC_PHY_STATUS(__pdesc)                  \
 271         SHIFT_AND_MASK_LE(__pdesc, 26, 1)
 272 #define GET_RX_STATUS_DESC_SWDEC(__pdesc)                       \
 273         SHIFT_AND_MASK_LE(__pdesc, 27, 1)
 274 #define GET_RX_STATUS_DESC_LAST_SEG(__pdesc)                    \
 275         SHIFT_AND_MASK_LE(__pdesc, 28, 1)
 276 #define GET_RX_STATUS_DESC_FIRST_SEG(__pdesc)                   \
 277         SHIFT_AND_MASK_LE(__pdesc, 29, 1)
 278 #define GET_RX_STATUS_DESC_EOR(__pdesc)                         \
 279         SHIFT_AND_MASK_LE(__pdesc, 30, 1)
 280 #define GET_RX_STATUS_DESC_OWN(__pdesc)                         \
 281         SHIFT_AND_MASK_LE(__pdesc, 31, 1)
 282 
 283 /* DWORD 1 */
 284 #define SET_RX_STATUS_DESC_MACID(__pdesc, __val)                \
 285         SET_BITS_OFFSET_LE(__pdesc + 4, 0, 5, __val)
 286 #define SET_RX_STATUS_DESC_TID(__pdesc, __val)                  \
 287         SET_BITS_OFFSET_LE(__pdesc + 4, 5, 4, __val)
 288 #define SET_RX_STATUS_DESC_PAGGR(__pdesc, __val)                \
 289         SET_BITS_OFFSET_LE(__pdesc + 4, 14, 1, __val)
 290 #define SET_RX_STATUS_DESC_FAGGR(__pdesc, __val)                \
 291         SET_BITS_OFFSET_LE(__pdesc + 4, 15, 1, __val)
 292 #define SET_RX_STATUS_DESC_A1_FIT(__pdesc, __val)               \
 293         SET_BITS_OFFSET_LE(__pdesc + 4, 16, 4, __val)
 294 #define SET_RX_STATUS_DESC_A2_FIT(__pdesc, __val)               \
 295         SET_BITS_OFFSET_LE(__pdesc + 4, 20, 4, __val)
 296 #define SET_RX_STATUS_DESC_PAM(__pdesc, __val)                  \
 297         SET_BITS_OFFSET_LE(__pdesc + 4, 24, 1, __val)
 298 #define SET_RX_STATUS_DESC_PWR(__pdesc, __val)                  \
 299         SET_BITS_OFFSET_LE(__pdesc + 4, 25, 1, __val)
 300 #define SET_RX_STATUS_DESC_MOREDATA(__pdesc, __val)             \
 301         SET_BITS_OFFSET_LE(__pdesc + 4, 26, 1, __val)
 302 #define SET_RX_STATUS_DESC_MOREFRAG(__pdesc, __val)             \
 303         SET_BITS_OFFSET_LE(__pdesc + 4, 27, 1, __val)
 304 #define SET_RX_STATUS_DESC_TYPE(__pdesc, __val)                 \
 305         SET_BITS_OFFSET_LE(__pdesc + 4, 28, 2, __val)
 306 #define SET_RX_STATUS_DESC_MC(__pdesc, __val)                   \
 307         SET_BITS_OFFSET_LE(__pdesc + 4, 30, 1, __val)
 308 #define SET_RX_STATUS_DESC_BC(__pdesc, __val)                   \
 309         SET_BITS_OFFSET_LE(__pdesc + 4, 31, 1, __val)
 310 
 311 #define GET_RX_STATUS_DEC_MACID(__pdesc)                        \
 312         SHIFT_AND_MASK_LE(__pdesc + 4, 0, 5)
 313 #define GET_RX_STATUS_DESC_TID(__pdesc)                         \
 314         SHIFT_AND_MASK_LE(__pdesc + 4, 5, 4)
 315 #define GET_RX_STATUS_DESC_PAGGR(__pdesc)                       \
 316         SHIFT_AND_MASK_LE(__pdesc + 4, 14, 1)
 317 #define GET_RX_STATUS_DESC_FAGGR(__pdesc)                       \
 318         SHIFT_AND_MASK_LE(__pdesc + 4, 15, 1)
 319 #define GET_RX_STATUS_DESC_A1_FIT(__pdesc)                      \
 320         SHIFT_AND_MASK_LE(__pdesc + 4, 16, 4)
 321 #define GET_RX_STATUS_DESC_A2_FIT(__pdesc)                      \
 322         SHIFT_AND_MASK_LE(__pdesc + 4, 20, 4)
 323 #define GET_RX_STATUS_DESC_PAM(__pdesc)                         \
 324         SHIFT_AND_MASK_LE(__pdesc + 4, 24, 1)
 325 #define GET_RX_STATUS_DESC_PWR(__pdesc)                         \
 326         SHIFT_AND_MASK_LE(__pdesc + 4, 25, 1)
 327 #define GET_RX_STATUS_DESC_MORE_DATA(__pdesc)                   \
 328         SHIFT_AND_MASK_LE(__pdesc + 4, 26, 1)
 329 #define GET_RX_STATUS_DESC_MORE_FRAG(__pdesc)                   \
 330         SHIFT_AND_MASK_LE(__pdesc + 4, 27, 1)
 331 #define GET_RX_STATUS_DESC_TYPE(__pdesc)                        \
 332         SHIFT_AND_MASK_LE(__pdesc + 4, 28, 2)
 333 #define GET_RX_STATUS_DESC_MC(__pdesc)                          \
 334         SHIFT_AND_MASK_LE(__pdesc + 4, 30, 1)
 335 #define GET_RX_STATUS_DESC_BC(__pdesc)                          \
 336         SHIFT_AND_MASK_LE(__pdesc + 4, 31, 1)
 337 
 338 /* DWORD 2 */
 339 #define SET_RX_STATUS_DESC_SEQ(__pdesc, __val)                  \
 340         SET_BITS_OFFSET_LE(__pdesc + 8, 0, 12, __val)
 341 #define SET_RX_STATUS_DESC_FRAG(__pdesc, __val)                 \
 342         SET_BITS_OFFSET_LE(__pdesc + 8, 12, 4, __val)
 343 #define SET_RX_STATUS_DESC_NEXT_PKTLEN(__pdesc, __val)          \
 344         SET_BITS_OFFSET_LE(__pdesc + 8, 16, 8, __val)
 345 #define SET_RX_STATUS_DESC_NEXT_IND(__pdesc, __val)             \
 346         SET_BITS_OFFSET_LE(__pdesc + 8, 30, 1, __val)
 347 
 348 #define GET_RX_STATUS_DESC_SEQ(__pdesc)                         \
 349         SHIFT_AND_MASK_LE(__pdesc + 8, 0, 12)
 350 #define GET_RX_STATUS_DESC_FRAG(__pdesc)                        \
 351         SHIFT_AND_MASK_LE(__pdesc + 8, 12, 4)
 352 #define GET_RX_STATUS_DESC_NEXT_PKTLEN(__pdesc)                 \
 353         SHIFT_AND_MASK_LE(__pdesc + 8, 16, 8)
 354 #define GET_RX_STATUS_DESC_NEXT_IND(__pdesc)                    \
 355         SHIFT_AND_MASK_LE(__pdesc + 8, 30, 1)
 356 
 357 /* DWORD 3 */
 358 #define SET_RX_STATUS_DESC_RX_MCS(__pdesc, __val)               \
 359         SET_BITS_OFFSET_LE(__pdesc + 12, 0, 6, __val)
 360 #define SET_RX_STATUS_DESC_RX_HT(__pdesc, __val)                \
 361         SET_BITS_OFFSET_LE(__pdesc + 12, 6, 1, __val)
 362 #define SET_RX_STATUS_DESC_AMSDU(__pdesc, __val)                \
 363         SET_BITS_OFFSET_LE(__pdesc + 12, 7, 1, __val)
 364 #define SET_RX_STATUS_DESC_SPLCP(__pdesc, __val)                \
 365         SET_BITS_OFFSET_LE(__pdesc + 12, 8, 1, __val)
 366 #define SET_RX_STATUS_DESC_BW(__pdesc, __val)                   \
 367         SET_BITS_OFFSET_LE(__pdesc + 12, 9, 1, __val)
 368 #define SET_RX_STATUS_DESC_HTC(__pdesc, __val)                  \
 369         SET_BITS_OFFSET_LE(__pdesc + 12, 10, 1, __val)
 370 #define SET_RX_STATUS_DESC_TCP_CHK_RPT(__pdesc, __val)          \
 371         SET_BITS_OFFSET_LE(__pdesc + 12, 11, 1, __val)
 372 #define SET_RX_STATUS_DESC_IP_CHK_RPT(__pdesc, __val)           \
 373         SET_BITS_OFFSET_LE(__pdesc + 12, 12, 1, __val)
 374 #define SET_RX_STATUS_DESC_TCP_CHK_VALID(__pdesc, __val)        \
 375         SET_BITS_OFFSET_LE(__pdesc + 12, 13, 1, __val)
 376 #define SET_RX_STATUS_DESC_HWPC_ERR(__pdesc, __val)             \
 377         SET_BITS_OFFSET_LE(__pdesc + 12, 14, 1, __val)
 378 #define SET_RX_STATUS_DESC_HWPC_IND(__pdesc, __val)             \
 379         SET_BITS_OFFSET_LE(__pdesc + 12, 15, 1, __val)
 380 #define SET_RX_STATUS_DESC_IV0(__pdesc, __val)                  \
 381         SET_BITS_OFFSET_LE(__pdesc + 12, 16, 16, __val)
 382 
 383 #define GET_RX_STATUS_DESC_RX_MCS(__pdesc)                      \
 384         SHIFT_AND_MASK_LE(__pdesc + 12, 0, 6)
 385 #define GET_RX_STATUS_DESC_RX_HT(__pdesc)                       \
 386         SHIFT_AND_MASK_LE(__pdesc + 12, 6, 1)
 387 #define GET_RX_STATUS_DESC_AMSDU(__pdesc)                       \
 388         SHIFT_AND_MASK_LE(__pdesc + 12, 7, 1)
 389 #define GET_RX_STATUS_DESC_SPLCP(__pdesc)                       \
 390         SHIFT_AND_MASK_LE(__pdesc + 12, 8, 1)
 391 #define GET_RX_STATUS_DESC_BW(__pdesc)                          \
 392         SHIFT_AND_MASK_LE(__pdesc + 12, 9, 1)
 393 #define GET_RX_STATUS_DESC_HTC(__pdesc)                         \
 394         SHIFT_AND_MASK_LE(__pdesc + 12, 10, 1)
 395 #define GET_RX_STATUS_DESC_TCP_CHK_RPT(__pdesc)                 \
 396         SHIFT_AND_MASK_LE(__pdesc + 12, 11, 1)
 397 #define GET_RX_STATUS_DESC_IP_CHK_RPT(__pdesc)                  \
 398         SHIFT_AND_MASK_LE(__pdesc + 12, 12, 1)
 399 #define GET_RX_STATUS_DESC_TCP_CHK_VALID(__pdesc)               \
 400         SHIFT_AND_MASK_LE(__pdesc + 12, 13, 1)
 401 #define GET_RX_STATUS_DESC_HWPC_ERR(__pdesc)                    \
 402         SHIFT_AND_MASK_LE(__pdesc + 12, 14, 1)
 403 #define GET_RX_STATUS_DESC_HWPC_IND(__pdesc)                    \
 404         SHIFT_AND_MASK_LE(__pdesc + 12, 15, 1)
 405 #define GET_RX_STATUS_DESC_IV0(__pdesc)                         \
 406         SHIFT_AND_MASK_LE(__pdesc + 12, 16, 16)
 407 
 408 /* DWORD 4 */
 409 #define SET_RX_STATUS_DESC_IV1(__pdesc, __val)                  \
 410         SET_BITS_OFFSET_LE(__pdesc + 16, 0, 32, __val)
 411 #define GET_RX_STATUS_DESC_IV1(__pdesc)                         \
 412         SHIFT_AND_MASK_LE(__pdesc + 16, 0, 32)
 413 
 414 /* DWORD 5 */
 415 #define SET_RX_STATUS_DESC_TSFL(__pdesc, __val)                 \
 416         SET_BITS_OFFSET_LE(__pdesc + 20, 0, 32, __val)
 417 #define GET_RX_STATUS_DESC_TSFL(__pdesc)                        \
 418         SHIFT_AND_MASK_LE(__pdesc + 20, 0, 32)
 419 
 420 /* DWORD 6 */
 421 #define SET_RX_STATUS__DESC_BUFF_ADDR(__pdesc, __val)   \
 422         SET_BITS_OFFSET_LE(__pdesc + 24, 0, 32, __val)
 423 #define GET_RX_STATUS_DESC_BUFF_ADDR(__pdesc)                   \
 424         SHIFT_AND_MASK_LE(__pdesc + 24, 0, 32)
 425 
 426 #define SE_RX_HAL_IS_CCK_RATE(_pdesc)\
 427         (GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC_RATE1M ||    \
 428          GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC_RATE2M ||    \
 429          GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC_RATE5_5M ||\
 430          GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC_RATE11M)
 431 
 432 enum rf_optype {
 433         RF_OP_BY_SW_3WIRE = 0,
 434         RF_OP_BY_FW,
 435         RF_OP_MAX
 436 };
 437 
 438 enum ic_inferiority {
 439         IC_INFERIORITY_A = 0,
 440         IC_INFERIORITY_B = 1,
 441 };
 442 
 443 enum fwcmd_iotype {
 444         /* For DIG DM */
 445         FW_CMD_DIG_ENABLE = 0,
 446         FW_CMD_DIG_DISABLE = 1,
 447         FW_CMD_DIG_HALT = 2,
 448         FW_CMD_DIG_RESUME = 3,
 449         /* For High Power DM */
 450         FW_CMD_HIGH_PWR_ENABLE = 4,
 451         FW_CMD_HIGH_PWR_DISABLE = 5,
 452         /* For Rate adaptive DM */
 453         FW_CMD_RA_RESET = 6,
 454         FW_CMD_RA_ACTIVE = 7,
 455         FW_CMD_RA_REFRESH_N = 8,
 456         FW_CMD_RA_REFRESH_BG = 9,
 457         FW_CMD_RA_INIT = 10,
 458         /* For FW supported IQK */
 459         FW_CMD_IQK_INIT = 11,
 460         /* Tx power tracking switch,
 461          * MP driver only */
 462         FW_CMD_TXPWR_TRACK_ENABLE = 12,
 463         /* Tx power tracking switch,
 464          * MP driver only */
 465         FW_CMD_TXPWR_TRACK_DISABLE = 13,
 466         /* Tx power tracking with thermal
 467          * indication, for Normal driver */
 468         FW_CMD_TXPWR_TRACK_THERMAL = 14,
 469         FW_CMD_PAUSE_DM_BY_SCAN = 15,
 470         FW_CMD_RESUME_DM_BY_SCAN = 16,
 471         FW_CMD_RA_REFRESH_N_COMB = 17,
 472         FW_CMD_RA_REFRESH_BG_COMB = 18,
 473         FW_CMD_ANTENNA_SW_ENABLE = 19,
 474         FW_CMD_ANTENNA_SW_DISABLE = 20,
 475         /* Tx Status report for CCX from FW */
 476         FW_CMD_TX_FEEDBACK_CCX_ENABLE = 21,
 477         /* Indifate firmware that driver
 478          * enters LPS, For PS-Poll issue */
 479         FW_CMD_LPS_ENTER = 22,
 480         /* Indicate firmware that driver
 481          * leave LPS*/
 482         FW_CMD_LPS_LEAVE = 23,
 483         /* Set DIG mode to signal strength */
 484         FW_CMD_DIG_MODE_SS = 24,
 485         /* Set DIG mode to false alarm. */
 486         FW_CMD_DIG_MODE_FA = 25,
 487         FW_CMD_ADD_A2_ENTRY = 26,
 488         FW_CMD_CTRL_DM_BY_DRIVER = 27,
 489         FW_CMD_CTRL_DM_BY_DRIVER_NEW = 28,
 490         FW_CMD_PAPE_CONTROL = 29,
 491         FW_CMD_IQK_ENABLE = 30,
 492 };
 493 
 494 /* Driver info contain PHY status
 495  * and other variabel size info
 496  * PHY Status content as below
 497  */
 498 struct  rx_fwinfo {
 499         /* DWORD 0 */
 500         u8 gain_trsw[4];
 501         /* DWORD 1 */
 502         u8 pwdb_all;
 503         u8 cfosho[4];
 504         /* DWORD 2 */
 505         u8 cfotail[4];
 506         /* DWORD 3 */
 507         s8 rxevm[2];
 508         s8 rxsnr[4];
 509         /* DWORD 4 */
 510         u8 pdsnr[2];
 511         /* DWORD 5 */
 512         u8 csi_current[2];
 513         u8 csi_target[2];
 514         /* DWORD 6 */
 515         u8 sigevm;
 516         u8 max_ex_pwr;
 517         u8 ex_intf_flag:1;
 518         u8 sgi_en:1;
 519         u8 rxsc:2;
 520         u8 reserve:4;
 521 };
 522 
 523 struct phy_sts_cck_8192s_t {
 524         u8 adc_pwdb_x[4];
 525         u8 sq_rpt;
 526         u8 cck_agc_rpt;
 527 };
 528 
 529 #endif
 530
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root/drivers/net/wireless/realtek/rtlwifi/rtl8192se/def.h

INCLUDED FROM
