This source file includes following definitions.
- rtw_get_rfe_def
- rtw_check_supported_rfe
1
2
3
4
5 #ifndef __RTW_PHY_H_
6 #define __RTW_PHY_H_
7
8 #include "debug.h"
9
10 extern u8 rtw_cck_rates[];
11 extern u8 rtw_ofdm_rates[];
12 extern u8 rtw_ht_1s_rates[];
13 extern u8 rtw_ht_2s_rates[];
14 extern u8 rtw_vht_1s_rates[];
15 extern u8 rtw_vht_2s_rates[];
16 extern u8 *rtw_rate_section[];
17 extern u8 rtw_rate_size[];
18
19 void rtw_phy_init(struct rtw_dev *rtwdev);
20 void rtw_phy_dynamic_mechanism(struct rtw_dev *rtwdev);
21 u8 rtw_phy_rf_power_2_rssi(s8 *rf_power, u8 path_num);
22 u32 rtw_phy_read_rf(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
23 u32 addr, u32 mask);
24 bool rtw_phy_write_rf_reg_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
25 u32 addr, u32 mask, u32 data);
26 bool rtw_phy_write_rf_reg(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
27 u32 addr, u32 mask, u32 data);
28 bool rtw_phy_write_rf_reg_mix(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
29 u32 addr, u32 mask, u32 data);
30 void rtw_phy_setup_phy_cond(struct rtw_dev *rtwdev, u32 pkg);
31 void rtw_parse_tbl_phy_cond(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
32 void rtw_parse_tbl_bb_pg(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
33 void rtw_parse_tbl_txpwr_lmt(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
34 void rtw_phy_cfg_mac(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
35 u32 addr, u32 data);
36 void rtw_phy_cfg_agc(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
37 u32 addr, u32 data);
38 void rtw_phy_cfg_bb(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
39 u32 addr, u32 data);
40 void rtw_phy_cfg_rf(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
41 u32 addr, u32 data);
42 void rtw_phy_init_tx_power(struct rtw_dev *rtwdev);
43 void rtw_phy_load_tables(struct rtw_dev *rtwdev);
44 void rtw_phy_set_tx_power_level(struct rtw_dev *rtwdev, u8 channel);
45 void rtw_phy_tx_power_by_rate_config(struct rtw_hal *hal);
46 void rtw_phy_tx_power_limit_config(struct rtw_hal *hal);
47
48 struct rtw_txpwr_lmt_cfg_pair {
49 u8 regd;
50 u8 band;
51 u8 bw;
52 u8 rs;
53 u8 ch;
54 s8 txpwr_lmt;
55 };
56
57 #define RTW_DECL_TABLE_PHY_COND_CORE(name, cfg, path) \
58 const struct rtw_table name ## _tbl = { \
59 .data = name, \
60 .size = ARRAY_SIZE(name), \
61 .parse = rtw_parse_tbl_phy_cond, \
62 .do_cfg = cfg, \
63 .rf_path = path, \
64 }
65
66 #define RTW_DECL_TABLE_PHY_COND(name, cfg) \
67 RTW_DECL_TABLE_PHY_COND_CORE(name, cfg, 0)
68
69 #define RTW_DECL_TABLE_RF_RADIO(name, path) \
70 RTW_DECL_TABLE_PHY_COND_CORE(name, rtw_phy_cfg_rf, RF_PATH_ ## path)
71
72 #define RTW_DECL_TABLE_BB_PG(name) \
73 const struct rtw_table name ## _tbl = { \
74 .data = name, \
75 .size = ARRAY_SIZE(name), \
76 .parse = rtw_parse_tbl_bb_pg, \
77 }
78
79 #define RTW_DECL_TABLE_TXPWR_LMT(name) \
80 const struct rtw_table name ## _tbl = { \
81 .data = name, \
82 .size = ARRAY_SIZE(name), \
83 .parse = rtw_parse_tbl_txpwr_lmt, \
84 }
85
86 static inline const struct rtw_rfe_def *rtw_get_rfe_def(struct rtw_dev *rtwdev)
87 {
88 struct rtw_chip_info *chip = rtwdev->chip;
89 struct rtw_efuse *efuse = &rtwdev->efuse;
90 const struct rtw_rfe_def *rfe_def = NULL;
91
92 if (chip->rfe_defs_size == 0)
93 return NULL;
94
95 if (efuse->rfe_option < chip->rfe_defs_size)
96 rfe_def = &chip->rfe_defs[efuse->rfe_option];
97
98 rtw_dbg(rtwdev, RTW_DBG_PHY, "use rfe_def[%d]\n", efuse->rfe_option);
99 return rfe_def;
100 }
101
102 static inline int rtw_check_supported_rfe(struct rtw_dev *rtwdev)
103 {
104 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev);
105
106 if (!rfe_def || !rfe_def->phy_pg_tbl || !rfe_def->txpwr_lmt_tbl) {
107 rtw_err(rtwdev, "rfe %d isn't supported\n",
108 rtwdev->efuse.rfe_option);
109 return -ENODEV;
110 }
111
112 return 0;
113 }
114
115 void rtw_phy_dig_write(struct rtw_dev *rtwdev, u8 igi);
116
117 struct rtw_power_params {
118 u8 pwr_base;
119 s8 pwr_offset;
120 s8 pwr_limit;
121 };
122
123 void
124 rtw_get_tx_power_params(struct rtw_dev *rtwdev, u8 path,
125 u8 rate, u8 bw, u8 ch, u8 regd,
126 struct rtw_power_params *pwr_param);
127
128 enum rtw_phy_cck_pd_lv {
129 CCK_PD_LV0,
130 CCK_PD_LV1,
131 CCK_PD_LV2,
132 CCK_PD_LV3,
133 CCK_PD_LV4,
134 CCK_PD_LV_MAX,
135 };
136
137 #define MASKBYTE0 0xff
138 #define MASKBYTE1 0xff00
139 #define MASKBYTE2 0xff0000
140 #define MASKBYTE3 0xff000000
141 #define MASKHWORD 0xffff0000
142 #define MASKLWORD 0x0000ffff
143 #define MASKDWORD 0xffffffff
144 #define RFREG_MASK 0xfffff
145
146 #define MASK7BITS 0x7f
147 #define MASK12BITS 0xfff
148 #define MASKH4BITS 0xf0000000
149 #define MASK20BITS 0xfffff
150 #define MASK24BITS 0xffffff
151
152 #define MASKH3BYTES 0xffffff00
153 #define MASKL3BYTES 0x00ffffff
154 #define MASKBYTE2HIGHNIBBLE 0x00f00000
155 #define MASKBYTE3LOWNIBBLE 0x0f000000
156 #define MASKL3BYTES 0x00ffffff
157
158 #define CCK_FA_AVG_RESET 0xffffffff
159
160 #endif