This source file includes following definitions.
- rtw8822ce_efuse_parsing
- rtw8822c_read_efuse
- rtw8822c_header_file_init
- rtw8822c_dac_backup_reg
- rtw8822c_dac_restore_reg
- rtw8822c_rf_minmax_cmp
- swap_u32
- __rtw8822c_dac_iq_sort
- rtw8822c_dac_iq_sort
- rtw8822c_dac_iq_offset
- rtw8822c_get_path_write_addr
- rtw8822c_get_path_read_addr
- rtw8822c_dac_iq_check
- rtw8822c_dac_cal_iq_sample
- rtw8822c_dac_cal_iq_search
- rtw8822c_dac_cal_rf_mode
- rtw8822c_dac_bb_setting
- rtw8822c_dac_cal_adc
- rtw8822c_dac_cal_step1
- rtw8822c_dac_cal_step2
- rtw8822c_dac_cal_step3
- rtw8822c_dac_cal_step4
- rtw8822c_dac_cal_backup_vec
- rtw8822c_dac_cal_backup_path
- rtw8822c_dac_cal_backup_dck
- rtw8822c_dac_cal_backup
- rtw8822c_dac_cal_restore_dck
- rtw8822c_dac_cal_restore_prepare
- rtw8822c_dac_cal_restore_wait
- rtw8822c_dac_cal_restore_path
- __rtw8822c_dac_cal_restore
- rtw8822c_dac_cal_restore
- rtw8822c_rf_dac_cal
- rtw8822c_rf_x2_check
- rtw8822c_rf_init
- rtw8822c_phy_set_param
- rtw8822c_mac_init
- rtw8822c_set_channel_rf
- rtw8822c_toggle_igi
- rtw8822c_set_channel_bb
- rtw8822c_set_channel
- rtw8822c_config_cck_rx_path
- rtw8822c_config_ofdm_rx_path
- rtw8822c_config_rx_path
- rtw8822c_config_cck_tx_path
- rtw8822c_config_ofdm_tx_path
- rtw8822c_config_tx_path
- rtw8822c_config_trx_mode
- query_phy_status_page0
- query_phy_status_page1
- query_phy_status
- rtw8822c_query_rx_desc
- rtw8822c_set_write_tx_power_ref
- rtw8822c_set_tx_power_diff
- rtw8822c_set_tx_power_index
- rtw8822c_cfg_ldo25
- rtw8822c_false_alarm_statistics
- rtw8822c_do_iqk
- rtw8822c_coex_cfg_init
- rtw8822c_coex_cfg_gnt_fix
- rtw8822c_coex_cfg_gnt_debug
- rtw8822c_coex_cfg_rfe_type
- rtw8822c_coex_cfg_wl_tx_power
- rtw8822c_coex_cfg_wl_rx_gain
- rtw8822c_parse_tbl_dpk
- rtw8822c_dpk_set_gnt_wl
- rtw8822c_dpk_restore_registers
- rtw8822c_dpk_backup_registers
- rtw8822c_dpk_backup_rf_registers
- rtw8822c_dpk_reload_rf_registers
- rtw8822c_dpk_information
- rtw8822c_dpk_rxbb_dc_cal
- rtw8822c_dpk_dc_corr_check
- rtw8822c_dpk_tx_pause
- rtw8822c_dpk_mac_bb_setting
- rtw8822c_dpk_afe_setting
- rtw8822c_dpk_pre_setting
- rtw8822c_dpk_rf_setting
- rtw8822c_dpk_get_cmd
- rtw8822c_dpk_one_shot
- rtw8822c_dpk_dgain_read
- rtw8822c_dpk_thermal_read
- rtw8822c_dpk_pas_read
- rtw8822c_psd_log2base
- rtw8822c_dpk_gainloss_result
- rtw8822c_dpk_agc_gain_chk
- rtw8822c_dpk_agc_loss_chk
- rtw8822c_gain_check_state
- rtw8822c_gain_large_state
- rtw8822c_gain_less_state
- rtw8822c_gl_state
- rtw8822c_gl_large_state
- rtw8822c_gl_less_state
- rtw8822c_loss_check_state
- rtw8822c_dpk_pas_agc
- rtw8822c_dpk_coef_iq_check
- rtw8822c_dpk_coef_transfer
- rtw8822c_dpk_coef_tbl_apply
- rtw8822c_dpk_get_coef
- rtw8822c_dpk_coef_read
- rtw8822c_dpk_coef_write
- rtw8822c_dpk_fill_result
- rtw8822c_dpk_gainloss
- rtw8822c_dpk_by_path
- rtw8822c_dpk_cal_gs
- rtw8822c_dpk_cal_coef1
- rtw8822c_dpk_on
- rtw8822c_dpk_check_pass
- rtw8822c_dpk_result_reset
- rtw8822c_dpk_calibrate
- rtw8822c_dpk_path_select
- rtw8822c_dpk_enable_disable
- rtw8822c_dpk_reload_data
- rtw8822c_dpk_reload
- rtw8822c_do_dpk
- rtw8822c_phy_calibration
- rtw8822c_dpk_track
- rtw8822c_phy_cck_pd_set_reg
- rtw8822c_phy_cck_pd_set
1
2
3
4
5 #include "main.h"
6 #include "coex.h"
7 #include "fw.h"
8 #include "tx.h"
9 #include "rx.h"
10 #include "phy.h"
11 #include "rtw8822c.h"
12 #include "rtw8822c_table.h"
13 #include "mac.h"
14 #include "reg.h"
15 #include "debug.h"
16 #include "util.h"
17
18 static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path,
19 u8 rx_path, bool is_tx2_path);
20
21 static void rtw8822ce_efuse_parsing(struct rtw_efuse *efuse,
22 struct rtw8822c_efuse *map)
23 {
24 ether_addr_copy(efuse->addr, map->e.mac_addr);
25 }
26
27 static int rtw8822c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
28 {
29 struct rtw_efuse *efuse = &rtwdev->efuse;
30 struct rtw8822c_efuse *map;
31 int i;
32
33 map = (struct rtw8822c_efuse *)log_map;
34
35 efuse->rfe_option = map->rfe_option;
36 efuse->rf_board_option = map->rf_board_option;
37 efuse->crystal_cap = map->xtal_k;
38 efuse->channel_plan = map->channel_plan;
39 efuse->country_code[0] = map->country_code[0];
40 efuse->country_code[1] = map->country_code[1];
41 efuse->bt_setting = map->rf_bt_setting;
42 efuse->regd = map->rf_board_option & 0x7;
43
44 for (i = 0; i < 4; i++)
45 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
46
47 switch (rtw_hci_type(rtwdev)) {
48 case RTW_HCI_TYPE_PCIE:
49 rtw8822ce_efuse_parsing(efuse, map);
50 break;
51 default:
52
53 return -ENOTSUPP;
54 }
55
56 return 0;
57 }
58
59 static void rtw8822c_header_file_init(struct rtw_dev *rtwdev, bool pre)
60 {
61 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN);
62 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_PI_ON);
63 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN);
64 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_PI_ON);
65
66 if (pre)
67 rtw_write32_clr(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN);
68 else
69 rtw_write32_set(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN);
70 }
71
72 static void rtw8822c_dac_backup_reg(struct rtw_dev *rtwdev,
73 struct rtw_backup_info *backup,
74 struct rtw_backup_info *backup_rf)
75 {
76 u32 path, i;
77 u32 val;
78 u32 reg;
79 u32 rf_addr[DACK_RF_8822C] = {0x8f};
80 u32 addrs[DACK_REG_8822C] = {0x180c, 0x1810, 0x410c, 0x4110,
81 0x1c3c, 0x1c24, 0x1d70, 0x9b4,
82 0x1a00, 0x1a14, 0x1d58, 0x1c38,
83 0x1e24, 0x1e28, 0x1860, 0x4160};
84
85 for (i = 0; i < DACK_REG_8822C; i++) {
86 backup[i].len = 4;
87 backup[i].reg = addrs[i];
88 backup[i].val = rtw_read32(rtwdev, addrs[i]);
89 }
90
91 for (path = 0; path < DACK_PATH_8822C; path++) {
92 for (i = 0; i < DACK_RF_8822C; i++) {
93 reg = rf_addr[i];
94 val = rtw_read_rf(rtwdev, path, reg, RFREG_MASK);
95 backup_rf[path * i + i].reg = reg;
96 backup_rf[path * i + i].val = val;
97 }
98 }
99 }
100
101 static void rtw8822c_dac_restore_reg(struct rtw_dev *rtwdev,
102 struct rtw_backup_info *backup,
103 struct rtw_backup_info *backup_rf)
104 {
105 u32 path, i;
106 u32 val;
107 u32 reg;
108
109 rtw_restore_reg(rtwdev, backup, DACK_REG_8822C);
110
111 for (path = 0; path < DACK_PATH_8822C; path++) {
112 for (i = 0; i < DACK_RF_8822C; i++) {
113 val = backup_rf[path * i + i].val;
114 reg = backup_rf[path * i + i].reg;
115 rtw_write_rf(rtwdev, path, reg, RFREG_MASK, val);
116 }
117 }
118 }
119
120 static void rtw8822c_rf_minmax_cmp(struct rtw_dev *rtwdev, u32 value,
121 u32 *min, u32 *max)
122 {
123 if (value >= 0x200) {
124 if (*min >= 0x200) {
125 if (*min > value)
126 *min = value;
127 } else {
128 *min = value;
129 }
130 if (*max >= 0x200) {
131 if (*max < value)
132 *max = value;
133 }
134 } else {
135 if (*min < 0x200) {
136 if (*min > value)
137 *min = value;
138 }
139
140 if (*max >= 0x200) {
141 *max = value;
142 } else {
143 if (*max < value)
144 *max = value;
145 }
146 }
147 }
148
149 static void swap_u32(u32 *v1, u32 *v2)
150 {
151 u32 tmp;
152
153 tmp = *v1;
154 *v1 = *v2;
155 *v2 = tmp;
156 }
157
158 static void __rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *v1, u32 *v2)
159 {
160 if (*v1 >= 0x200 && *v2 >= 0x200) {
161 if (*v1 > *v2)
162 swap_u32(v1, v2);
163 } else if (*v1 < 0x200 && *v2 < 0x200) {
164 if (*v1 > *v2)
165 swap_u32(v1, v2);
166 } else if (*v1 < 0x200 && *v2 >= 0x200) {
167 swap_u32(v1, v2);
168 }
169 }
170
171 static void rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *iv, u32 *qv)
172 {
173 u32 i, j;
174
175 for (i = 0; i < DACK_SN_8822C - 1; i++) {
176 for (j = 0; j < (DACK_SN_8822C - 1 - i) ; j++) {
177 __rtw8822c_dac_iq_sort(rtwdev, &iv[j], &iv[j + 1]);
178 __rtw8822c_dac_iq_sort(rtwdev, &qv[j], &qv[j + 1]);
179 }
180 }
181 }
182
183 static void rtw8822c_dac_iq_offset(struct rtw_dev *rtwdev, u32 *vec, u32 *val)
184 {
185 u32 p, m, t, i;
186
187 m = 0;
188 p = 0;
189 for (i = 10; i < DACK_SN_8822C - 10; i++) {
190 if (vec[i] > 0x200)
191 m = (0x400 - vec[i]) + m;
192 else
193 p = vec[i] + p;
194 }
195
196 if (p > m) {
197 t = p - m;
198 t = t / (DACK_SN_8822C - 20);
199 } else {
200 t = m - p;
201 t = t / (DACK_SN_8822C - 20);
202 if (t != 0x0)
203 t = 0x400 - t;
204 }
205
206 *val = t;
207 }
208
209 static u32 rtw8822c_get_path_write_addr(u8 path)
210 {
211 u32 base_addr;
212
213 switch (path) {
214 case RF_PATH_A:
215 base_addr = 0x1800;
216 break;
217 case RF_PATH_B:
218 base_addr = 0x4100;
219 break;
220 default:
221 WARN_ON(1);
222 return -1;
223 }
224
225 return base_addr;
226 }
227
228 static u32 rtw8822c_get_path_read_addr(u8 path)
229 {
230 u32 base_addr;
231
232 switch (path) {
233 case RF_PATH_A:
234 base_addr = 0x2800;
235 break;
236 case RF_PATH_B:
237 base_addr = 0x4500;
238 break;
239 default:
240 WARN_ON(1);
241 return -1;
242 }
243
244 return base_addr;
245 }
246
247 static bool rtw8822c_dac_iq_check(struct rtw_dev *rtwdev, u32 value)
248 {
249 bool ret = true;
250
251 if ((value >= 0x200 && (0x400 - value) > 0x64) ||
252 (value < 0x200 && value > 0x64)) {
253 ret = false;
254 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] Error overflow\n");
255 }
256
257 return ret;
258 }
259
260 static void rtw8822c_dac_cal_iq_sample(struct rtw_dev *rtwdev, u32 *iv, u32 *qv)
261 {
262 u32 temp;
263 int i = 0, cnt = 0;
264
265 while (i < DACK_SN_8822C && cnt < 10000) {
266 cnt++;
267 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
268 iv[i] = (temp & 0x3ff000) >> 12;
269 qv[i] = temp & 0x3ff;
270
271 if (rtw8822c_dac_iq_check(rtwdev, iv[i]) &&
272 rtw8822c_dac_iq_check(rtwdev, qv[i]))
273 i++;
274 }
275 }
276
277 static void rtw8822c_dac_cal_iq_search(struct rtw_dev *rtwdev,
278 u32 *iv, u32 *qv,
279 u32 *i_value, u32 *q_value)
280 {
281 u32 i_max = 0, q_max = 0, i_min = 0, q_min = 0;
282 u32 i_delta, q_delta;
283 u32 temp;
284 int i, cnt = 0;
285
286 do {
287 i_min = iv[0];
288 i_max = iv[0];
289 q_min = qv[0];
290 q_max = qv[0];
291 for (i = 0; i < DACK_SN_8822C; i++) {
292 rtw8822c_rf_minmax_cmp(rtwdev, iv[i], &i_min, &i_max);
293 rtw8822c_rf_minmax_cmp(rtwdev, qv[i], &q_min, &q_max);
294 }
295
296 if (i_max < 0x200 && i_min < 0x200)
297 i_delta = i_max - i_min;
298 else if (i_max >= 0x200 && i_min >= 0x200)
299 i_delta = i_max - i_min;
300 else
301 i_delta = i_max + (0x400 - i_min);
302
303 if (q_max < 0x200 && q_min < 0x200)
304 q_delta = q_max - q_min;
305 else if (q_max >= 0x200 && q_min >= 0x200)
306 q_delta = q_max - q_min;
307 else
308 q_delta = q_max + (0x400 - q_min);
309
310 rtw_dbg(rtwdev, RTW_DBG_RFK,
311 "[DACK] i: min=0x%08x, max=0x%08x, delta=0x%08x\n",
312 i_min, i_max, i_delta);
313 rtw_dbg(rtwdev, RTW_DBG_RFK,
314 "[DACK] q: min=0x%08x, max=0x%08x, delta=0x%08x\n",
315 q_min, q_max, q_delta);
316
317 rtw8822c_dac_iq_sort(rtwdev, iv, qv);
318
319 if (i_delta > 5 || q_delta > 5) {
320 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
321 iv[0] = (temp & 0x3ff000) >> 12;
322 qv[0] = temp & 0x3ff;
323 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
324 iv[DACK_SN_8822C - 1] = (temp & 0x3ff000) >> 12;
325 qv[DACK_SN_8822C - 1] = temp & 0x3ff;
326 } else {
327 break;
328 }
329 } while (cnt++ < 100);
330
331 rtw8822c_dac_iq_offset(rtwdev, iv, i_value);
332 rtw8822c_dac_iq_offset(rtwdev, qv, q_value);
333 }
334
335 static void rtw8822c_dac_cal_rf_mode(struct rtw_dev *rtwdev,
336 u32 *i_value, u32 *q_value)
337 {
338 u32 iv[DACK_SN_8822C], qv[DACK_SN_8822C];
339 u32 rf_a, rf_b;
340
341 rf_a = rtw_read_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK);
342 rf_b = rtw_read_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK);
343
344 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-A=0x%05x\n", rf_a);
345 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-B=0x%05x\n", rf_b);
346
347 rtw8822c_dac_cal_iq_sample(rtwdev, iv, qv);
348 rtw8822c_dac_cal_iq_search(rtwdev, iv, qv, i_value, q_value);
349 }
350
351 static void rtw8822c_dac_bb_setting(struct rtw_dev *rtwdev)
352 {
353 rtw_write32_mask(rtwdev, 0x1d58, 0xff8, 0x1ff);
354 rtw_write32_mask(rtwdev, 0x1a00, 0x3, 0x2);
355 rtw_write32_mask(rtwdev, 0x1a14, 0x300, 0x3);
356 rtw_write32(rtwdev, 0x1d70, 0x7e7e7e7e);
357 rtw_write32_mask(rtwdev, 0x180c, 0x3, 0x0);
358 rtw_write32_mask(rtwdev, 0x410c, 0x3, 0x0);
359 rtw_write32(rtwdev, 0x1b00, 0x00000008);
360 rtw_write8(rtwdev, 0x1bcc, 0x3f);
361 rtw_write32(rtwdev, 0x1b00, 0x0000000a);
362 rtw_write8(rtwdev, 0x1bcc, 0x3f);
363 rtw_write32_mask(rtwdev, 0x1e24, BIT(31), 0x0);
364 rtw_write32_mask(rtwdev, 0x1e28, 0xf, 0x3);
365 }
366
367 static void rtw8822c_dac_cal_adc(struct rtw_dev *rtwdev,
368 u8 path, u32 *adc_ic, u32 *adc_qc)
369 {
370 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
371 u32 ic = 0, qc = 0, temp = 0;
372 u32 base_addr;
373 u32 path_sel;
374 int i;
375
376 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK path(%d)\n", path);
377
378 base_addr = rtw8822c_get_path_write_addr(path);
379 switch (path) {
380 case RF_PATH_A:
381 path_sel = 0xa0000;
382 break;
383 case RF_PATH_B:
384 path_sel = 0x80000;
385 break;
386 default:
387 WARN_ON(1);
388 return;
389 }
390
391
392 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x0);
393 if (path == RF_PATH_B)
394 rtw_write32(rtwdev, base_addr + 0x30, 0x30db8041);
395 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0);
396 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
397 rtw_write32(rtwdev, base_addr + 0x10, 0x02dd08c4);
398 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260);
399 rtw_write_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK, 0x10000);
400 rtw_write_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK, 0x10000);
401 for (i = 0; i < 10; i++) {
402 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK count=%d\n", i);
403 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8003);
404 rtw_write32(rtwdev, 0x1c24, 0x00010002);
405 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc);
406 rtw_dbg(rtwdev, RTW_DBG_RFK,
407 "[DACK] before: i=0x%x, q=0x%x\n", ic, qc);
408
409
410 if (ic != 0x0) {
411 ic = 0x400 - ic;
412 *adc_ic = ic;
413 }
414 if (qc != 0x0) {
415 qc = 0x400 - qc;
416 *adc_qc = qc;
417 }
418 temp = (ic & 0x3ff) | ((qc & 0x3ff) << 10);
419 rtw_write32(rtwdev, base_addr + 0x68, temp);
420 dm_info->dack_adck[path] = temp;
421 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK 0x%08x=0x08%x\n",
422 base_addr + 0x68, temp);
423
424 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8103);
425 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc);
426 rtw_dbg(rtwdev, RTW_DBG_RFK,
427 "[DACK] after: i=0x%08x, q=0x%08x\n", ic, qc);
428 if (ic >= 0x200)
429 ic = 0x400 - ic;
430 if (qc >= 0x200)
431 qc = 0x400 - qc;
432 if (ic < 5 && qc < 5)
433 break;
434 }
435
436
437 rtw_write32(rtwdev, 0x1c3c, 0x00000003);
438 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260);
439 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4);
440
441
442 rtw_write_rf(rtwdev, path, 0x8f, BIT(13), 0x1);
443 }
444
445 static void rtw8822c_dac_cal_step1(struct rtw_dev *rtwdev, u8 path)
446 {
447 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
448 u32 base_addr;
449 u32 read_addr;
450
451 base_addr = rtw8822c_get_path_write_addr(path);
452 read_addr = rtw8822c_get_path_read_addr(path);
453
454 rtw_write32(rtwdev, base_addr + 0x68, dm_info->dack_adck[path]);
455 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
456 if (path == RF_PATH_A) {
457 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0);
458 rtw_write32(rtwdev, 0x1c38, 0xffffffff);
459 }
460 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
461 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
462 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88);
463 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff81);
464 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208);
465 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88);
466 rtw_write32(rtwdev, base_addr + 0xd8, 0x0008ff81);
467 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208);
468 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000);
469 mdelay(2);
470 rtw_write32(rtwdev, base_addr + 0xbc, 0x000aff8d);
471 mdelay(2);
472 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89);
473 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89);
474 mdelay(1);
475 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000);
476 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000);
477 mdelay(20);
478 if (!check_hw_ready(rtwdev, read_addr + 0x08, 0x7fff80, 0xffff) ||
479 !check_hw_ready(rtwdev, read_addr + 0x34, 0x7fff80, 0xffff))
480 rtw_err(rtwdev, "failed to wait for dack ready\n");
481 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000);
482 mdelay(1);
483 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87);
484 rtw_write32(rtwdev, 0x9b4, 0xdb6db600);
485 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
486 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87);
487 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000);
488 }
489
490 static void rtw8822c_dac_cal_step2(struct rtw_dev *rtwdev,
491 u8 path, u32 *ic_out, u32 *qc_out)
492 {
493 u32 base_addr;
494 u32 ic, qc, ic_in, qc_in;
495
496 base_addr = rtw8822c_get_path_write_addr(path);
497 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, 0x0);
498 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, 0x8);
499 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, 0x0);
500 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, 0x8);
501
502 rtw_write32(rtwdev, 0x1b00, 0x00000008);
503 rtw_write8(rtwdev, 0x1bcc, 0x03f);
504 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
505 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
506 rtw_write32(rtwdev, 0x1c3c, 0x00088103);
507
508 rtw8822c_dac_cal_rf_mode(rtwdev, &ic_in, &qc_in);
509 ic = ic_in;
510 qc = qc_in;
511
512
513 if (ic != 0x0)
514 ic = 0x400 - ic;
515 if (qc != 0x0)
516 qc = 0x400 - qc;
517 if (ic < 0x300) {
518 ic = ic * 2 * 6 / 5;
519 ic = ic + 0x80;
520 } else {
521 ic = (0x400 - ic) * 2 * 6 / 5;
522 ic = 0x7f - ic;
523 }
524 if (qc < 0x300) {
525 qc = qc * 2 * 6 / 5;
526 qc = qc + 0x80;
527 } else {
528 qc = (0x400 - qc) * 2 * 6 / 5;
529 qc = 0x7f - qc;
530 }
531
532 *ic_out = ic;
533 *qc_out = qc;
534
535 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] before i=0x%x, q=0x%x\n", ic_in, qc_in);
536 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] after i=0x%x, q=0x%x\n", ic, qc);
537 }
538
539 static void rtw8822c_dac_cal_step3(struct rtw_dev *rtwdev, u8 path,
540 u32 adc_ic, u32 adc_qc,
541 u32 *ic_in, u32 *qc_in,
542 u32 *i_out, u32 *q_out)
543 {
544 u32 base_addr;
545 u32 read_addr;
546 u32 ic, qc;
547 u32 temp;
548
549 base_addr = rtw8822c_get_path_write_addr(path);
550 read_addr = rtw8822c_get_path_read_addr(path);
551 ic = *ic_in;
552 qc = *qc_in;
553
554 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
555 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
556 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
557 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88);
558 rtw_write32(rtwdev, base_addr + 0xbc, 0xc008ff81);
559 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208);
560 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, ic & 0xf);
561 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, (ic & 0xf0) >> 4);
562 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88);
563 rtw_write32(rtwdev, base_addr + 0xd8, 0xe008ff81);
564 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208);
565 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, qc & 0xf);
566 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, (qc & 0xf0) >> 4);
567 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000);
568 mdelay(2);
569 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x6);
570 mdelay(2);
571 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89);
572 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89);
573 mdelay(1);
574 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000);
575 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000);
576 mdelay(20);
577 if (!check_hw_ready(rtwdev, read_addr + 0x24, 0x07f80000, ic) ||
578 !check_hw_ready(rtwdev, read_addr + 0x50, 0x07f80000, qc))
579 rtw_err(rtwdev, "failed to write IQ vector to hardware\n");
580 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000);
581 mdelay(1);
582 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x3);
583 rtw_write32(rtwdev, 0x9b4, 0xdb6db600);
584
585
586 temp = ((adc_ic + 0x10) & 0x3ff) | (((adc_qc + 0x10) & 0x3ff) << 10);
587 rtw_write32(rtwdev, base_addr + 0x68, temp);
588 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
589 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000);
590 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc);
591 if (ic >= 0x10)
592 ic = ic - 0x10;
593 else
594 ic = 0x400 - (0x10 - ic);
595
596 if (qc >= 0x10)
597 qc = qc - 0x10;
598 else
599 qc = 0x400 - (0x10 - qc);
600
601 *i_out = ic;
602 *q_out = qc;
603
604 if (ic >= 0x200)
605 ic = 0x400 - ic;
606 if (qc >= 0x200)
607 qc = 0x400 - qc;
608
609 *ic_in = ic;
610 *qc_in = qc;
611
612 rtw_dbg(rtwdev, RTW_DBG_RFK,
613 "[DACK] after DACK i=0x%x, q=0x%x\n", *i_out, *q_out);
614 }
615
616 static void rtw8822c_dac_cal_step4(struct rtw_dev *rtwdev, u8 path)
617 {
618 u32 base_addr = rtw8822c_get_path_write_addr(path);
619
620 rtw_write32(rtwdev, base_addr + 0x68, 0x0);
621 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4);
622 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0x1, 0x0);
623 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x1);
624 }
625
626 static void rtw8822c_dac_cal_backup_vec(struct rtw_dev *rtwdev,
627 u8 path, u8 vec, u32 w_addr, u32 r_addr)
628 {
629 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
630 u16 val;
631 u32 i;
632
633 if (WARN_ON(vec >= 2))
634 return;
635
636 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) {
637 rtw_write32_mask(rtwdev, w_addr, 0xf0000000, i);
638 val = (u16)rtw_read32_mask(rtwdev, r_addr, 0x7fc0000);
639 dm_info->dack_msbk[path][vec][i] = val;
640 }
641 }
642
643 static void rtw8822c_dac_cal_backup_path(struct rtw_dev *rtwdev, u8 path)
644 {
645 u32 w_off = 0x1c;
646 u32 r_off = 0x2c;
647 u32 w_addr, r_addr;
648
649 if (WARN_ON(path >= 2))
650 return;
651
652
653 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0;
654 r_addr = rtw8822c_get_path_read_addr(path) + 0x10;
655 rtw8822c_dac_cal_backup_vec(rtwdev, path, 0, w_addr, r_addr);
656
657
658 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off;
659 r_addr = rtw8822c_get_path_read_addr(path) + 0x10 + r_off;
660 rtw8822c_dac_cal_backup_vec(rtwdev, path, 1, w_addr, r_addr);
661 }
662
663 static void rtw8822c_dac_cal_backup_dck(struct rtw_dev *rtwdev)
664 {
665 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
666 u8 val;
667
668 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000);
669 dm_info->dack_dck[RF_PATH_A][0][0] = val;
670 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_1, 0xf);
671 dm_info->dack_dck[RF_PATH_A][0][1] = val;
672 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000);
673 dm_info->dack_dck[RF_PATH_A][1][0] = val;
674 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_1, 0xf);
675 dm_info->dack_dck[RF_PATH_A][1][1] = val;
676
677 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000);
678 dm_info->dack_dck[RF_PATH_B][0][0] = val;
679 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_1, 0xf);
680 dm_info->dack_dck[RF_PATH_B][1][0] = val;
681 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000);
682 dm_info->dack_dck[RF_PATH_B][0][1] = val;
683 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_1, 0xf);
684 dm_info->dack_dck[RF_PATH_B][1][1] = val;
685 }
686
687 static void rtw8822c_dac_cal_backup(struct rtw_dev *rtwdev)
688 {
689 u32 temp[3];
690
691 temp[0] = rtw_read32(rtwdev, 0x1860);
692 temp[1] = rtw_read32(rtwdev, 0x4160);
693 temp[2] = rtw_read32(rtwdev, 0x9b4);
694
695
696 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
697
698
699 rtw_write32_clr(rtwdev, 0x1830, BIT(30));
700 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c);
701 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_A);
702
703
704 rtw_write32_clr(rtwdev, 0x4130, BIT(30));
705 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c);
706 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_B);
707
708 rtw8822c_dac_cal_backup_dck(rtwdev);
709 rtw_write32_set(rtwdev, 0x1830, BIT(30));
710 rtw_write32_set(rtwdev, 0x4130, BIT(30));
711
712 rtw_write32(rtwdev, 0x1860, temp[0]);
713 rtw_write32(rtwdev, 0x4160, temp[1]);
714 rtw_write32(rtwdev, 0x9b4, temp[2]);
715 }
716
717 static void rtw8822c_dac_cal_restore_dck(struct rtw_dev *rtwdev)
718 {
719 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
720 u8 val;
721
722 rtw_write32_set(rtwdev, REG_DCKA_I_0, BIT(19));
723 val = dm_info->dack_dck[RF_PATH_A][0][0];
724 rtw_write32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000, val);
725 val = dm_info->dack_dck[RF_PATH_A][0][1];
726 rtw_write32_mask(rtwdev, REG_DCKA_I_1, 0xf, val);
727
728 rtw_write32_set(rtwdev, REG_DCKA_Q_0, BIT(19));
729 val = dm_info->dack_dck[RF_PATH_A][1][0];
730 rtw_write32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000, val);
731 val = dm_info->dack_dck[RF_PATH_A][1][1];
732 rtw_write32_mask(rtwdev, REG_DCKA_Q_1, 0xf, val);
733
734 rtw_write32_set(rtwdev, REG_DCKB_I_0, BIT(19));
735 val = dm_info->dack_dck[RF_PATH_B][0][0];
736 rtw_write32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000, val);
737 val = dm_info->dack_dck[RF_PATH_B][0][1];
738 rtw_write32_mask(rtwdev, REG_DCKB_I_1, 0xf, val);
739
740 rtw_write32_set(rtwdev, REG_DCKB_Q_0, BIT(19));
741 val = dm_info->dack_dck[RF_PATH_B][1][0];
742 rtw_write32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000, val);
743 val = dm_info->dack_dck[RF_PATH_B][1][1];
744 rtw_write32_mask(rtwdev, REG_DCKB_Q_1, 0xf, val);
745 }
746
747 static void rtw8822c_dac_cal_restore_prepare(struct rtw_dev *rtwdev)
748 {
749 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
750
751 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x0);
752 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x0);
753 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x0);
754 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x0);
755
756 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x0);
757 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c);
758 rtw_write32_mask(rtwdev, 0x18b4, BIT(0), 0x1);
759 rtw_write32_mask(rtwdev, 0x18d0, BIT(0), 0x1);
760
761 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x0);
762 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c);
763 rtw_write32_mask(rtwdev, 0x41b4, BIT(0), 0x1);
764 rtw_write32_mask(rtwdev, 0x41d0, BIT(0), 0x1);
765
766 rtw_write32_mask(rtwdev, 0x18b0, 0xf00, 0x0);
767 rtw_write32_mask(rtwdev, 0x18c0, BIT(14), 0x0);
768 rtw_write32_mask(rtwdev, 0x18cc, 0xf00, 0x0);
769 rtw_write32_mask(rtwdev, 0x18dc, BIT(14), 0x0);
770
771 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x0);
772 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x0);
773 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x1);
774 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x1);
775
776 rtw8822c_dac_cal_restore_dck(rtwdev);
777
778 rtw_write32_mask(rtwdev, 0x18c0, 0x38000, 0x7);
779 rtw_write32_mask(rtwdev, 0x18dc, 0x38000, 0x7);
780 rtw_write32_mask(rtwdev, 0x41c0, 0x38000, 0x7);
781 rtw_write32_mask(rtwdev, 0x41dc, 0x38000, 0x7);
782
783 rtw_write32_mask(rtwdev, 0x18b8, BIT(26) | BIT(25), 0x1);
784 rtw_write32_mask(rtwdev, 0x18d4, BIT(26) | BIT(25), 0x1);
785
786 rtw_write32_mask(rtwdev, 0x41b0, 0xf00, 0x0);
787 rtw_write32_mask(rtwdev, 0x41c0, BIT(14), 0x0);
788 rtw_write32_mask(rtwdev, 0x41cc, 0xf00, 0x0);
789 rtw_write32_mask(rtwdev, 0x41dc, BIT(14), 0x0);
790
791 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x0);
792 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x0);
793 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x1);
794 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x1);
795
796 rtw_write32_mask(rtwdev, 0x41b8, BIT(26) | BIT(25), 0x1);
797 rtw_write32_mask(rtwdev, 0x41d4, BIT(26) | BIT(25), 0x1);
798 }
799
800 static bool rtw8822c_dac_cal_restore_wait(struct rtw_dev *rtwdev,
801 u32 target_addr, u32 toggle_addr)
802 {
803 u32 cnt = 0;
804
805 do {
806 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x0);
807 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x2);
808
809 if (rtw_read32_mask(rtwdev, target_addr, 0xf) == 0x6)
810 return true;
811
812 } while (cnt++ < 100);
813
814 return false;
815 }
816
817 static bool rtw8822c_dac_cal_restore_path(struct rtw_dev *rtwdev, u8 path)
818 {
819 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
820 u32 w_off = 0x1c;
821 u32 r_off = 0x2c;
822 u32 w_i, r_i, w_q, r_q;
823 u32 value;
824 u32 i;
825
826 w_i = rtw8822c_get_path_write_addr(path) + 0xb0;
827 r_i = rtw8822c_get_path_read_addr(path) + 0x08;
828 w_q = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off;
829 r_q = rtw8822c_get_path_read_addr(path) + 0x08 + r_off;
830
831 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_i, w_i + 0x8))
832 return false;
833
834 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) {
835 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0);
836 value = dm_info->dack_msbk[path][0][i];
837 rtw_write32_mask(rtwdev, w_i + 0x4, 0xff8, value);
838 rtw_write32_mask(rtwdev, w_i, 0xf0000000, i);
839 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x1);
840 }
841
842 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0);
843
844 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_q, w_q + 0x8))
845 return false;
846
847 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) {
848 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0);
849 value = dm_info->dack_msbk[path][1][i];
850 rtw_write32_mask(rtwdev, w_q + 0x4, 0xff8, value);
851 rtw_write32_mask(rtwdev, w_q, 0xf0000000, i);
852 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x1);
853 }
854 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0);
855
856 rtw_write32_mask(rtwdev, w_i + 0x8, BIT(26) | BIT(25), 0x0);
857 rtw_write32_mask(rtwdev, w_q + 0x8, BIT(26) | BIT(25), 0x0);
858 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(0), 0x0);
859 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(0), 0x0);
860
861 return true;
862 }
863
864 static bool __rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev)
865 {
866 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_A))
867 return false;
868
869 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_B))
870 return false;
871
872 return true;
873 }
874
875 static bool rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev)
876 {
877 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
878 u32 temp[3];
879
880
881 if (dm_info->dack_msbk[RF_PATH_A][0][0] == 0 &&
882 dm_info->dack_msbk[RF_PATH_A][1][0] == 0 &&
883 dm_info->dack_msbk[RF_PATH_B][0][0] == 0 &&
884 dm_info->dack_msbk[RF_PATH_B][1][0] == 0)
885 return false;
886
887 temp[0] = rtw_read32(rtwdev, 0x1860);
888 temp[1] = rtw_read32(rtwdev, 0x4160);
889 temp[2] = rtw_read32(rtwdev, 0x9b4);
890
891 rtw8822c_dac_cal_restore_prepare(rtwdev);
892 if (!check_hw_ready(rtwdev, 0x2808, 0x7fff80, 0xffff) ||
893 !check_hw_ready(rtwdev, 0x2834, 0x7fff80, 0xffff) ||
894 !check_hw_ready(rtwdev, 0x4508, 0x7fff80, 0xffff) ||
895 !check_hw_ready(rtwdev, 0x4534, 0x7fff80, 0xffff))
896 return false;
897
898 if (!__rtw8822c_dac_cal_restore(rtwdev)) {
899 rtw_err(rtwdev, "failed to restore dack vectors\n");
900 return false;
901 }
902
903 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x1);
904 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1);
905 rtw_write32(rtwdev, 0x1860, temp[0]);
906 rtw_write32(rtwdev, 0x4160, temp[1]);
907 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x1);
908 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x1);
909 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x1);
910 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x1);
911 rtw_write32(rtwdev, 0x9b4, temp[2]);
912
913 return true;
914 }
915
916 static void rtw8822c_rf_dac_cal(struct rtw_dev *rtwdev)
917 {
918 struct rtw_backup_info backup_rf[DACK_RF_8822C * DACK_PATH_8822C];
919 struct rtw_backup_info backup[DACK_REG_8822C];
920 u32 ic = 0, qc = 0, i;
921 u32 i_a = 0x0, q_a = 0x0, i_b = 0x0, q_b = 0x0;
922 u32 ic_a = 0x0, qc_a = 0x0, ic_b = 0x0, qc_b = 0x0;
923 u32 adc_ic_a = 0x0, adc_qc_a = 0x0, adc_ic_b = 0x0, adc_qc_b = 0x0;
924
925 if (rtw8822c_dac_cal_restore(rtwdev))
926 return;
927
928
929
930 rtw8822c_dac_backup_reg(rtwdev, backup, backup_rf);
931
932 rtw8822c_dac_bb_setting(rtwdev);
933
934
935 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_A, &adc_ic_a, &adc_qc_a);
936 for (i = 0; i < 10; i++) {
937 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_A);
938 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_A, &ic, &qc);
939 ic_a = ic;
940 qc_a = qc;
941
942 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_A, adc_ic_a, adc_qc_a,
943 &ic, &qc, &i_a, &q_a);
944
945 if (ic < 5 && qc < 5)
946 break;
947 }
948 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_A);
949
950
951 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_B, &adc_ic_b, &adc_qc_b);
952 for (i = 0; i < 10; i++) {
953 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_B);
954 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_B, &ic, &qc);
955 ic_b = ic;
956 qc_b = qc;
957
958 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_B, adc_ic_b, adc_qc_b,
959 &ic, &qc, &i_b, &q_b);
960
961 if (ic < 5 && qc < 5)
962 break;
963 }
964 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_B);
965
966 rtw_write32(rtwdev, 0x1b00, 0x00000008);
967 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1);
968 rtw_write8(rtwdev, 0x1bcc, 0x0);
969 rtw_write32(rtwdev, 0x1b00, 0x0000000a);
970 rtw_write8(rtwdev, 0x1bcc, 0x0);
971
972 rtw8822c_dac_restore_reg(rtwdev, backup, backup_rf);
973
974
975 rtw8822c_dac_cal_backup(rtwdev);
976
977 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: ic=0x%x, qc=0x%x\n", ic_a, qc_a);
978 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: ic=0x%x, qc=0x%x\n", ic_b, qc_b);
979 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: i=0x%x, q=0x%x\n", i_a, q_a);
980 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: i=0x%x, q=0x%x\n", i_b, q_b);
981 }
982
983 static void rtw8822c_rf_x2_check(struct rtw_dev *rtwdev)
984 {
985 u8 x2k_busy;
986
987 mdelay(1);
988 x2k_busy = rtw_read_rf(rtwdev, RF_PATH_A, 0xb8, BIT(15));
989 if (x2k_busy == 1) {
990 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0xC4440);
991 rtw_write_rf(rtwdev, RF_PATH_A, 0xba, RFREG_MASK, 0x6840D);
992 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0x80440);
993 mdelay(1);
994 }
995 }
996
997 static void rtw8822c_rf_init(struct rtw_dev *rtwdev)
998 {
999 rtw8822c_rf_dac_cal(rtwdev);
1000 rtw8822c_rf_x2_check(rtwdev);
1001 }
1002
1003 static void rtw8822c_phy_set_param(struct rtw_dev *rtwdev)
1004 {
1005 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1006 struct rtw_hal *hal = &rtwdev->hal;
1007 u8 crystal_cap;
1008 u8 cck_gi_u_bnd_msb = 0;
1009 u8 cck_gi_u_bnd_lsb = 0;
1010 u8 cck_gi_l_bnd_msb = 0;
1011 u8 cck_gi_l_bnd_lsb = 0;
1012 bool is_tx2_path;
1013
1014
1015 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN,
1016 BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB);
1017 rtw_write8_set(rtwdev, REG_RF_CTRL,
1018 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
1019 rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN);
1020
1021
1022 rtw_write32_mask(rtwdev, REG_DIS_DPD, DIS_DPD_MASK, DIS_DPD_RATEALL);
1023
1024
1025 rtw8822c_header_file_init(rtwdev, true);
1026
1027 rtw_phy_load_tables(rtwdev);
1028
1029 crystal_cap = rtwdev->efuse.crystal_cap & 0x7f;
1030 rtw_write32_mask(rtwdev, REG_ANAPAR_XTAL_0, 0xfffc00,
1031 crystal_cap | (crystal_cap << 7));
1032
1033
1034 rtw8822c_header_file_init(rtwdev, false);
1035
1036 is_tx2_path = false;
1037 rtw8822c_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx,
1038 is_tx2_path);
1039 rtw_phy_init(rtwdev);
1040
1041 cck_gi_u_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc000);
1042 cck_gi_u_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1aa8, 0xf0000);
1043 cck_gi_l_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc0);
1044 cck_gi_l_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1a70, 0x0f000000);
1045
1046 dm_info->cck_gi_u_bnd = ((cck_gi_u_bnd_msb << 4) | (cck_gi_u_bnd_lsb));
1047 dm_info->cck_gi_l_bnd = ((cck_gi_l_bnd_msb << 4) | (cck_gi_l_bnd_lsb));
1048
1049 rtw8822c_rf_init(rtwdev);
1050 }
1051
1052 #define WLAN_TXQ_RPT_EN 0x1F
1053 #define WLAN_SLOT_TIME 0x09
1054 #define WLAN_PIFS_TIME 0x1C
1055 #define WLAN_SIFS_CCK_CONT_TX 0x0A
1056 #define WLAN_SIFS_OFDM_CONT_TX 0x0E
1057 #define WLAN_SIFS_CCK_TRX 0x0A
1058 #define WLAN_SIFS_OFDM_TRX 0x10
1059 #define WLAN_NAV_MAX 0xC8
1060 #define WLAN_RDG_NAV 0x05
1061 #define WLAN_TXOP_NAV 0x1B
1062 #define WLAN_CCK_RX_TSF 0x30
1063 #define WLAN_OFDM_RX_TSF 0x30
1064 #define WLAN_TBTT_PROHIBIT 0x04
1065 #define WLAN_TBTT_HOLD_TIME 0x064
1066 #define WLAN_DRV_EARLY_INT 0x04
1067 #define WLAN_BCN_CTRL_CLT0 0x10
1068 #define WLAN_BCN_DMA_TIME 0x02
1069 #define WLAN_BCN_MAX_ERR 0xFF
1070 #define WLAN_SIFS_CCK_DUR_TUNE 0x0A
1071 #define WLAN_SIFS_OFDM_DUR_TUNE 0x10
1072 #define WLAN_SIFS_CCK_CTX 0x0A
1073 #define WLAN_SIFS_CCK_IRX 0x0A
1074 #define WLAN_SIFS_OFDM_CTX 0x0E
1075 #define WLAN_SIFS_OFDM_IRX 0x0E
1076 #define WLAN_EIFS_DUR_TUNE 0x40
1077 #define WLAN_EDCA_VO_PARAM 0x002FA226
1078 #define WLAN_EDCA_VI_PARAM 0x005EA328
1079 #define WLAN_EDCA_BE_PARAM 0x005EA42B
1080 #define WLAN_EDCA_BK_PARAM 0x0000A44F
1081
1082 #define WLAN_RX_FILTER0 0xFFFFFFFF
1083 #define WLAN_RX_FILTER2 0xFFFF
1084 #define WLAN_RCR_CFG 0xE400220E
1085 #define WLAN_RXPKT_MAX_SZ 12288
1086 #define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9)
1087
1088 #define WLAN_AMPDU_MAX_TIME 0x70
1089 #define WLAN_RTS_LEN_TH 0xFF
1090 #define WLAN_RTS_TX_TIME_TH 0x08
1091 #define WLAN_MAX_AGG_PKT_LIMIT 0x20
1092 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x20
1093 #define WLAN_PRE_TXCNT_TIME_TH 0x1E0
1094 #define FAST_EDCA_VO_TH 0x06
1095 #define FAST_EDCA_VI_TH 0x06
1096 #define FAST_EDCA_BE_TH 0x06
1097 #define FAST_EDCA_BK_TH 0x06
1098 #define WLAN_BAR_RETRY_LIMIT 0x01
1099 #define WLAN_BAR_ACK_TYPE 0x05
1100 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08
1101 #define WLAN_RESP_TXRATE 0x84
1102 #define WLAN_ACK_TO 0x21
1103 #define WLAN_ACK_TO_CCK 0x6A
1104 #define WLAN_DATA_RATE_FB_CNT_1_4 0x01000000
1105 #define WLAN_DATA_RATE_FB_CNT_5_8 0x08070504
1106 #define WLAN_RTS_RATE_FB_CNT_5_8 0x08070504
1107 #define WLAN_DATA_RATE_FB_RATE0 0xFE01F010
1108 #define WLAN_DATA_RATE_FB_RATE0_H 0x40000000
1109 #define WLAN_RTS_RATE_FB_RATE1 0x003FF010
1110 #define WLAN_RTS_RATE_FB_RATE1_H 0x40000000
1111 #define WLAN_RTS_RATE_FB_RATE4 0x0600F010
1112 #define WLAN_RTS_RATE_FB_RATE4_H 0x400003E0
1113 #define WLAN_RTS_RATE_FB_RATE5 0x0600F015
1114 #define WLAN_RTS_RATE_FB_RATE5_H 0x000000E0
1115
1116 #define WLAN_TX_FUNC_CFG1 0x30
1117 #define WLAN_TX_FUNC_CFG2 0x30
1118 #define WLAN_MAC_OPT_NORM_FUNC1 0x98
1119 #define WLAN_MAC_OPT_LB_FUNC1 0x80
1120 #define WLAN_MAC_OPT_FUNC2 0x30810041
1121 #define WLAN_MAC_INT_MIG_CFG 0x33330000
1122
1123 #define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \
1124 (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \
1125 (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \
1126 (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX))
1127
1128 #define WLAN_SIFS_DUR_TUNE (WLAN_SIFS_CCK_DUR_TUNE | \
1129 (WLAN_SIFS_OFDM_DUR_TUNE << 8))
1130
1131 #define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\
1132 (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP))
1133
1134 #define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16))
1135 #define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8)
1136
1137 #define MAC_CLK_SPEED 80
1138 #define EFUSE_PCB_INFO_OFFSET 0xCA
1139
1140 static int rtw8822c_mac_init(struct rtw_dev *rtwdev)
1141 {
1142 u8 value8;
1143 u16 value16;
1144 u32 value32;
1145 u16 pre_txcnt;
1146
1147
1148 value8 = rtw_read8(rtwdev, REG_FWHW_TXQ_CTRL);
1149 value8 |= (BIT(7) & ~BIT(1) & ~BIT(2));
1150 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL, value8);
1151 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN);
1152
1153 rtw_write16(rtwdev, REG_SPEC_SIFS, WLAN_SIFS_DUR_TUNE);
1154 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG);
1155 rtw_write16(rtwdev, REG_RESP_SIFS_CCK,
1156 WLAN_SIFS_CCK_CTX | WLAN_SIFS_CCK_IRX << 8);
1157 rtw_write16(rtwdev, REG_RESP_SIFS_OFDM,
1158 WLAN_SIFS_OFDM_CTX | WLAN_SIFS_OFDM_IRX << 8);
1159
1160 rtw_write32(rtwdev, REG_DARFRC, WLAN_DATA_RATE_FB_CNT_1_4);
1161 rtw_write32(rtwdev, REG_DARFRCH, WLAN_DATA_RATE_FB_CNT_5_8);
1162 rtw_write32(rtwdev, REG_RARFRCH, WLAN_RTS_RATE_FB_CNT_5_8);
1163 rtw_write32(rtwdev, REG_ARFR0, WLAN_DATA_RATE_FB_RATE0);
1164 rtw_write32(rtwdev, REG_ARFRH0, WLAN_DATA_RATE_FB_RATE0_H);
1165 rtw_write32(rtwdev, REG_ARFR1_V1, WLAN_RTS_RATE_FB_RATE1);
1166 rtw_write32(rtwdev, REG_ARFRH1_V1, WLAN_RTS_RATE_FB_RATE1_H);
1167 rtw_write32(rtwdev, REG_ARFR4, WLAN_RTS_RATE_FB_RATE4);
1168 rtw_write32(rtwdev, REG_ARFRH4, WLAN_RTS_RATE_FB_RATE4_H);
1169 rtw_write32(rtwdev, REG_ARFR5, WLAN_RTS_RATE_FB_RATE5);
1170 rtw_write32(rtwdev, REG_ARFRH5, WLAN_RTS_RATE_FB_RATE5_H);
1171
1172 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME);
1173 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
1174 pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT;
1175 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF));
1176 rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8));
1177 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) |
1178 (WLAN_MAX_AGG_PKT_LIMIT << 16) |
1179 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24);
1180 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32);
1181 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2,
1182 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8);
1183 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH);
1184 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH);
1185 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH);
1186 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH);
1187
1188 rtw_write8_clr(rtwdev, REG_LIFETIME_EN, BIT_BA_PARSER_EN);
1189 rtw_write32_clr(rtwdev, REG_RRSR, BITS_RRSR_RSC);
1190
1191
1192 rtw_write32(rtwdev, REG_EDCA_VO_PARAM, WLAN_EDCA_VO_PARAM);
1193 rtw_write32(rtwdev, REG_EDCA_VI_PARAM, WLAN_EDCA_VI_PARAM);
1194 rtw_write32(rtwdev, REG_EDCA_BE_PARAM, WLAN_EDCA_BE_PARAM);
1195 rtw_write32(rtwdev, REG_EDCA_BK_PARAM, WLAN_EDCA_BK_PARAM);
1196 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME);
1197 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8);
1198 rtw_write8_set(rtwdev, REG_RD_CTRL + 1,
1199 (BIT_DIS_TXOP_CFE | BIT_DIS_LSIG_CFE |
1200 BIT_DIS_STBC_CFE) >> 8);
1201
1202
1203 rtw_write32_clr(rtwdev, REG_AFE_CTRL1, BIT_MAC_CLK_SEL);
1204 rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED);
1205 rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED);
1206
1207 rtw_write8_set(rtwdev, REG_MISC_CTRL,
1208 BIT_EN_FREE_CNT | BIT_DIS_SECOND_CCA);
1209 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0);
1210 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000);
1211 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME);
1212 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG);
1213 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG);
1214
1215 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
1216
1217 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME);
1218 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT);
1219 rtw_write8(rtwdev, REG_BCN_CTRL_CLINT0, WLAN_BCN_CTRL_CLT0);
1220 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
1221 rtw_write8(rtwdev, REG_BCN_MAX_ERR, WLAN_BCN_MAX_ERR);
1222
1223
1224 rtw_write8(rtwdev, REG_BBPSF_CTRL + 2, WLAN_RESP_TXRATE);
1225 rtw_write8(rtwdev, REG_ACKTO, WLAN_ACK_TO);
1226 rtw_write8(rtwdev, REG_ACKTO_CCK, WLAN_ACK_TO_CCK);
1227 rtw_write16(rtwdev, REG_EIFS, WLAN_EIFS_DUR_TUNE);
1228 rtw_write8(rtwdev, REG_NAV_CTRL + 2, WLAN_NAV_MAX);
1229 rtw_write8(rtwdev, REG_WMAC_TRXPTCL_CTL_H + 2, WLAN_BAR_ACK_TYPE);
1230 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0);
1231 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2);
1232 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG);
1233 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512);
1234 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2);
1235 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1);
1236 rtw_write32_set(rtwdev, REG_GENERAL_OPTION, BIT_DUMMY_FCS_READY_MASK_EN);
1237 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2);
1238 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION_1, WLAN_MAC_OPT_NORM_FUNC1);
1239
1240
1241 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL + 2) & 0xF00F;
1242 value16 |= (BIT_RXGCK_VHT_FIFOTHR(1) | BIT_RXGCK_HT_FIFOTHR(1) |
1243 BIT_RXGCK_OFDM_FIFOTHR(1) | BIT_RXGCK_CCK_FIFOTHR(1)) >> 16;
1244 rtw_write16(rtwdev, REG_RXPSF_CTRL + 2, value16);
1245 value16 = 0;
1246 value16 = BIT_SET_RXPSF_PKTLENTHR(value16, 1);
1247 value16 |= BIT_RXPSF_CTRLEN | BIT_RXPSF_VHTCHKEN | BIT_RXPSF_HTCHKEN
1248 | BIT_RXPSF_OFDMCHKEN | BIT_RXPSF_CCKCHKEN
1249 | BIT_RXPSF_OFDMRST;
1250 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16);
1251 rtw_write32(rtwdev, REG_RXPSF_TYPE_CTRL, 0xFFFFFFFF);
1252
1253 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL);
1254 value16 &= ~(BIT_RXPSF_MHCHKEN | BIT_RXPSF_CCKRST |
1255 BIT_RXPSF_CONT_ERRCHKEN);
1256 value16 = BIT_SET_RXPSF_ERRTHR(value16, 0x07);
1257 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16);
1258
1259
1260 rtw_write32(rtwdev, REG_INT_MIG, WLAN_MAC_INT_MIG_CFG);
1261
1262 return 0;
1263 }
1264
1265 static void rtw8822c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
1266 {
1267 #define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8))
1268 #define RF18_BAND_2G (0)
1269 #define RF18_BAND_5G (BIT(16) | BIT(8))
1270 #define RF18_CHANNEL_MASK (MASKBYTE0)
1271 #define RF18_RFSI_MASK (BIT(18) | BIT(17))
1272 #define RF18_RFSI_GE_CH80 (BIT(17))
1273 #define RF18_RFSI_GT_CH140 (BIT(18))
1274 #define RF18_BW_MASK (BIT(13) | BIT(12))
1275 #define RF18_BW_20M (BIT(13) | BIT(12))
1276 #define RF18_BW_40M (BIT(13))
1277 #define RF18_BW_80M (BIT(12))
1278
1279 u32 rf_reg18 = 0;
1280 u32 rf_rxbb = 0;
1281
1282 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
1283
1284 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK |
1285 RF18_BW_MASK);
1286
1287 rf_reg18 |= (channel <= 14 ? RF18_BAND_2G : RF18_BAND_5G);
1288 rf_reg18 |= (channel & RF18_CHANNEL_MASK);
1289 if (channel > 144)
1290 rf_reg18 |= RF18_RFSI_GT_CH140;
1291 else if (channel >= 80)
1292 rf_reg18 |= RF18_RFSI_GE_CH80;
1293
1294 switch (bw) {
1295 case RTW_CHANNEL_WIDTH_5:
1296 case RTW_CHANNEL_WIDTH_10:
1297 case RTW_CHANNEL_WIDTH_20:
1298 default:
1299 rf_reg18 |= RF18_BW_20M;
1300 rf_rxbb = 0x18;
1301 break;
1302 case RTW_CHANNEL_WIDTH_40:
1303
1304 rf_reg18 |= RF18_BW_40M;
1305 rf_rxbb = 0x10;
1306 break;
1307 case RTW_CHANNEL_WIDTH_80:
1308 rf_reg18 |= RF18_BW_80M;
1309 rf_rxbb = 0x8;
1310 break;
1311 }
1312
1313 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x01);
1314 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, 0x1f, 0x12);
1315 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, 0xfffff, rf_rxbb);
1316 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x00);
1317
1318 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x01);
1319 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWA, 0x1f, 0x12);
1320 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWD0, 0xfffff, rf_rxbb);
1321 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x00);
1322
1323 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_reg18);
1324 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_reg18);
1325 }
1326
1327 static void rtw8822c_toggle_igi(struct rtw_dev *rtwdev)
1328 {
1329 u32 igi;
1330
1331 igi = rtw_read32_mask(rtwdev, REG_RXIGI, 0x7f);
1332 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi - 2);
1333 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi - 2);
1334 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi);
1335 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi);
1336 }
1337
1338 static void rtw8822c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
1339 u8 primary_ch_idx)
1340 {
1341 if (channel <= 14) {
1342 rtw_write32_clr(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT);
1343 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8);
1344 rtw_write32_set(rtwdev, REG_TXF4, BIT(20));
1345 rtw_write32_clr(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN);
1346 rtw_write32_clr(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN);
1347 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0xF);
1348
1349 switch (bw) {
1350 case RTW_CHANNEL_WIDTH_20:
1351 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK,
1352 0x5);
1353 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK,
1354 0x5);
1355 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
1356 0x6);
1357 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
1358 0x6);
1359 break;
1360 case RTW_CHANNEL_WIDTH_40:
1361 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK,
1362 0x4);
1363 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK,
1364 0x4);
1365 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
1366 0x0);
1367 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
1368 0x0);
1369 break;
1370 }
1371 if (channel == 13 || channel == 14)
1372 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x969);
1373 else if (channel == 11 || channel == 12)
1374 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x96a);
1375 else
1376 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x9aa);
1377 if (channel == 14) {
1378 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x3da0);
1379 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD,
1380 0x4962c931);
1381 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x6aa3);
1382 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xaa7b);
1383 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xf3d7);
1384 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 0x0);
1385 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD,
1386 0xff012455);
1387 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 0xffff);
1388 } else {
1389 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x5284);
1390 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD,
1391 0x3e18fec8);
1392 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x0a88);
1393 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xacc4);
1394 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xc8b2);
1395 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD,
1396 0x00faf0de);
1397 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD,
1398 0x00122344);
1399 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD,
1400 0x0fffffff);
1401 }
1402 if (channel == 13)
1403 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3);
1404 else
1405 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x1);
1406 } else if (channel > 35) {
1407 rtw_write32_set(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN);
1408 rtw_write32_set(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN);
1409 rtw_write32_set(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT);
1410 rtw_write32_clr(rtwdev, REG_TXF4, BIT(20));
1411 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x0);
1412 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0x22);
1413 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3);
1414 if (channel >= 36 && channel <= 64) {
1415 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
1416 0x1);
1417 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
1418 0x1);
1419 } else if (channel >= 100 && channel <= 144) {
1420 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
1421 0x2);
1422 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
1423 0x2);
1424 } else if (channel >= 149) {
1425 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
1426 0x3);
1427 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
1428 0x3);
1429 }
1430
1431 if (channel >= 36 && channel <= 51)
1432 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x494);
1433 else if (channel >= 52 && channel <= 55)
1434 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x493);
1435 else if (channel >= 56 && channel <= 111)
1436 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x453);
1437 else if (channel >= 112 && channel <= 119)
1438 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x452);
1439 else if (channel >= 120 && channel <= 172)
1440 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x412);
1441 else if (channel >= 173 && channel <= 177)
1442 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x411);
1443 }
1444
1445 switch (bw) {
1446 case RTW_CHANNEL_WIDTH_20:
1447 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x19B);
1448 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
1449 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x0);
1450 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x7);
1451 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x6);
1452 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
1453 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
1454 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
1455 break;
1456 case RTW_CHANNEL_WIDTH_40:
1457 rtw_write32_mask(rtwdev, REG_CCKSB, BIT(4),
1458 (primary_ch_idx == 1 ? 1 : 0));
1459 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x5);
1460 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0);
1461 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00,
1462 (primary_ch_idx | (primary_ch_idx << 4)));
1463 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x1);
1464 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
1465 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1);
1466 break;
1467 case RTW_CHANNEL_WIDTH_80:
1468 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0xa);
1469 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0);
1470 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00,
1471 (primary_ch_idx | (primary_ch_idx << 4)));
1472 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x6);
1473 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1);
1474 break;
1475 case RTW_CHANNEL_WIDTH_5:
1476 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB);
1477 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
1478 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x1);
1479 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x4);
1480 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x4);
1481 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
1482 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
1483 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
1484 break;
1485 case RTW_CHANNEL_WIDTH_10:
1486 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB);
1487 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
1488 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x2);
1489 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x6);
1490 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x5);
1491 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
1492 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
1493 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
1494 break;
1495 }
1496 }
1497
1498 static void rtw8822c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
1499 u8 primary_chan_idx)
1500 {
1501 rtw8822c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
1502 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
1503 rtw8822c_set_channel_rf(rtwdev, channel, bw);
1504 rtw8822c_toggle_igi(rtwdev);
1505 }
1506
1507 static void rtw8822c_config_cck_rx_path(struct rtw_dev *rtwdev, u8 rx_path)
1508 {
1509 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) {
1510 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x0);
1511 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x0);
1512 } else if (rx_path == BB_PATH_AB) {
1513 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x1);
1514 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x1);
1515 }
1516
1517 if (rx_path == BB_PATH_A)
1518 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x0);
1519 else if (rx_path == BB_PATH_B)
1520 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x5);
1521 else if (rx_path == BB_PATH_AB)
1522 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x1);
1523 }
1524
1525 static void rtw8822c_config_ofdm_rx_path(struct rtw_dev *rtwdev, u8 rx_path)
1526 {
1527 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) {
1528 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x0);
1529 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x0);
1530 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x0);
1531 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x0);
1532 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x0);
1533 } else if (rx_path == BB_PATH_AB) {
1534 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x1);
1535 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x1);
1536 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x1);
1537 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x1);
1538 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x1);
1539 }
1540
1541 rtw_write32_mask(rtwdev, 0x824, 0x0f000000, rx_path);
1542 rtw_write32_mask(rtwdev, 0x824, 0x000f0000, rx_path);
1543 }
1544
1545 static void rtw8822c_config_rx_path(struct rtw_dev *rtwdev, u8 rx_path)
1546 {
1547 rtw8822c_config_cck_rx_path(rtwdev, rx_path);
1548 rtw8822c_config_ofdm_rx_path(rtwdev, rx_path);
1549 }
1550
1551 static void rtw8822c_config_cck_tx_path(struct rtw_dev *rtwdev, u8 tx_path,
1552 bool is_tx2_path)
1553 {
1554 if (tx_path == BB_PATH_A) {
1555 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8);
1556 } else if (tx_path == BB_PATH_B) {
1557 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x4);
1558 } else {
1559 if (is_tx2_path)
1560 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0xc);
1561 else
1562 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8);
1563 }
1564 }
1565
1566 static void rtw8822c_config_ofdm_tx_path(struct rtw_dev *rtwdev, u8 tx_path,
1567 bool is_tx2_path)
1568 {
1569 if (tx_path == BB_PATH_A) {
1570 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x11);
1571 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0);
1572 } else if (tx_path == BB_PATH_B) {
1573 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x12);
1574 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0);
1575 } else {
1576 if (is_tx2_path) {
1577 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x33);
1578 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0404);
1579 } else {
1580 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x31);
1581 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0400);
1582 }
1583 }
1584 }
1585
1586 static void rtw8822c_config_tx_path(struct rtw_dev *rtwdev, u8 tx_path,
1587 bool is_tx2_path)
1588 {
1589 rtw8822c_config_cck_tx_path(rtwdev, tx_path, is_tx2_path);
1590 rtw8822c_config_ofdm_tx_path(rtwdev, tx_path, is_tx2_path);
1591 }
1592
1593 static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path,
1594 u8 rx_path, bool is_tx2_path)
1595 {
1596 if ((tx_path | rx_path) & BB_PATH_A)
1597 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x33312);
1598 else
1599 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x11111);
1600 if ((tx_path | rx_path) & BB_PATH_B)
1601 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x33312);
1602 else
1603 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x11111);
1604
1605 rtw8822c_config_rx_path(rtwdev, rx_path);
1606 rtw8822c_config_tx_path(rtwdev, tx_path, is_tx2_path);
1607
1608 rtw8822c_toggle_igi(rtwdev);
1609 }
1610
1611 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status,
1612 struct rtw_rx_pkt_stat *pkt_stat)
1613 {
1614 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1615 u8 l_bnd, u_bnd;
1616 u8 gain_a, gain_b;
1617 s8 rx_power[RTW_RF_PATH_MAX];
1618 s8 min_rx_power = -120;
1619
1620 rx_power[RF_PATH_A] = GET_PHY_STAT_P0_PWDB_A(phy_status);
1621 rx_power[RF_PATH_B] = GET_PHY_STAT_P0_PWDB_B(phy_status);
1622 l_bnd = dm_info->cck_gi_l_bnd;
1623 u_bnd = dm_info->cck_gi_u_bnd;
1624 gain_a = GET_PHY_STAT_P0_GAIN_A(phy_status);
1625 gain_b = GET_PHY_STAT_P0_GAIN_B(phy_status);
1626 if (gain_a < l_bnd)
1627 rx_power[RF_PATH_A] += (l_bnd - gain_a) << 1;
1628 else if (gain_a > u_bnd)
1629 rx_power[RF_PATH_A] -= (gain_a - u_bnd) << 1;
1630 if (gain_b < l_bnd)
1631 rx_power[RF_PATH_B] += (l_bnd - gain_b) << 1;
1632 else if (gain_b > u_bnd)
1633 rx_power[RF_PATH_B] -= (gain_b - u_bnd) << 1;
1634
1635 rx_power[RF_PATH_A] -= 110;
1636 rx_power[RF_PATH_B] -= 110;
1637
1638 pkt_stat->rx_power[RF_PATH_A] = rx_power[RF_PATH_A];
1639 pkt_stat->rx_power[RF_PATH_B] = rx_power[RF_PATH_B];
1640
1641 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
1642 pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
1643 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],
1644 min_rx_power);
1645 }
1646
1647 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status,
1648 struct rtw_rx_pkt_stat *pkt_stat)
1649 {
1650 u8 rxsc, bw;
1651 s8 min_rx_power = -120;
1652
1653 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0)
1654 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status);
1655 else
1656 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status);
1657
1658 if (rxsc >= 9 && rxsc <= 12)
1659 bw = RTW_CHANNEL_WIDTH_40;
1660 else if (rxsc >= 13)
1661 bw = RTW_CHANNEL_WIDTH_80;
1662 else
1663 bw = RTW_CHANNEL_WIDTH_20;
1664
1665 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110;
1666 pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110;
1667 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2);
1668 pkt_stat->bw = bw;
1669 pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A],
1670 pkt_stat->rx_power[RF_PATH_B],
1671 min_rx_power);
1672 }
1673
1674 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
1675 struct rtw_rx_pkt_stat *pkt_stat)
1676 {
1677 u8 page;
1678
1679 page = *phy_status & 0xf;
1680
1681 switch (page) {
1682 case 0:
1683 query_phy_status_page0(rtwdev, phy_status, pkt_stat);
1684 break;
1685 case 1:
1686 query_phy_status_page1(rtwdev, phy_status, pkt_stat);
1687 break;
1688 default:
1689 rtw_warn(rtwdev, "unused phy status page (%d)\n", page);
1690 return;
1691 }
1692 }
1693
1694 static void rtw8822c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc,
1695 struct rtw_rx_pkt_stat *pkt_stat,
1696 struct ieee80211_rx_status *rx_status)
1697 {
1698 struct ieee80211_hdr *hdr;
1699 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz;
1700 u8 *phy_status = NULL;
1701
1702 memset(pkt_stat, 0, sizeof(*pkt_stat));
1703
1704 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc);
1705 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc);
1706 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc);
1707 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc);
1708 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc);
1709 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc);
1710 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc);
1711 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc);
1712 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc);
1713 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc);
1714 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc);
1715 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc);
1716
1717
1718 pkt_stat->drv_info_sz *= 8;
1719
1720
1721 if (pkt_stat->is_c2h)
1722 return;
1723
1724 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift +
1725 pkt_stat->drv_info_sz);
1726 if (pkt_stat->phy_status) {
1727 phy_status = rx_desc + desc_sz + pkt_stat->shift;
1728 query_phy_status(rtwdev, phy_status, pkt_stat);
1729 }
1730
1731 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status);
1732 }
1733
1734 static void
1735 rtw8822c_set_write_tx_power_ref(struct rtw_dev *rtwdev, u8 *tx_pwr_ref_cck,
1736 u8 *tx_pwr_ref_ofdm)
1737 {
1738 struct rtw_hal *hal = &rtwdev->hal;
1739 u32 txref_cck[2] = {0x18a0, 0x41a0};
1740 u32 txref_ofdm[2] = {0x18e8, 0x41e8};
1741 u8 path;
1742
1743 for (path = 0; path < hal->rf_path_num; path++) {
1744 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0);
1745 rtw_write32_mask(rtwdev, txref_cck[path], 0x7f0000,
1746 tx_pwr_ref_cck[path]);
1747 }
1748 for (path = 0; path < hal->rf_path_num; path++) {
1749 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0);
1750 rtw_write32_mask(rtwdev, txref_ofdm[path], 0x1fc00,
1751 tx_pwr_ref_ofdm[path]);
1752 }
1753 }
1754
1755 static void rtw8822c_set_tx_power_diff(struct rtw_dev *rtwdev, u8 rate,
1756 s8 *diff_idx)
1757 {
1758 u32 offset_txagc = 0x3a00;
1759 u8 rate_idx = rate & 0xfc;
1760 u8 pwr_idx[4];
1761 u32 phy_pwr_idx;
1762 int i;
1763
1764 for (i = 0; i < 4; i++)
1765 pwr_idx[i] = diff_idx[i] & 0x7f;
1766
1767 phy_pwr_idx = pwr_idx[0] |
1768 (pwr_idx[1] << 8) |
1769 (pwr_idx[2] << 16) |
1770 (pwr_idx[3] << 24);
1771
1772 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0x0);
1773 rtw_write32_mask(rtwdev, offset_txagc + rate_idx, MASKDWORD,
1774 phy_pwr_idx);
1775 }
1776
1777 static void rtw8822c_set_tx_power_index(struct rtw_dev *rtwdev)
1778 {
1779 struct rtw_hal *hal = &rtwdev->hal;
1780 u8 rs, rate, j;
1781 u8 pwr_ref_cck[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATE11M],
1782 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATE11M]};
1783 u8 pwr_ref_ofdm[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATEMCS7],
1784 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATEMCS7]};
1785 s8 diff_a, diff_b;
1786 u8 pwr_a, pwr_b;
1787 s8 diff_idx[4];
1788
1789 rtw8822c_set_write_tx_power_ref(rtwdev, pwr_ref_cck, pwr_ref_ofdm);
1790 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) {
1791 for (j = 0; j < rtw_rate_size[rs]; j++) {
1792 rate = rtw_rate_section[rs][j];
1793 pwr_a = hal->tx_pwr_tbl[RF_PATH_A][rate];
1794 pwr_b = hal->tx_pwr_tbl[RF_PATH_B][rate];
1795 if (rs == 0) {
1796 diff_a = (s8)pwr_a - (s8)pwr_ref_cck[0];
1797 diff_b = (s8)pwr_b - (s8)pwr_ref_cck[1];
1798 } else {
1799 diff_a = (s8)pwr_a - (s8)pwr_ref_ofdm[0];
1800 diff_b = (s8)pwr_b - (s8)pwr_ref_ofdm[1];
1801 }
1802 diff_idx[rate % 4] = min(diff_a, diff_b);
1803 if (rate % 4 == 3)
1804 rtw8822c_set_tx_power_diff(rtwdev, rate - 3,
1805 diff_idx);
1806 }
1807 }
1808 }
1809
1810 static void rtw8822c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)
1811 {
1812 u8 ldo_pwr;
1813
1814 ldo_pwr = rtw_read8(rtwdev, REG_ANAPARLDO_POW_MAC);
1815 ldo_pwr = enable ? ldo_pwr | BIT_LDOE25_PON : ldo_pwr & ~BIT_LDOE25_PON;
1816 rtw_write8(rtwdev, REG_ANAPARLDO_POW_MAC, ldo_pwr);
1817 }
1818
1819 static void rtw8822c_false_alarm_statistics(struct rtw_dev *rtwdev)
1820 {
1821 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1822 u32 cck_enable;
1823 u32 cck_fa_cnt;
1824 u32 crc32_cnt;
1825 u32 ofdm_fa_cnt;
1826 u32 ofdm_fa_cnt1, ofdm_fa_cnt2, ofdm_fa_cnt3, ofdm_fa_cnt4, ofdm_fa_cnt5;
1827 u16 parity_fail, rate_illegal, crc8_fail, mcs_fail, sb_search_fail,
1828 fast_fsync, crc8_fail_vhta, mcs_fail_vht;
1829
1830 cck_enable = rtw_read32(rtwdev, REG_ENCCK) & BIT_CCK_BLK_EN;
1831 cck_fa_cnt = rtw_read16(rtwdev, REG_CCK_FACNT);
1832
1833 ofdm_fa_cnt1 = rtw_read32(rtwdev, REG_OFDM_FACNT1);
1834 ofdm_fa_cnt2 = rtw_read32(rtwdev, REG_OFDM_FACNT2);
1835 ofdm_fa_cnt3 = rtw_read32(rtwdev, REG_OFDM_FACNT3);
1836 ofdm_fa_cnt4 = rtw_read32(rtwdev, REG_OFDM_FACNT4);
1837 ofdm_fa_cnt5 = rtw_read32(rtwdev, REG_OFDM_FACNT5);
1838
1839 parity_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt1);
1840 rate_illegal = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt2);
1841 crc8_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt2);
1842 crc8_fail_vhta = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt3);
1843 mcs_fail = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt4);
1844 mcs_fail_vht = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt4);
1845 fast_fsync = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt5);
1846 sb_search_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt5);
1847
1848 ofdm_fa_cnt = parity_fail + rate_illegal + crc8_fail + crc8_fail_vhta +
1849 mcs_fail + mcs_fail_vht + fast_fsync + sb_search_fail;
1850
1851 dm_info->cck_fa_cnt = cck_fa_cnt;
1852 dm_info->ofdm_fa_cnt = ofdm_fa_cnt;
1853 dm_info->total_fa_cnt = ofdm_fa_cnt;
1854 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0;
1855
1856 crc32_cnt = rtw_read32(rtwdev, 0x2c04);
1857 dm_info->cck_ok_cnt = crc32_cnt & 0xffff;
1858 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
1859 crc32_cnt = rtw_read32(rtwdev, 0x2c14);
1860 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff;
1861 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
1862 crc32_cnt = rtw_read32(rtwdev, 0x2c10);
1863 dm_info->ht_ok_cnt = crc32_cnt & 0xffff;
1864 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
1865 crc32_cnt = rtw_read32(rtwdev, 0x2c0c);
1866 dm_info->vht_ok_cnt = crc32_cnt & 0xffff;
1867 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
1868
1869 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 0);
1870 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 2);
1871 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 0);
1872 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 2);
1873
1874
1875 rtw_write32_clr(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN);
1876 rtw_write32_set(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST);
1877 rtw_write32_clr(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST);
1878 rtw_write32_set(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN);
1879 }
1880
1881 static void rtw8822c_do_iqk(struct rtw_dev *rtwdev)
1882 {
1883 struct rtw_iqk_para para = {0};
1884 u8 iqk_chk;
1885 int counter;
1886
1887 para.clear = 1;
1888 rtw_fw_do_iqk(rtwdev, ¶);
1889
1890 for (counter = 0; counter < 300; counter++) {
1891 iqk_chk = rtw_read8(rtwdev, REG_RPT_CIP);
1892 if (iqk_chk == 0xaa)
1893 break;
1894 msleep(20);
1895 }
1896 rtw_write8(rtwdev, REG_IQKSTAT, 0x0);
1897
1898 rtw_dbg(rtwdev, RTW_DBG_RFK, "iqk counter=%d\n", counter);
1899 }
1900
1901
1902 static void rtw8822c_coex_cfg_init(struct rtw_dev *rtwdev)
1903 {
1904
1905 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
1906
1907
1908
1909 rtw_write8_set(rtwdev, REG_BT_TDMA_TIME, 0x05);
1910
1911
1912 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1);
1913
1914
1915 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);
1916 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_AOD_GPIO3);
1917
1918
1919 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN);
1920
1921 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN);
1922
1923 rtw_write8_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY);
1924
1925 rtw_write8_clr(rtwdev, REG_DUMMY_PAGE4_V1, BIT_BTCCA_CTRL);
1926
1927
1928 rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, 0x40000);
1929 }
1930
1931 static void rtw8822c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
1932 {
1933 struct rtw_coex *coex = &rtwdev->coex;
1934 struct rtw_coex_stat *coex_stat = &coex->stat;
1935 struct rtw_efuse *efuse = &rtwdev->efuse;
1936 u32 rf_0x1;
1937
1938 if (coex_stat->gnt_workaround_state == coex_stat->wl_coex_mode)
1939 return;
1940
1941 coex_stat->gnt_workaround_state = coex_stat->wl_coex_mode;
1942
1943 if ((coex_stat->kt_ver == 0 && coex->under_5g) || coex->freerun)
1944 rf_0x1 = 0x40021;
1945 else
1946 rf_0x1 = 0x40000;
1947
1948
1949 if (efuse->share_ant)
1950 rf_0x1 |= BIT(13);
1951
1952 rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, rf_0x1);
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965 rtw_write8_mask(rtwdev, 0x1c32, BIT(6), 1);
1966 rtw_write8_mask(rtwdev, 0x1c39, BIT(4), 0);
1967 rtw_write8_mask(rtwdev, 0x1c3b, BIT(4), 1);
1968 rtw_write8_mask(rtwdev, 0x4160, BIT(3), 1);
1969
1970
1971
1972
1973 if (coex_stat->wl_coex_mode == COEX_WLINK_5G ||
1974 coex->under_5g || !efuse->share_ant) {
1975 if (coex_stat->kt_ver >= 3) {
1976 rtw_write8_mask(rtwdev, 0x1860, BIT(3), 0);
1977 rtw_write8_mask(rtwdev, 0x1ca7, BIT(3), 1);
1978 } else {
1979 rtw_write8_mask(rtwdev, 0x1860, BIT(3), 1);
1980 }
1981 } else {
1982
1983 rtw_write8_mask(rtwdev, 0x1860, BIT(3), 0);
1984 if (coex_stat->kt_ver >= 3)
1985 rtw_write8_mask(rtwdev, 0x1ca7, BIT(3), 0);
1986 }
1987 }
1988
1989 static void rtw8822c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev)
1990 {
1991 rtw_write8_mask(rtwdev, 0x66, BIT(4), 0);
1992 rtw_write8_mask(rtwdev, 0x67, BIT(0), 0);
1993 rtw_write8_mask(rtwdev, 0x42, BIT(3), 0);
1994 rtw_write8_mask(rtwdev, 0x65, BIT(7), 0);
1995 rtw_write8_mask(rtwdev, 0x73, BIT(3), 0);
1996 }
1997
1998 static void rtw8822c_coex_cfg_rfe_type(struct rtw_dev *rtwdev)
1999 {
2000 struct rtw_coex *coex = &rtwdev->coex;
2001 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
2002 struct rtw_efuse *efuse = &rtwdev->efuse;
2003
2004 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option;
2005 coex_rfe->ant_switch_polarity = 0;
2006 coex_rfe->ant_switch_exist = false;
2007 coex_rfe->ant_switch_with_bt = false;
2008 coex_rfe->ant_switch_diversity = false;
2009
2010 if (efuse->share_ant)
2011 coex_rfe->wlg_at_btg = true;
2012 else
2013 coex_rfe->wlg_at_btg = false;
2014
2015
2016 rtw_coex_write_indirect_reg(rtwdev, 0x38, BIT_LTE_COEX_EN, 0x0);
2017 rtw_coex_write_indirect_reg(rtwdev, 0xa0, MASKLWORD, 0xffff);
2018 rtw_coex_write_indirect_reg(rtwdev, 0xa4, MASKLWORD, 0xffff);
2019 }
2020
2021 static void rtw8822c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
2022 {
2023 struct rtw_coex *coex = &rtwdev->coex;
2024 struct rtw_coex_dm *coex_dm = &coex->dm;
2025
2026 if (wl_pwr == coex_dm->cur_wl_pwr_lvl)
2027 return;
2028
2029 coex_dm->cur_wl_pwr_lvl = wl_pwr;
2030 }
2031
2032 static void rtw8822c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
2033 {
2034 struct rtw_coex *coex = &rtwdev->coex;
2035 struct rtw_coex_dm *coex_dm = &coex->dm;
2036
2037 if (low_gain == coex_dm->cur_wl_rx_low_gain_en)
2038 return;
2039
2040 coex_dm->cur_wl_rx_low_gain_en = low_gain;
2041
2042 if (coex_dm->cur_wl_rx_low_gain_en) {
2043
2044 rtw_write_rf(rtwdev, RF_PATH_A, 0xde, 0xfffff, 0x22);
2045 rtw_write_rf(rtwdev, RF_PATH_A, 0x1d, 0xfffff, 0x36);
2046 rtw_write_rf(rtwdev, RF_PATH_B, 0xde, 0xfffff, 0x22);
2047 rtw_write_rf(rtwdev, RF_PATH_B, 0x1d, 0xfffff, 0x36);
2048 } else {
2049
2050 rtw_write_rf(rtwdev, RF_PATH_A, 0xde, 0xfffff, 0x20);
2051 rtw_write_rf(rtwdev, RF_PATH_A, 0x1d, 0xfffff, 0x0);
2052 rtw_write_rf(rtwdev, RF_PATH_B, 0x1d, 0xfffff, 0x0);
2053 }
2054 }
2055
2056 struct dpk_cfg_pair {
2057 u32 addr;
2058 u32 bitmask;
2059 u32 data;
2060 };
2061
2062 void rtw8822c_parse_tbl_dpk(struct rtw_dev *rtwdev,
2063 const struct rtw_table *tbl)
2064 {
2065 const struct dpk_cfg_pair *p = tbl->data;
2066 const struct dpk_cfg_pair *end = p + tbl->size / 3;
2067
2068 BUILD_BUG_ON(sizeof(struct dpk_cfg_pair) != sizeof(u32) * 3);
2069
2070 for (; p < end; p++)
2071 rtw_write32_mask(rtwdev, p->addr, p->bitmask, p->data);
2072 }
2073
2074 static void rtw8822c_dpk_set_gnt_wl(struct rtw_dev *rtwdev, bool is_before_k)
2075 {
2076 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2077
2078 if (is_before_k) {
2079 dpk_info->gnt_control = rtw_read32(rtwdev, 0x70);
2080 dpk_info->gnt_value = rtw_coex_read_indirect_reg(rtwdev, 0x38);
2081 rtw_write32_mask(rtwdev, 0x70, BIT(26), 0x1);
2082 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKBYTE1, 0x77);
2083 } else {
2084 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKDWORD,
2085 dpk_info->gnt_value);
2086 rtw_write32(rtwdev, 0x70, dpk_info->gnt_control);
2087 }
2088 }
2089
2090 static void
2091 rtw8822c_dpk_restore_registers(struct rtw_dev *rtwdev, u32 reg_num,
2092 struct rtw_backup_info *bckp)
2093 {
2094 rtw_restore_reg(rtwdev, bckp, reg_num);
2095 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
2096 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0x4);
2097 }
2098
2099 static void
2100 rtw8822c_dpk_backup_registers(struct rtw_dev *rtwdev, u32 *reg,
2101 u32 reg_num, struct rtw_backup_info *bckp)
2102 {
2103 u32 i;
2104
2105 for (i = 0; i < reg_num; i++) {
2106 bckp[i].len = 4;
2107 bckp[i].reg = reg[i];
2108 bckp[i].val = rtw_read32(rtwdev, reg[i]);
2109 }
2110 }
2111
2112 static void rtw8822c_dpk_backup_rf_registers(struct rtw_dev *rtwdev,
2113 u32 *rf_reg,
2114 u32 rf_reg_bak[][2])
2115 {
2116 u32 i;
2117
2118 for (i = 0; i < DPK_RF_REG_NUM; i++) {
2119 rf_reg_bak[i][RF_PATH_A] = rtw_read_rf(rtwdev, RF_PATH_A,
2120 rf_reg[i], RFREG_MASK);
2121 rf_reg_bak[i][RF_PATH_B] = rtw_read_rf(rtwdev, RF_PATH_B,
2122 rf_reg[i], RFREG_MASK);
2123 }
2124 }
2125
2126 static void rtw8822c_dpk_reload_rf_registers(struct rtw_dev *rtwdev,
2127 u32 *rf_reg,
2128 u32 rf_reg_bak[][2])
2129 {
2130 u32 i;
2131
2132 for (i = 0; i < DPK_RF_REG_NUM; i++) {
2133 rtw_write_rf(rtwdev, RF_PATH_A, rf_reg[i], RFREG_MASK,
2134 rf_reg_bak[i][RF_PATH_A]);
2135 rtw_write_rf(rtwdev, RF_PATH_B, rf_reg[i], RFREG_MASK,
2136 rf_reg_bak[i][RF_PATH_B]);
2137 }
2138 }
2139
2140 static void rtw8822c_dpk_information(struct rtw_dev *rtwdev)
2141 {
2142 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2143 u32 reg;
2144 u8 band_shift;
2145
2146 reg = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
2147
2148 band_shift = FIELD_GET(BIT(16), reg);
2149 dpk_info->dpk_band = 1 << band_shift;
2150 dpk_info->dpk_ch = FIELD_GET(0xff, reg);
2151 dpk_info->dpk_bw = FIELD_GET(0x3000, reg);
2152 }
2153
2154 static void rtw8822c_dpk_rxbb_dc_cal(struct rtw_dev *rtwdev, u8 path)
2155 {
2156 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800);
2157 udelay(5);
2158 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84801);
2159 usleep_range(600, 610);
2160 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800);
2161 }
2162
2163 static u8 rtw8822c_dpk_dc_corr_check(struct rtw_dev *rtwdev, u8 path)
2164 {
2165 u16 dc_i, dc_q;
2166 u8 corr_val, corr_idx;
2167
2168 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000900f0);
2169 dc_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16));
2170 dc_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(11, 0));
2171
2172 if (dc_i & BIT(11))
2173 dc_i = 0x1000 - dc_i;
2174 if (dc_q & BIT(11))
2175 dc_q = 0x1000 - dc_q;
2176
2177 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0);
2178 corr_idx = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(7, 0));
2179 corr_val = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(15, 8));
2180
2181 if (dc_i > 200 || dc_q > 200 || corr_idx < 40 || corr_idx > 65)
2182 return 1;
2183 else
2184 return 0;
2185
2186 }
2187
2188 static void rtw8822c_dpk_tx_pause(struct rtw_dev *rtwdev)
2189 {
2190 u8 reg_a, reg_b;
2191 u16 count = 0;
2192
2193 rtw_write8(rtwdev, 0x522, 0xff);
2194 rtw_write32_mask(rtwdev, 0x1e70, 0xf, 0x2);
2195
2196 do {
2197 reg_a = (u8)rtw_read_rf(rtwdev, RF_PATH_A, 0x00, 0xf0000);
2198 reg_b = (u8)rtw_read_rf(rtwdev, RF_PATH_B, 0x00, 0xf0000);
2199 udelay(2);
2200 count++;
2201 } while ((reg_a == 2 || reg_b == 2) && count < 2500);
2202 }
2203
2204 static void rtw8822c_dpk_mac_bb_setting(struct rtw_dev *rtwdev)
2205 {
2206 rtw8822c_dpk_tx_pause(rtwdev);
2207 rtw_load_table(rtwdev, &rtw8822c_dpk_mac_bb_tbl);
2208 }
2209
2210 static void rtw8822c_dpk_afe_setting(struct rtw_dev *rtwdev, bool is_do_dpk)
2211 {
2212 if (is_do_dpk)
2213 rtw_load_table(rtwdev, &rtw8822c_dpk_afe_is_dpk_tbl);
2214 else
2215 rtw_load_table(rtwdev, &rtw8822c_dpk_afe_no_dpk_tbl);
2216 }
2217
2218 static void rtw8822c_dpk_pre_setting(struct rtw_dev *rtwdev)
2219 {
2220 u8 path;
2221
2222 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
2223 rtw_write_rf(rtwdev, path, RF_RXAGC_OFFSET, RFREG_MASK, 0x0);
2224 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1));
2225 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G)
2226 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f100000);
2227 else
2228 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f0d0000);
2229 rtw_write32_mask(rtwdev, REG_DPD_LUT0, BIT_GLOSS_DB, 0x4);
2230 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x3);
2231 }
2232 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
2233 rtw_write32(rtwdev, REG_DPD_CTL11, 0x3b23170b);
2234 rtw_write32(rtwdev, REG_DPD_CTL12, 0x775f5347);
2235 }
2236
2237 static u32 rtw8822c_dpk_rf_setting(struct rtw_dev *rtwdev, u8 path)
2238 {
2239 u32 ori_txbb;
2240
2241 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x50017);
2242 ori_txbb = rtw_read_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK);
2243
2244 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1);
2245 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_PWR_TRIM, 0x1);
2246 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_TX_OFFSET_VAL, 0x0);
2247 rtw_write_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK, ori_txbb);
2248
2249 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G) {
2250 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_LB_ATT, 0x1);
2251 rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x0);
2252 } else {
2253 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x0);
2254 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_ATT, 0x6);
2255 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_SW, 0x1);
2256 rtw_write_rf(rtwdev, path, RF_RXA_MIX_GAIN, BIT_RXA_MIX_GAIN, 0);
2257 }
2258
2259 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf);
2260 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1);
2261 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0);
2262
2263 if (rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80)
2264 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x2);
2265 else
2266 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x1);
2267
2268 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT(1), 0x1);
2269
2270 usleep_range(100, 110);
2271
2272 return ori_txbb & 0x1f;
2273 }
2274
2275 static u16 rtw8822c_dpk_get_cmd(struct rtw_dev *rtwdev, u8 action, u8 path)
2276 {
2277 u16 cmd;
2278 u8 bw = rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80 ? 2 : 0;
2279
2280 switch (action) {
2281 case RTW_DPK_GAIN_LOSS:
2282 cmd = 0x14 + path;
2283 break;
2284 case RTW_DPK_DO_DPK:
2285 cmd = 0x16 + path + bw;
2286 break;
2287 case RTW_DPK_DPK_ON:
2288 cmd = 0x1a + path;
2289 break;
2290 case RTW_DPK_DAGC:
2291 cmd = 0x1c + path + bw;
2292 break;
2293 default:
2294 return 0;
2295 }
2296
2297 return (cmd << 8) | 0x48;
2298 }
2299
2300 static u8 rtw8822c_dpk_one_shot(struct rtw_dev *rtwdev, u8 path, u8 action)
2301 {
2302 u16 dpk_cmd;
2303 u8 result = 0;
2304
2305 rtw8822c_dpk_set_gnt_wl(rtwdev, true);
2306
2307 if (action == RTW_DPK_CAL_PWR) {
2308 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x1);
2309 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x0);
2310 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0);
2311 msleep(10);
2312 if (!check_hw_ready(rtwdev, REG_STAT_RPT, BIT(31), 0x1)) {
2313 result = 1;
2314 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n");
2315 }
2316 } else {
2317 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
2318 0x8 | (path << 1));
2319 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9);
2320
2321 dpk_cmd = rtw8822c_dpk_get_cmd(rtwdev, action, path);
2322 rtw_write32(rtwdev, REG_NCTL0, dpk_cmd);
2323 rtw_write32(rtwdev, REG_NCTL0, dpk_cmd + 1);
2324 msleep(10);
2325 if (!check_hw_ready(rtwdev, 0x2d9c, 0xff, 0x55)) {
2326 result = 1;
2327 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n");
2328 }
2329 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
2330 0x8 | (path << 1));
2331 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0);
2332 }
2333
2334 rtw8822c_dpk_set_gnt_wl(rtwdev, false);
2335
2336 rtw_write8(rtwdev, 0x1b10, 0x0);
2337
2338 return result;
2339 }
2340
2341 static u16 rtw8822c_dpk_dgain_read(struct rtw_dev *rtwdev, u8 path)
2342 {
2343 u16 dgain;
2344
2345 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
2346 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, 0x00ff0000, 0x0);
2347
2348 dgain = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16));
2349
2350 return dgain;
2351 }
2352
2353 static u8 rtw8822c_dpk_thermal_read(struct rtw_dev *rtwdev, u8 path)
2354 {
2355 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1);
2356 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x0);
2357 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1);
2358 udelay(15);
2359
2360 return (u8)rtw_read_rf(rtwdev, path, RF_T_METER, 0x0007e);
2361 }
2362
2363 static u32 rtw8822c_dpk_pas_read(struct rtw_dev *rtwdev, u8 path)
2364 {
2365 u32 i_val, q_val;
2366
2367 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1));
2368 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0);
2369 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060001);
2370 rtw_write32(rtwdev, 0x1b4c, 0x00000000);
2371 rtw_write32(rtwdev, 0x1b4c, 0x00080000);
2372
2373 q_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD);
2374 i_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD);
2375
2376 if (i_val & BIT(15))
2377 i_val = 0x10000 - i_val;
2378 if (q_val & BIT(15))
2379 q_val = 0x10000 - q_val;
2380
2381 rtw_write32(rtwdev, 0x1b4c, 0x00000000);
2382
2383 return i_val * i_val + q_val * q_val;
2384 }
2385
2386 static u32 rtw8822c_psd_log2base(u32 val)
2387 {
2388 u32 tmp, val_integerd_b, tindex;
2389 u32 result, val_fractiond_b;
2390 u32 table_fraction[21] = {0, 432, 332, 274, 232, 200, 174,
2391 151, 132, 115, 100, 86, 74, 62, 51,
2392 42, 32, 23, 15, 7, 0};
2393
2394 if (val == 0)
2395 return 0;
2396
2397 val_integerd_b = __fls(val) + 1;
2398
2399 tmp = (val * 100) / (1 << val_integerd_b);
2400 tindex = tmp / 5;
2401
2402 if (tindex >= ARRAY_SIZE(table_fraction))
2403 tindex = ARRAY_SIZE(table_fraction) - 1;
2404
2405 val_fractiond_b = table_fraction[tindex];
2406
2407 result = val_integerd_b * 100 - val_fractiond_b;
2408
2409 return result;
2410 }
2411
2412 static u8 rtw8822c_dpk_gainloss_result(struct rtw_dev *rtwdev, u8 path)
2413 {
2414 u8 result;
2415
2416 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
2417 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x1);
2418 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060000);
2419
2420 result = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, 0x000000f0);
2421
2422 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0);
2423
2424 return result;
2425 }
2426
2427 static u8 rtw8822c_dpk_agc_gain_chk(struct rtw_dev *rtwdev, u8 path,
2428 u8 limited_pga)
2429 {
2430 u8 result = 0;
2431 u16 dgain;
2432
2433 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC);
2434 dgain = rtw8822c_dpk_dgain_read(rtwdev, path);
2435
2436 if (dgain > 1535 && !limited_pga)
2437 return RTW_DPK_GAIN_LESS;
2438 else if (dgain < 768 && !limited_pga)
2439 return RTW_DPK_GAIN_LARGE;
2440 else
2441 return result;
2442 }
2443
2444 static u8 rtw8822c_dpk_agc_loss_chk(struct rtw_dev *rtwdev, u8 path)
2445 {
2446 u32 loss, loss_db;
2447
2448 loss = rtw8822c_dpk_pas_read(rtwdev, path);
2449 if (loss < 0x4000000)
2450 return RTW_DPK_GL_LESS;
2451 loss_db = 3 * rtw8822c_psd_log2base(loss >> 13) - 3870;
2452
2453 if (loss_db > 1000)
2454 return RTW_DPK_GL_LARGE;
2455 else if (loss_db < 250)
2456 return RTW_DPK_GL_LESS;
2457 else
2458 return RTW_DPK_AGC_OUT;
2459 }
2460
2461 struct rtw8822c_dpk_data {
2462 u8 txbb;
2463 u8 pga;
2464 u8 limited_pga;
2465 u8 agc_cnt;
2466 bool loss_only;
2467 bool gain_only;
2468 u8 path;
2469 };
2470
2471 static u8 rtw8822c_gain_check_state(struct rtw_dev *rtwdev,
2472 struct rtw8822c_dpk_data *data)
2473 {
2474 u8 state;
2475
2476 data->txbb = (u8)rtw_read_rf(rtwdev, data->path, RF_TX_GAIN,
2477 BIT_GAIN_TXBB);
2478 data->pga = (u8)rtw_read_rf(rtwdev, data->path, RF_MODE_TRXAGC,
2479 BIT_RXAGC);
2480
2481 if (data->loss_only) {
2482 state = RTW_DPK_LOSS_CHECK;
2483 goto check_end;
2484 }
2485
2486 state = rtw8822c_dpk_agc_gain_chk(rtwdev, data->path,
2487 data->limited_pga);
2488 if (state == RTW_DPK_GAIN_CHECK && data->gain_only)
2489 state = RTW_DPK_AGC_OUT;
2490 else if (state == RTW_DPK_GAIN_CHECK)
2491 state = RTW_DPK_LOSS_CHECK;
2492
2493 check_end:
2494 data->agc_cnt++;
2495 if (data->agc_cnt >= 6)
2496 state = RTW_DPK_AGC_OUT;
2497
2498 return state;
2499 }
2500
2501 static u8 rtw8822c_gain_large_state(struct rtw_dev *rtwdev,
2502 struct rtw8822c_dpk_data *data)
2503 {
2504 u8 pga = data->pga;
2505
2506 if (pga > 0xe)
2507 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc);
2508 else if (pga > 0xb && pga < 0xf)
2509 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0);
2510 else if (pga < 0xc)
2511 data->limited_pga = 1;
2512
2513 return RTW_DPK_GAIN_CHECK;
2514 }
2515
2516 static u8 rtw8822c_gain_less_state(struct rtw_dev *rtwdev,
2517 struct rtw8822c_dpk_data *data)
2518 {
2519 u8 pga = data->pga;
2520
2521 if (pga < 0xc)
2522 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc);
2523 else if (pga > 0xb && pga < 0xf)
2524 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf);
2525 else if (pga > 0xe)
2526 data->limited_pga = 1;
2527
2528 return RTW_DPK_GAIN_CHECK;
2529 }
2530
2531 static u8 rtw8822c_gl_state(struct rtw_dev *rtwdev,
2532 struct rtw8822c_dpk_data *data, u8 is_large)
2533 {
2534 u8 txbb_bound[] = {0x1f, 0};
2535
2536 if (data->txbb == txbb_bound[is_large])
2537 return RTW_DPK_AGC_OUT;
2538
2539 if (is_large == 1)
2540 data->txbb -= 2;
2541 else
2542 data->txbb += 3;
2543
2544 rtw_write_rf(rtwdev, data->path, RF_TX_GAIN, BIT_GAIN_TXBB, data->txbb);
2545 data->limited_pga = 0;
2546
2547 return RTW_DPK_GAIN_CHECK;
2548 }
2549
2550 static u8 rtw8822c_gl_large_state(struct rtw_dev *rtwdev,
2551 struct rtw8822c_dpk_data *data)
2552 {
2553 return rtw8822c_gl_state(rtwdev, data, 1);
2554 }
2555
2556 static u8 rtw8822c_gl_less_state(struct rtw_dev *rtwdev,
2557 struct rtw8822c_dpk_data *data)
2558 {
2559 return rtw8822c_gl_state(rtwdev, data, 0);
2560 }
2561
2562 static u8 rtw8822c_loss_check_state(struct rtw_dev *rtwdev,
2563 struct rtw8822c_dpk_data *data)
2564 {
2565 u8 path = data->path;
2566 u8 state;
2567
2568 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_GAIN_LOSS);
2569 state = rtw8822c_dpk_agc_loss_chk(rtwdev, path);
2570
2571 return state;
2572 }
2573
2574 static u8 (*dpk_state[])(struct rtw_dev *rtwdev,
2575 struct rtw8822c_dpk_data *data) = {
2576 rtw8822c_gain_check_state, rtw8822c_gain_large_state,
2577 rtw8822c_gain_less_state, rtw8822c_gl_large_state,
2578 rtw8822c_gl_less_state, rtw8822c_loss_check_state };
2579
2580 static u8 rtw8822c_dpk_pas_agc(struct rtw_dev *rtwdev, u8 path,
2581 bool gain_only, bool loss_only)
2582 {
2583 struct rtw8822c_dpk_data data = {0};
2584 u8 (*func)(struct rtw_dev *rtwdev, struct rtw8822c_dpk_data *data);
2585 u8 state = RTW_DPK_GAIN_CHECK;
2586
2587 data.loss_only = loss_only;
2588 data.gain_only = gain_only;
2589 data.path = path;
2590
2591 for (;;) {
2592 func = dpk_state[state];
2593 state = func(rtwdev, &data);
2594 if (state == RTW_DPK_AGC_OUT)
2595 break;
2596 }
2597
2598 return data.txbb;
2599 }
2600
2601 static bool rtw8822c_dpk_coef_iq_check(struct rtw_dev *rtwdev,
2602 u16 coef_i, u16 coef_q)
2603 {
2604 if (coef_i == 0x1000 || coef_i == 0x0fff ||
2605 coef_q == 0x1000 || coef_q == 0x0fff)
2606 return 1;
2607 else
2608 return 0;
2609 }
2610
2611 static u32 rtw8822c_dpk_coef_transfer(struct rtw_dev *rtwdev)
2612 {
2613 u32 reg = 0;
2614 u16 coef_i = 0, coef_q = 0;
2615
2616 reg = rtw_read32(rtwdev, REG_STAT_RPT);
2617
2618 coef_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD) & 0x1fff;
2619 coef_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD) & 0x1fff;
2620
2621 coef_q = ((0x2000 - coef_q) & 0x1fff) - 1;
2622
2623 reg = (coef_i << 16) | coef_q;
2624
2625 return reg;
2626 }
2627
2628 static const u32 rtw8822c_dpk_get_coef_tbl[] = {
2629 0x000400f0, 0x040400f0, 0x080400f0, 0x010400f0, 0x050400f0,
2630 0x090400f0, 0x020400f0, 0x060400f0, 0x0a0400f0, 0x030400f0,
2631 0x070400f0, 0x0b0400f0, 0x0c0400f0, 0x100400f0, 0x0d0400f0,
2632 0x110400f0, 0x0e0400f0, 0x120400f0, 0x0f0400f0, 0x130400f0,
2633 };
2634
2635 static void rtw8822c_dpk_coef_tbl_apply(struct rtw_dev *rtwdev, u8 path)
2636 {
2637 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2638 int i;
2639
2640 for (i = 0; i < 20; i++) {
2641 rtw_write32(rtwdev, REG_RXSRAM_CTL,
2642 rtw8822c_dpk_get_coef_tbl[i]);
2643 dpk_info->coef[path][i] = rtw8822c_dpk_coef_transfer(rtwdev);
2644 }
2645 }
2646
2647 static void rtw8822c_dpk_get_coef(struct rtw_dev *rtwdev, u8 path)
2648 {
2649 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c);
2650
2651 if (path == RF_PATH_A) {
2652 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x0);
2653 rtw_write32(rtwdev, REG_DPD_CTL0_S0, 0x30000080);
2654 } else if (path == RF_PATH_B) {
2655 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x1);
2656 rtw_write32(rtwdev, REG_DPD_CTL0_S1, 0x30000080);
2657 }
2658
2659 rtw8822c_dpk_coef_tbl_apply(rtwdev, path);
2660 }
2661
2662 static u8 rtw8822c_dpk_coef_read(struct rtw_dev *rtwdev, u8 path)
2663 {
2664 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2665 u8 addr, result = 1;
2666 u16 coef_i, coef_q;
2667
2668 for (addr = 0; addr < 20; addr++) {
2669 coef_i = FIELD_GET(0x1fff0000, dpk_info->coef[path][addr]);
2670 coef_q = FIELD_GET(0x1fff, dpk_info->coef[path][addr]);
2671
2672 if (rtw8822c_dpk_coef_iq_check(rtwdev, coef_i, coef_q)) {
2673 result = 0;
2674 break;
2675 }
2676 }
2677 return result;
2678 }
2679
2680 static void rtw8822c_dpk_coef_write(struct rtw_dev *rtwdev, u8 path, u8 result)
2681 {
2682 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2683 u16 reg[DPK_RF_PATH_NUM] = {0x1b0c, 0x1b64};
2684 u32 coef;
2685 u8 addr;
2686
2687 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c);
2688 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0);
2689
2690 for (addr = 0; addr < 20; addr++) {
2691 if (result == 0) {
2692 if (addr == 3)
2693 coef = 0x04001fff;
2694 else
2695 coef = 0x00001fff;
2696 } else {
2697 coef = dpk_info->coef[path][addr];
2698 }
2699 rtw_write32(rtwdev, reg[path] + addr * 4, coef);
2700 }
2701 }
2702
2703 static void rtw8822c_dpk_fill_result(struct rtw_dev *rtwdev, u32 dpk_txagc,
2704 u8 path, u8 result)
2705 {
2706 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2707
2708 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
2709
2710 if (result)
2711 rtw_write8(rtwdev, REG_DPD_AGC, (u8)(dpk_txagc - 6));
2712 else
2713 rtw_write8(rtwdev, REG_DPD_AGC, 0x00);
2714
2715 dpk_info->result[path] = result;
2716 dpk_info->dpk_txagc[path] = rtw_read8(rtwdev, REG_DPD_AGC);
2717
2718 rtw8822c_dpk_coef_write(rtwdev, path, result);
2719 }
2720
2721 static u32 rtw8822c_dpk_gainloss(struct rtw_dev *rtwdev, u8 path)
2722 {
2723 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2724 u8 tx_agc, tx_bb, ori_txbb, ori_txagc, tx_agc_search, t1, t2;
2725
2726 ori_txbb = rtw8822c_dpk_rf_setting(rtwdev, path);
2727 ori_txagc = (u8)rtw_read_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_TXAGC);
2728
2729 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path);
2730 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC);
2731 rtw8822c_dpk_dgain_read(rtwdev, path);
2732
2733 if (rtw8822c_dpk_dc_corr_check(rtwdev, path)) {
2734 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path);
2735 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC);
2736 rtw8822c_dpk_dc_corr_check(rtwdev, path);
2737 }
2738
2739 t1 = rtw8822c_dpk_thermal_read(rtwdev, path);
2740 tx_bb = rtw8822c_dpk_pas_agc(rtwdev, path, false, true);
2741 tx_agc_search = rtw8822c_dpk_gainloss_result(rtwdev, path);
2742
2743 if (tx_bb < tx_agc_search)
2744 tx_bb = 0;
2745 else
2746 tx_bb = tx_bb - tx_agc_search;
2747
2748 rtw_write_rf(rtwdev, path, RF_TX_GAIN, BIT_GAIN_TXBB, tx_bb);
2749
2750 tx_agc = ori_txagc - (ori_txbb - tx_bb);
2751
2752 t2 = rtw8822c_dpk_thermal_read(rtwdev, path);
2753
2754 dpk_info->thermal_dpk_delta[path] = abs(t2 - t1);
2755
2756 return tx_agc;
2757 }
2758
2759 static u8 rtw8822c_dpk_by_path(struct rtw_dev *rtwdev, u32 tx_agc, u8 path)
2760 {
2761 u8 result;
2762
2763 result = rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DO_DPK);
2764
2765 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
2766
2767 result = result | (u8)rtw_read32_mask(rtwdev, REG_DPD_CTL1_S0, BIT(26));
2768
2769 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x33e14);
2770
2771 rtw8822c_dpk_get_coef(rtwdev, path);
2772
2773 return result;
2774 }
2775
2776 static void rtw8822c_dpk_cal_gs(struct rtw_dev *rtwdev, u8 path)
2777 {
2778 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2779 u32 tmp_gs = 0;
2780
2781 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
2782 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_BYPASS_DPD, 0x0);
2783 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
2784 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9);
2785 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x1);
2786 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
2787 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0xf);
2788
2789 if (path == RF_PATH_A) {
2790 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF,
2791 0x1066680);
2792 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN, 0x1);
2793 } else {
2794 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF,
2795 0x1066680);
2796 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN, 0x1);
2797 }
2798
2799 if (dpk_info->dpk_bw == DPK_CHANNEL_WIDTH_80) {
2800 rtw_write32(rtwdev, REG_DPD_CTL16, 0x80001310);
2801 rtw_write32(rtwdev, REG_DPD_CTL16, 0x00001310);
2802 rtw_write32(rtwdev, REG_DPD_CTL16, 0x810000db);
2803 rtw_write32(rtwdev, REG_DPD_CTL16, 0x010000db);
2804 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428);
2805 rtw_write32(rtwdev, REG_DPD_CTL15,
2806 0x05020000 | (BIT(path) << 28));
2807 } else {
2808 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8200190c);
2809 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0200190c);
2810 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8301ee14);
2811 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0301ee14);
2812 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428);
2813 rtw_write32(rtwdev, REG_DPD_CTL15,
2814 0x05020008 | (BIT(path) << 28));
2815 }
2816
2817 rtw_write32_mask(rtwdev, REG_DPD_CTL0, MASKBYTE3, 0x8 | path);
2818
2819 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_CAL_PWR);
2820
2821 rtw_write32_mask(rtwdev, REG_DPD_CTL15, MASKBYTE3, 0x0);
2822 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
2823 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0);
2824 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x0);
2825 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
2826
2827 if (path == RF_PATH_A)
2828 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 0x5b);
2829 else
2830 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 0x5b);
2831
2832 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0);
2833
2834 tmp_gs = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, BIT_RPT_DGAIN);
2835 tmp_gs = (tmp_gs * 910) >> 10;
2836 tmp_gs = DIV_ROUND_CLOSEST(tmp_gs, 10);
2837
2838 if (path == RF_PATH_A)
2839 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, tmp_gs);
2840 else
2841 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, tmp_gs);
2842
2843 dpk_info->dpk_gs[path] = tmp_gs;
2844 }
2845
2846 void rtw8822c_dpk_cal_coef1(struct rtw_dev *rtwdev)
2847 {
2848 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2849 u32 offset[DPK_RF_PATH_NUM] = {0, 0x58};
2850 u32 i_scaling;
2851 u8 path;
2852
2853 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c);
2854 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0);
2855 rtw_write32(rtwdev, REG_NCTL0, 0x00001148);
2856 rtw_write32(rtwdev, REG_NCTL0, 0x00001149);
2857
2858 check_hw_ready(rtwdev, 0x2d9c, MASKBYTE0, 0x55);
2859
2860 rtw_write8(rtwdev, 0x1b10, 0x0);
2861 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c);
2862
2863 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
2864 i_scaling = 0x16c00 / dpk_info->dpk_gs[path];
2865
2866 rtw_write32_mask(rtwdev, 0x1b18 + offset[path], MASKHWORD,
2867 i_scaling);
2868 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path],
2869 GENMASK(31, 28), 0x9);
2870 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path],
2871 GENMASK(31, 28), 0x1);
2872 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path],
2873 GENMASK(31, 28), 0x0);
2874 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0 + offset[path],
2875 BIT(14), 0x0);
2876 }
2877 }
2878
2879 static void rtw8822c_dpk_on(struct rtw_dev *rtwdev, u8 path)
2880 {
2881 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2882
2883 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DPK_ON);
2884
2885 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
2886 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
2887
2888 if (test_bit(path, dpk_info->dpk_path_ok))
2889 rtw8822c_dpk_cal_gs(rtwdev, path);
2890 }
2891
2892 static bool rtw8822c_dpk_check_pass(struct rtw_dev *rtwdev, bool is_fail,
2893 u32 dpk_txagc, u8 path)
2894 {
2895 bool result;
2896
2897 if (!is_fail) {
2898 if (rtw8822c_dpk_coef_read(rtwdev, path))
2899 result = true;
2900 else
2901 result = false;
2902 } else {
2903 result = false;
2904 }
2905
2906 rtw8822c_dpk_fill_result(rtwdev, dpk_txagc, path, result);
2907
2908 return result;
2909 }
2910
2911 static void rtw8822c_dpk_result_reset(struct rtw_dev *rtwdev)
2912 {
2913 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2914 u8 path;
2915
2916 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
2917 clear_bit(path, dpk_info->dpk_path_ok);
2918 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
2919 0x8 | (path << 1));
2920 rtw_write32_mask(rtwdev, 0x1b58, 0x0000007f, 0x0);
2921
2922 dpk_info->dpk_txagc[path] = 0;
2923 dpk_info->result[path] = 0;
2924 dpk_info->dpk_gs[path] = 0x5b;
2925 dpk_info->pre_pwsf[path] = 0;
2926 dpk_info->thermal_dpk[path] = rtw8822c_dpk_thermal_read(rtwdev,
2927 path);
2928 }
2929 }
2930
2931 static void rtw8822c_dpk_calibrate(struct rtw_dev *rtwdev, u8 path)
2932 {
2933 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2934 u32 dpk_txagc;
2935 u8 dpk_fail;
2936
2937 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] s%d dpk start\n", path);
2938
2939 dpk_txagc = rtw8822c_dpk_gainloss(rtwdev, path);
2940
2941 dpk_fail = rtw8822c_dpk_by_path(rtwdev, dpk_txagc, path);
2942
2943 if (!rtw8822c_dpk_check_pass(rtwdev, dpk_fail, dpk_txagc, path))
2944 rtw_err(rtwdev, "failed to do dpk calibration\n");
2945
2946 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] s%d dpk finish\n", path);
2947
2948 if (dpk_info->result[path])
2949 set_bit(path, dpk_info->dpk_path_ok);
2950 }
2951
2952 static void rtw8822c_dpk_path_select(struct rtw_dev *rtwdev)
2953 {
2954 rtw8822c_dpk_calibrate(rtwdev, RF_PATH_A);
2955 rtw8822c_dpk_calibrate(rtwdev, RF_PATH_B);
2956 rtw8822c_dpk_on(rtwdev, RF_PATH_A);
2957 rtw8822c_dpk_on(rtwdev, RF_PATH_B);
2958 rtw8822c_dpk_cal_coef1(rtwdev);
2959 }
2960
2961 static void rtw8822c_dpk_enable_disable(struct rtw_dev *rtwdev)
2962 {
2963 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2964 u32 mask = BIT(15) | BIT(14);
2965
2966 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
2967
2968 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN,
2969 dpk_info->is_dpk_pwr_on);
2970 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN,
2971 dpk_info->is_dpk_pwr_on);
2972
2973 if (test_bit(RF_PATH_A, dpk_info->dpk_path_ok)) {
2974 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, mask, 0x0);
2975 rtw_write8(rtwdev, REG_DPD_CTL0_S0, dpk_info->dpk_gs[RF_PATH_A]);
2976 }
2977 if (test_bit(RF_PATH_B, dpk_info->dpk_path_ok)) {
2978 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, mask, 0x0);
2979 rtw_write8(rtwdev, REG_DPD_CTL0_S1, dpk_info->dpk_gs[RF_PATH_B]);
2980 }
2981 }
2982
2983 static void rtw8822c_dpk_reload_data(struct rtw_dev *rtwdev)
2984 {
2985 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
2986 u8 path;
2987
2988 if (!test_bit(RF_PATH_A, dpk_info->dpk_path_ok) &&
2989 !test_bit(RF_PATH_B, dpk_info->dpk_path_ok) &&
2990 dpk_info->dpk_ch == 0)
2991 return;
2992
2993 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
2994 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
2995 0x8 | (path << 1));
2996 if (dpk_info->dpk_band == RTW_BAND_2G)
2997 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f100000);
2998 else
2999 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f0d0000);
3000
3001 rtw_write8(rtwdev, REG_DPD_AGC, dpk_info->dpk_txagc[path]);
3002
3003 rtw8822c_dpk_coef_write(rtwdev, path,
3004 test_bit(path, dpk_info->dpk_path_ok));
3005
3006 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DPK_ON);
3007
3008 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3009
3010 if (path == RF_PATH_A)
3011 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF,
3012 dpk_info->dpk_gs[path]);
3013 else
3014 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF,
3015 dpk_info->dpk_gs[path]);
3016 }
3017 rtw8822c_dpk_cal_coef1(rtwdev);
3018 }
3019
3020 static bool rtw8822c_dpk_reload(struct rtw_dev *rtwdev)
3021 {
3022 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3023 u8 channel;
3024
3025 dpk_info->is_reload = false;
3026
3027 channel = (u8)(rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK) & 0xff);
3028
3029 if (channel == dpk_info->dpk_ch) {
3030 rtw_dbg(rtwdev, RTW_DBG_RFK,
3031 "[DPK] DPK reload for CH%d!!\n", dpk_info->dpk_ch);
3032 rtw8822c_dpk_reload_data(rtwdev);
3033 dpk_info->is_reload = true;
3034 }
3035
3036 return dpk_info->is_reload;
3037 }
3038
3039 static void rtw8822c_do_dpk(struct rtw_dev *rtwdev)
3040 {
3041 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3042 struct rtw_backup_info bckp[DPK_BB_REG_NUM];
3043 u32 rf_reg_backup[DPK_RF_REG_NUM][DPK_RF_PATH_NUM];
3044 u32 bb_reg[DPK_BB_REG_NUM] = {
3045 0x520, 0x820, 0x824, 0x1c3c, 0x1d58, 0x1864,
3046 0x4164, 0x180c, 0x410c, 0x186c, 0x416c,
3047 0x1a14, 0x1e70, 0x80c, 0x1d70, 0x1e7c, 0x18a4, 0x41a4};
3048 u32 rf_reg[DPK_RF_REG_NUM] = {
3049 0x0, 0x1a, 0x55, 0x63, 0x87, 0x8f, 0xde};
3050 u8 path;
3051
3052 if (!dpk_info->is_dpk_pwr_on) {
3053 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] Skip DPK due to DPD PWR off\n");
3054 return;
3055 } else if (rtw8822c_dpk_reload(rtwdev)) {
3056 return;
3057 }
3058
3059 for (path = RF_PATH_A; path < DPK_RF_PATH_NUM; path++)
3060 ewma_thermal_init(&dpk_info->avg_thermal[path]);
3061
3062 rtw8822c_dpk_information(rtwdev);
3063
3064 rtw8822c_dpk_backup_registers(rtwdev, bb_reg, DPK_BB_REG_NUM, bckp);
3065 rtw8822c_dpk_backup_rf_registers(rtwdev, rf_reg, rf_reg_backup);
3066
3067 rtw8822c_dpk_mac_bb_setting(rtwdev);
3068 rtw8822c_dpk_afe_setting(rtwdev, true);
3069 rtw8822c_dpk_pre_setting(rtwdev);
3070 rtw8822c_dpk_result_reset(rtwdev);
3071 rtw8822c_dpk_path_select(rtwdev);
3072 rtw8822c_dpk_afe_setting(rtwdev, false);
3073 rtw8822c_dpk_enable_disable(rtwdev);
3074
3075 rtw8822c_dpk_reload_rf_registers(rtwdev, rf_reg, rf_reg_backup);
3076 for (path = 0; path < rtwdev->hal.rf_path_num; path++)
3077 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path);
3078 rtw8822c_dpk_restore_registers(rtwdev, DPK_BB_REG_NUM, bckp);
3079 }
3080
3081 static void rtw8822c_phy_calibration(struct rtw_dev *rtwdev)
3082 {
3083 rtw8822c_do_iqk(rtwdev);
3084 rtw8822c_do_dpk(rtwdev);
3085 }
3086
3087 void rtw8822c_dpk_track(struct rtw_dev *rtwdev)
3088 {
3089 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3090 u8 path;
3091 u8 thermal_value[DPK_RF_PATH_NUM] = {0};
3092 s8 offset[DPK_RF_PATH_NUM], delta_dpk[DPK_RF_PATH_NUM];
3093
3094 if (dpk_info->thermal_dpk[0] == 0 && dpk_info->thermal_dpk[1] == 0)
3095 return;
3096
3097 for (path = 0; path < DPK_RF_PATH_NUM; path++) {
3098 thermal_value[path] = rtw8822c_dpk_thermal_read(rtwdev, path);
3099 ewma_thermal_add(&dpk_info->avg_thermal[path],
3100 thermal_value[path]);
3101 thermal_value[path] =
3102 ewma_thermal_read(&dpk_info->avg_thermal[path]);
3103 delta_dpk[path] = dpk_info->thermal_dpk[path] -
3104 thermal_value[path];
3105 offset[path] = delta_dpk[path] -
3106 dpk_info->thermal_dpk_delta[path];
3107 offset[path] &= 0x7f;
3108
3109 if (offset[path] != dpk_info->pre_pwsf[path]) {
3110 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
3111 0x8 | (path << 1));
3112 rtw_write32_mask(rtwdev, 0x1b58, GENMASK(6, 0),
3113 offset[path]);
3114 dpk_info->pre_pwsf[path] = offset[path];
3115 }
3116 }
3117 }
3118
3119 static const struct rtw_phy_cck_pd_reg
3120 rtw8822c_cck_pd_reg[RTW_CHANNEL_WIDTH_40 + 1][RTW_RF_PATH_MAX] = {
3121 {
3122 {0x1ac8, 0x00ff, 0x1ad0, 0x01f},
3123 {0x1ac8, 0xff00, 0x1ad0, 0x3e0}
3124 },
3125 {
3126 {0x1acc, 0x00ff, 0x1ad0, 0x01F00000},
3127 {0x1acc, 0xff00, 0x1ad0, 0x3E000000}
3128 },
3129 };
3130
3131 #define RTW_CCK_PD_MAX 255
3132 #define RTW_CCK_CS_MAX 31
3133 #define RTW_CCK_CS_ERR1 27
3134 #define RTW_CCK_CS_ERR2 29
3135 static void
3136 rtw8822c_phy_cck_pd_set_reg(struct rtw_dev *rtwdev,
3137 s8 pd_diff, s8 cs_diff, u8 bw, u8 nrx)
3138 {
3139 u32 pd, cs;
3140
3141 if (WARN_ON(bw > RTW_CHANNEL_WIDTH_40 || nrx >= RTW_RF_PATH_MAX))
3142 return;
3143
3144 pd = rtw_read32_mask(rtwdev,
3145 rtw8822c_cck_pd_reg[bw][nrx].reg_pd,
3146 rtw8822c_cck_pd_reg[bw][nrx].mask_pd);
3147 cs = rtw_read32_mask(rtwdev,
3148 rtw8822c_cck_pd_reg[bw][nrx].reg_cs,
3149 rtw8822c_cck_pd_reg[bw][nrx].mask_cs);
3150 pd += pd_diff;
3151 cs += cs_diff;
3152 if (pd > RTW_CCK_PD_MAX)
3153 pd = RTW_CCK_PD_MAX;
3154 if (cs == RTW_CCK_CS_ERR1 || cs == RTW_CCK_CS_ERR2)
3155 cs++;
3156 else if (cs > RTW_CCK_CS_MAX)
3157 cs = RTW_CCK_CS_MAX;
3158 rtw_write32_mask(rtwdev,
3159 rtw8822c_cck_pd_reg[bw][nrx].reg_pd,
3160 rtw8822c_cck_pd_reg[bw][nrx].mask_pd,
3161 pd);
3162 rtw_write32_mask(rtwdev,
3163 rtw8822c_cck_pd_reg[bw][nrx].reg_cs,
3164 rtw8822c_cck_pd_reg[bw][nrx].mask_cs,
3165 cs);
3166 }
3167
3168 static void rtw8822c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl)
3169 {
3170 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
3171 s8 pd_lvl[CCK_PD_LV_MAX] = {0, 2, 4, 6, 8};
3172 s8 cs_lvl[CCK_PD_LV_MAX] = {0, 2, 2, 2, 4};
3173 u8 cur_lvl;
3174 u8 nrx, bw;
3175
3176 nrx = (u8)rtw_read32_mask(rtwdev, 0x1a2c, 0x60000);
3177 bw = (u8)rtw_read32_mask(rtwdev, 0x9b0, 0xc);
3178
3179 if (dm_info->cck_pd_lv[bw][nrx] == new_lvl)
3180 return;
3181
3182 cur_lvl = dm_info->cck_pd_lv[bw][nrx];
3183
3184
3185 dm_info->cck_fa_avg = CCK_FA_AVG_RESET;
3186
3187 rtw8822c_phy_cck_pd_set_reg(rtwdev,
3188 pd_lvl[new_lvl] - pd_lvl[cur_lvl],
3189 cs_lvl[new_lvl] - cs_lvl[cur_lvl],
3190 bw, nrx);
3191 dm_info->cck_pd_lv[bw][nrx] = new_lvl;
3192 }
3193
3194 static struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8822c[] = {
3195 {0x0086,
3196 RTW_PWR_CUT_ALL_MSK,
3197 RTW_PWR_INTF_SDIO_MSK,
3198 RTW_PWR_ADDR_SDIO,
3199 RTW_PWR_CMD_WRITE, BIT(0), 0},
3200 {0x0086,
3201 RTW_PWR_CUT_ALL_MSK,
3202 RTW_PWR_INTF_SDIO_MSK,
3203 RTW_PWR_ADDR_SDIO,
3204 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
3205 {0x002E,
3206 RTW_PWR_CUT_ALL_MSK,
3207 RTW_PWR_INTF_ALL_MSK,
3208 RTW_PWR_ADDR_MAC,
3209 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
3210 {0x002D,
3211 RTW_PWR_CUT_ALL_MSK,
3212 RTW_PWR_INTF_ALL_MSK,
3213 RTW_PWR_ADDR_MAC,
3214 RTW_PWR_CMD_WRITE, BIT(0), 0},
3215 {0x007F,
3216 RTW_PWR_CUT_ALL_MSK,
3217 RTW_PWR_INTF_ALL_MSK,
3218 RTW_PWR_ADDR_MAC,
3219 RTW_PWR_CMD_WRITE, BIT(7), 0},
3220 {0x004A,
3221 RTW_PWR_CUT_ALL_MSK,
3222 RTW_PWR_INTF_USB_MSK,
3223 RTW_PWR_ADDR_MAC,
3224 RTW_PWR_CMD_WRITE, BIT(0), 0},
3225 {0x0005,
3226 RTW_PWR_CUT_ALL_MSK,
3227 RTW_PWR_INTF_ALL_MSK,
3228 RTW_PWR_ADDR_MAC,
3229 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
3230 {0xFFFF,
3231 RTW_PWR_CUT_ALL_MSK,
3232 RTW_PWR_INTF_ALL_MSK,
3233 0,
3234 RTW_PWR_CMD_END, 0, 0},
3235 };
3236
3237 static struct rtw_pwr_seq_cmd trans_cardemu_to_act_8822c[] = {
3238 {0x0000,
3239 RTW_PWR_CUT_ALL_MSK,
3240 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
3241 RTW_PWR_ADDR_MAC,
3242 RTW_PWR_CMD_WRITE, BIT(5), 0},
3243 {0x0005,
3244 RTW_PWR_CUT_ALL_MSK,
3245 RTW_PWR_INTF_ALL_MSK,
3246 RTW_PWR_ADDR_MAC,
3247 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
3248 {0x0075,
3249 RTW_PWR_CUT_ALL_MSK,
3250 RTW_PWR_INTF_PCI_MSK,
3251 RTW_PWR_ADDR_MAC,
3252 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
3253 {0x0006,
3254 RTW_PWR_CUT_ALL_MSK,
3255 RTW_PWR_INTF_ALL_MSK,
3256 RTW_PWR_ADDR_MAC,
3257 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
3258 {0x0075,
3259 RTW_PWR_CUT_ALL_MSK,
3260 RTW_PWR_INTF_PCI_MSK,
3261 RTW_PWR_ADDR_MAC,
3262 RTW_PWR_CMD_WRITE, BIT(0), 0},
3263 {0xFF1A,
3264 RTW_PWR_CUT_ALL_MSK,
3265 RTW_PWR_INTF_USB_MSK,
3266 RTW_PWR_ADDR_MAC,
3267 RTW_PWR_CMD_WRITE, 0xFF, 0},
3268 {0x002E,
3269 RTW_PWR_CUT_ALL_MSK,
3270 RTW_PWR_INTF_ALL_MSK,
3271 RTW_PWR_ADDR_MAC,
3272 RTW_PWR_CMD_WRITE, BIT(3), 0},
3273 {0x0006,
3274 RTW_PWR_CUT_ALL_MSK,
3275 RTW_PWR_INTF_ALL_MSK,
3276 RTW_PWR_ADDR_MAC,
3277 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
3278 {0x0005,
3279 RTW_PWR_CUT_ALL_MSK,
3280 RTW_PWR_INTF_ALL_MSK,
3281 RTW_PWR_ADDR_MAC,
3282 RTW_PWR_CMD_WRITE, BIT(7), 0},
3283 {0x0005,
3284 RTW_PWR_CUT_ALL_MSK,
3285 RTW_PWR_INTF_ALL_MSK,
3286 RTW_PWR_ADDR_MAC,
3287 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
3288 {0x0005,
3289 RTW_PWR_CUT_ALL_MSK,
3290 RTW_PWR_INTF_ALL_MSK,
3291 RTW_PWR_ADDR_MAC,
3292 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
3293 {0x0005,
3294 RTW_PWR_CUT_ALL_MSK,
3295 RTW_PWR_INTF_ALL_MSK,
3296 RTW_PWR_ADDR_MAC,
3297 RTW_PWR_CMD_POLLING, BIT(0), 0},
3298 {0x0074,
3299 RTW_PWR_CUT_ALL_MSK,
3300 RTW_PWR_INTF_PCI_MSK,
3301 RTW_PWR_ADDR_MAC,
3302 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
3303 {0x0071,
3304 RTW_PWR_CUT_ALL_MSK,
3305 RTW_PWR_INTF_PCI_MSK,
3306 RTW_PWR_ADDR_MAC,
3307 RTW_PWR_CMD_WRITE, BIT(4), 0},
3308 {0x0062,
3309 RTW_PWR_CUT_ALL_MSK,
3310 RTW_PWR_INTF_PCI_MSK,
3311 RTW_PWR_ADDR_MAC,
3312 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)),
3313 (BIT(7) | BIT(6) | BIT(5))},
3314 {0x0061,
3315 RTW_PWR_CUT_ALL_MSK,
3316 RTW_PWR_INTF_PCI_MSK,
3317 RTW_PWR_ADDR_MAC,
3318 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0},
3319 {0x001F,
3320 RTW_PWR_CUT_ALL_MSK,
3321 RTW_PWR_INTF_ALL_MSK,
3322 RTW_PWR_ADDR_MAC,
3323 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)},
3324 {0x00EF,
3325 RTW_PWR_CUT_ALL_MSK,
3326 RTW_PWR_INTF_ALL_MSK,
3327 RTW_PWR_ADDR_MAC,
3328 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)},
3329 {0x1045,
3330 RTW_PWR_CUT_ALL_MSK,
3331 RTW_PWR_INTF_ALL_MSK,
3332 RTW_PWR_ADDR_MAC,
3333 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
3334 {0x0010,
3335 RTW_PWR_CUT_ALL_MSK,
3336 RTW_PWR_INTF_ALL_MSK,
3337 RTW_PWR_ADDR_MAC,
3338 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
3339 {0xFFFF,
3340 RTW_PWR_CUT_ALL_MSK,
3341 RTW_PWR_INTF_ALL_MSK,
3342 0,
3343 RTW_PWR_CMD_END, 0, 0},
3344 };
3345
3346 static struct rtw_pwr_seq_cmd trans_act_to_cardemu_8822c[] = {
3347 {0x0093,
3348 RTW_PWR_CUT_ALL_MSK,
3349 RTW_PWR_INTF_ALL_MSK,
3350 RTW_PWR_ADDR_MAC,
3351 RTW_PWR_CMD_WRITE, BIT(3), 0},
3352 {0x001F,
3353 RTW_PWR_CUT_ALL_MSK,
3354 RTW_PWR_INTF_ALL_MSK,
3355 RTW_PWR_ADDR_MAC,
3356 RTW_PWR_CMD_WRITE, 0xFF, 0},
3357 {0x00EF,
3358 RTW_PWR_CUT_ALL_MSK,
3359 RTW_PWR_INTF_ALL_MSK,
3360 RTW_PWR_ADDR_MAC,
3361 RTW_PWR_CMD_WRITE, 0xFF, 0},
3362 {0x1045,
3363 RTW_PWR_CUT_ALL_MSK,
3364 RTW_PWR_INTF_ALL_MSK,
3365 RTW_PWR_ADDR_MAC,
3366 RTW_PWR_CMD_WRITE, BIT(4), 0},
3367 {0xFF1A,
3368 RTW_PWR_CUT_ALL_MSK,
3369 RTW_PWR_INTF_USB_MSK,
3370 RTW_PWR_ADDR_MAC,
3371 RTW_PWR_CMD_WRITE, 0xFF, 0x30},
3372 {0x0049,
3373 RTW_PWR_CUT_ALL_MSK,
3374 RTW_PWR_INTF_ALL_MSK,
3375 RTW_PWR_ADDR_MAC,
3376 RTW_PWR_CMD_WRITE, BIT(1), 0},
3377 {0x0006,
3378 RTW_PWR_CUT_ALL_MSK,
3379 RTW_PWR_INTF_ALL_MSK,
3380 RTW_PWR_ADDR_MAC,
3381 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
3382 {0x0002,
3383 RTW_PWR_CUT_ALL_MSK,
3384 RTW_PWR_INTF_ALL_MSK,
3385 RTW_PWR_ADDR_MAC,
3386 RTW_PWR_CMD_WRITE, BIT(1), 0},
3387 {0x0005,
3388 RTW_PWR_CUT_ALL_MSK,
3389 RTW_PWR_INTF_ALL_MSK,
3390 RTW_PWR_ADDR_MAC,
3391 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
3392 {0x0005,
3393 RTW_PWR_CUT_ALL_MSK,
3394 RTW_PWR_INTF_ALL_MSK,
3395 RTW_PWR_ADDR_MAC,
3396 RTW_PWR_CMD_POLLING, BIT(1), 0},
3397 {0x0000,
3398 RTW_PWR_CUT_ALL_MSK,
3399 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
3400 RTW_PWR_ADDR_MAC,
3401 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
3402 {0xFFFF,
3403 RTW_PWR_CUT_ALL_MSK,
3404 RTW_PWR_INTF_ALL_MSK,
3405 0,
3406 RTW_PWR_CMD_END, 0, 0},
3407 };
3408
3409 static struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8822c[] = {
3410 {0x0005,
3411 RTW_PWR_CUT_ALL_MSK,
3412 RTW_PWR_INTF_SDIO_MSK,
3413 RTW_PWR_ADDR_MAC,
3414 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
3415 {0x0007,
3416 RTW_PWR_CUT_ALL_MSK,
3417 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
3418 RTW_PWR_ADDR_MAC,
3419 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
3420 {0x0067,
3421 RTW_PWR_CUT_ALL_MSK,
3422 RTW_PWR_INTF_ALL_MSK,
3423 RTW_PWR_ADDR_MAC,
3424 RTW_PWR_CMD_WRITE, BIT(5), 0},
3425 {0x004A,
3426 RTW_PWR_CUT_ALL_MSK,
3427 RTW_PWR_INTF_USB_MSK,
3428 RTW_PWR_ADDR_MAC,
3429 RTW_PWR_CMD_WRITE, BIT(0), 0},
3430 {0x0081,
3431 RTW_PWR_CUT_ALL_MSK,
3432 RTW_PWR_INTF_ALL_MSK,
3433 RTW_PWR_ADDR_MAC,
3434 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
3435 {0x0090,
3436 RTW_PWR_CUT_ALL_MSK,
3437 RTW_PWR_INTF_ALL_MSK,
3438 RTW_PWR_ADDR_MAC,
3439 RTW_PWR_CMD_WRITE, BIT(1), 0},
3440 {0x0092,
3441 RTW_PWR_CUT_ALL_MSK,
3442 RTW_PWR_INTF_PCI_MSK,
3443 RTW_PWR_ADDR_MAC,
3444 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
3445 {0x0093,
3446 RTW_PWR_CUT_ALL_MSK,
3447 RTW_PWR_INTF_PCI_MSK,
3448 RTW_PWR_ADDR_MAC,
3449 RTW_PWR_CMD_WRITE, 0xFF, 0x04},
3450 {0x0005,
3451 RTW_PWR_CUT_ALL_MSK,
3452 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
3453 RTW_PWR_ADDR_MAC,
3454 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
3455 {0x0005,
3456 RTW_PWR_CUT_ALL_MSK,
3457 RTW_PWR_INTF_PCI_MSK,
3458 RTW_PWR_ADDR_MAC,
3459 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
3460 {0x0086,
3461 RTW_PWR_CUT_ALL_MSK,
3462 RTW_PWR_INTF_SDIO_MSK,
3463 RTW_PWR_ADDR_SDIO,
3464 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
3465 {0xFFFF,
3466 RTW_PWR_CUT_ALL_MSK,
3467 RTW_PWR_INTF_ALL_MSK,
3468 0,
3469 RTW_PWR_CMD_END, 0, 0},
3470 };
3471
3472 static struct rtw_pwr_seq_cmd *card_enable_flow_8822c[] = {
3473 trans_carddis_to_cardemu_8822c,
3474 trans_cardemu_to_act_8822c,
3475 NULL
3476 };
3477
3478 static struct rtw_pwr_seq_cmd *card_disable_flow_8822c[] = {
3479 trans_act_to_cardemu_8822c,
3480 trans_cardemu_to_carddis_8822c,
3481 NULL
3482 };
3483
3484 static struct rtw_intf_phy_para usb2_param_8822c[] = {
3485 {0xFFFF, 0x00,
3486 RTW_IP_SEL_PHY,
3487 RTW_INTF_PHY_CUT_ALL,
3488 RTW_INTF_PHY_PLATFORM_ALL},
3489 };
3490
3491 static struct rtw_intf_phy_para usb3_param_8822c[] = {
3492 {0xFFFF, 0x0000,
3493 RTW_IP_SEL_PHY,
3494 RTW_INTF_PHY_CUT_ALL,
3495 RTW_INTF_PHY_PLATFORM_ALL},
3496 };
3497
3498 static struct rtw_intf_phy_para pcie_gen1_param_8822c[] = {
3499 {0xFFFF, 0x0000,
3500 RTW_IP_SEL_PHY,
3501 RTW_INTF_PHY_CUT_ALL,
3502 RTW_INTF_PHY_PLATFORM_ALL},
3503 };
3504
3505 static struct rtw_intf_phy_para pcie_gen2_param_8822c[] = {
3506 {0xFFFF, 0x0000,
3507 RTW_IP_SEL_PHY,
3508 RTW_INTF_PHY_CUT_ALL,
3509 RTW_INTF_PHY_PLATFORM_ALL},
3510 };
3511
3512 static struct rtw_intf_phy_para_table phy_para_table_8822c = {
3513 .usb2_para = usb2_param_8822c,
3514 .usb3_para = usb3_param_8822c,
3515 .gen1_para = pcie_gen1_param_8822c,
3516 .gen2_para = pcie_gen2_param_8822c,
3517 .n_usb2_para = ARRAY_SIZE(usb2_param_8822c),
3518 .n_usb3_para = ARRAY_SIZE(usb2_param_8822c),
3519 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8822c),
3520 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8822c),
3521 };
3522
3523 static const struct rtw_rfe_def rtw8822c_rfe_defs[] = {
3524 [0] = RTW_DEF_RFE(8822c, 0, 0),
3525 [1] = RTW_DEF_RFE(8822c, 0, 0),
3526 [2] = RTW_DEF_RFE(8822c, 0, 0),
3527 };
3528
3529 static struct rtw_hw_reg rtw8822c_dig[] = {
3530 [0] = { .addr = 0x1d70, .mask = 0x7f },
3531 [1] = { .addr = 0x1d70, .mask = 0x7f00 },
3532 };
3533
3534 static struct rtw_page_table page_table_8822c[] = {
3535 {64, 64, 64, 64, 1},
3536 {64, 64, 64, 64, 1},
3537 {64, 64, 0, 0, 1},
3538 {64, 64, 64, 0, 1},
3539 {64, 64, 64, 64, 1},
3540 };
3541
3542 static struct rtw_rqpn rqpn_table_8822c[] = {
3543 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
3544 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
3545 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
3546 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
3547 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
3548 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
3549 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
3550 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH,
3551 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
3552 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
3553 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
3554 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
3555 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
3556 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
3557 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
3558 };
3559
3560 static struct rtw_chip_ops rtw8822c_ops = {
3561 .phy_set_param = rtw8822c_phy_set_param,
3562 .read_efuse = rtw8822c_read_efuse,
3563 .query_rx_desc = rtw8822c_query_rx_desc,
3564 .set_channel = rtw8822c_set_channel,
3565 .mac_init = rtw8822c_mac_init,
3566 .read_rf = rtw_phy_read_rf,
3567 .write_rf = rtw_phy_write_rf_reg_mix,
3568 .set_tx_power_index = rtw8822c_set_tx_power_index,
3569 .cfg_ldo25 = rtw8822c_cfg_ldo25,
3570 .false_alarm_statistics = rtw8822c_false_alarm_statistics,
3571 .dpk_track = rtw8822c_dpk_track,
3572 .phy_calibration = rtw8822c_phy_calibration,
3573 .cck_pd_set = rtw8822c_phy_cck_pd_set,
3574
3575 .coex_set_init = rtw8822c_coex_cfg_init,
3576 .coex_set_ant_switch = NULL,
3577 .coex_set_gnt_fix = rtw8822c_coex_cfg_gnt_fix,
3578 .coex_set_gnt_debug = rtw8822c_coex_cfg_gnt_debug,
3579 .coex_set_rfe_type = rtw8822c_coex_cfg_rfe_type,
3580 .coex_set_wl_tx_power = rtw8822c_coex_cfg_wl_tx_power,
3581 .coex_set_wl_rx_gain = rtw8822c_coex_cfg_wl_rx_gain,
3582 };
3583
3584
3585 static const struct coex_table_para table_sant_8822c[] = {
3586 {0xffffffff, 0xffffffff},
3587 {0x55555555, 0x55555555},
3588 {0x66555555, 0x66555555},
3589 {0xaaaaaaaa, 0xaaaaaaaa},
3590 {0x5a5a5a5a, 0x5a5a5a5a},
3591 {0xfafafafa, 0xfafafafa},
3592 {0x6a5a6a5a, 0xaaaaaaaa},
3593 {0x6a5a56aa, 0x6a5a56aa},
3594 {0x6a5a5a5a, 0x6a5a5a5a},
3595 {0x66555555, 0x5a5a5a5a},
3596 {0x66555555, 0x6a5a5a5a},
3597 {0x66555555, 0xfafafafa},
3598 {0x66555555, 0x6a5a5aaa},
3599 {0x66555555, 0x5aaa5aaa},
3600 {0x66555555, 0xaaaa5aaa},
3601 {0x66555555, 0xaaaaaaaa},
3602 {0xffff55ff, 0xfafafafa},
3603 {0xffff55ff, 0x6afa5afa},
3604 {0xaaffffaa, 0xfafafafa},
3605 {0xaa5555aa, 0x5a5a5a5a},
3606 {0xaa5555aa, 0x6a5a5a5a},
3607 {0xaa5555aa, 0xaaaaaaaa},
3608 {0xffffffff, 0x5a5a5a5a},
3609 {0xffffffff, 0x6a5a5a5a},
3610 {0xffffffff, 0x55555555},
3611 {0xffffffff, 0x6a5a5aaa},
3612 {0x55555555, 0x5a5a5a5a},
3613 {0x55555555, 0xaaaaaaaa},
3614 {0x55555555, 0x6a5a6a5a},
3615 {0x66556655, 0x66556655}
3616 };
3617
3618
3619 static const struct coex_table_para table_nsant_8822c[] = {
3620 {0xffffffff, 0xffffffff},
3621 {0x55555555, 0x55555555},
3622 {0x66555555, 0x66555555},
3623 {0xaaaaaaaa, 0xaaaaaaaa},
3624 {0x5a5a5a5a, 0x5a5a5a5a},
3625 {0xfafafafa, 0xfafafafa},
3626 {0x5afa5afa, 0x5afa5afa},
3627 {0x55555555, 0xfafafafa},
3628 {0x66555555, 0xfafafafa},
3629 {0x66555555, 0x5a5a5a5a},
3630 {0x66555555, 0x6a5a5a5a},
3631 {0x66555555, 0xaaaaaaaa},
3632 {0xffff55ff, 0xfafafafa},
3633 {0xffff55ff, 0x5afa5afa},
3634 {0xffff55ff, 0xaaaaaaaa},
3635 {0xaaffffaa, 0xfafafafa},
3636 {0xaaffffaa, 0x5afa5afa},
3637 {0xaaffffaa, 0xaaaaaaaa},
3638 {0xffffffff, 0xfafafafa},
3639 {0xffffffff, 0x5afa5afa},
3640 {0xffffffff, 0xaaaaaaaa},
3641 {0x55ff55ff, 0x5afa5afa},
3642 {0x55ff55ff, 0xaaaaaaaa},
3643 {0x55ff55ff, 0x55ff55ff}
3644 };
3645
3646
3647 static const struct coex_tdma_para tdma_sant_8822c[] = {
3648 { {0x00, 0x00, 0x00, 0x00, 0x00} },
3649 { {0x61, 0x45, 0x03, 0x11, 0x11} },
3650 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
3651 { {0x61, 0x30, 0x03, 0x11, 0x11} },
3652 { {0x61, 0x20, 0x03, 0x11, 0x11} },
3653 { {0x61, 0x10, 0x03, 0x11, 0x11} },
3654 { {0x61, 0x45, 0x03, 0x11, 0x10} },
3655 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
3656 { {0x61, 0x30, 0x03, 0x11, 0x10} },
3657 { {0x61, 0x20, 0x03, 0x11, 0x10} },
3658 { {0x61, 0x10, 0x03, 0x11, 0x10} },
3659 { {0x61, 0x08, 0x03, 0x11, 0x14} },
3660 { {0x61, 0x08, 0x03, 0x10, 0x14} },
3661 { {0x51, 0x08, 0x03, 0x10, 0x54} },
3662 { {0x51, 0x08, 0x03, 0x10, 0x55} },
3663 { {0x51, 0x08, 0x07, 0x10, 0x54} },
3664 { {0x51, 0x45, 0x03, 0x10, 0x10} },
3665 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
3666 { {0x51, 0x30, 0x03, 0x10, 0x50} },
3667 { {0x51, 0x20, 0x03, 0x10, 0x50} },
3668 { {0x51, 0x10, 0x03, 0x10, 0x50} },
3669 { {0x51, 0x4a, 0x03, 0x10, 0x50} },
3670 { {0x51, 0x0c, 0x03, 0x10, 0x54} },
3671 { {0x55, 0x08, 0x03, 0x10, 0x54} },
3672 { {0x65, 0x10, 0x03, 0x11, 0x11} },
3673 { {0x51, 0x10, 0x03, 0x10, 0x51} },
3674 { {0x51, 0x08, 0x03, 0x10, 0x50} }
3675 };
3676
3677
3678 static const struct coex_tdma_para tdma_nsant_8822c[] = {
3679 { {0x00, 0x00, 0x00, 0x00, 0x00} },
3680 { {0x61, 0x45, 0x03, 0x11, 0x11} },
3681 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
3682 { {0x61, 0x30, 0x03, 0x11, 0x11} },
3683 { {0x61, 0x20, 0x03, 0x11, 0x11} },
3684 { {0x61, 0x10, 0x03, 0x11, 0x11} },
3685 { {0x61, 0x45, 0x03, 0x11, 0x10} },
3686 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
3687 { {0x61, 0x30, 0x03, 0x11, 0x10} },
3688 { {0x61, 0x20, 0x03, 0x11, 0x10} },
3689 { {0x61, 0x10, 0x03, 0x11, 0x10} },
3690 { {0x61, 0x08, 0x03, 0x11, 0x14} },
3691 { {0x61, 0x08, 0x03, 0x10, 0x14} },
3692 { {0x51, 0x08, 0x03, 0x10, 0x54} },
3693 { {0x51, 0x08, 0x03, 0x10, 0x55} },
3694 { {0x51, 0x08, 0x07, 0x10, 0x54} },
3695 { {0x51, 0x45, 0x03, 0x10, 0x50} },
3696 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
3697 { {0x51, 0x30, 0x03, 0x10, 0x50} },
3698 { {0x51, 0x20, 0x03, 0x10, 0x50} },
3699 { {0x51, 0x10, 0x03, 0x10, 0x50} }
3700 };
3701
3702
3703 static const u8 wl_rssi_step_8822c[] = {60, 50, 44, 30};
3704 static const u8 bt_rssi_step_8822c[] = {8, 15, 20, 25};
3705 static const struct coex_5g_afh_map afh_5g_8822c[] = { {0, 0, 0} };
3706
3707
3708 static const struct coex_rf_para rf_para_tx_8822c[] = {
3709 {0, 0, false, 7},
3710 {0, 16, false, 7},
3711 {8, 17, true, 4},
3712 {7, 18, true, 4},
3713 {6, 19, true, 4},
3714 {5, 20, true, 4}
3715 };
3716
3717 static const struct coex_rf_para rf_para_rx_8822c[] = {
3718 {0, 0, false, 7},
3719 {0, 16, false, 7},
3720 {3, 24, true, 5},
3721 {2, 26, true, 5},
3722 {1, 27, true, 5},
3723 {0, 28, true, 5}
3724 };
3725
3726 static_assert(ARRAY_SIZE(rf_para_tx_8822c) == ARRAY_SIZE(rf_para_rx_8822c));
3727
3728 struct rtw_chip_info rtw8822c_hw_spec = {
3729 .ops = &rtw8822c_ops,
3730 .id = RTW_CHIP_TYPE_8822C,
3731 .fw_name = "rtw88/rtw8822c_fw.bin",
3732 .tx_pkt_desc_sz = 48,
3733 .tx_buf_desc_sz = 16,
3734 .rx_pkt_desc_sz = 24,
3735 .rx_buf_desc_sz = 8,
3736 .phy_efuse_size = 512,
3737 .log_efuse_size = 768,
3738 .ptct_efuse_size = 124,
3739 .txff_size = 262144,
3740 .rxff_size = 24576,
3741 .txgi_factor = 2,
3742 .is_pwr_by_rate_dec = false,
3743 .max_power_index = 0x7f,
3744 .csi_buf_pg_num = 50,
3745 .band = RTW_BAND_2G | RTW_BAND_5G,
3746 .page_size = 128,
3747 .dig_min = 0x20,
3748 .ht_supported = true,
3749 .vht_supported = true,
3750 .sys_func_en = 0xD8,
3751 .pwr_on_seq = card_enable_flow_8822c,
3752 .pwr_off_seq = card_disable_flow_8822c,
3753 .page_table = page_table_8822c,
3754 .rqpn_table = rqpn_table_8822c,
3755 .intf_table = &phy_para_table_8822c,
3756 .dig = rtw8822c_dig,
3757 .rf_base_addr = {0x3c00, 0x4c00},
3758 .rf_sipi_addr = {0x1808, 0x4108},
3759 .mac_tbl = &rtw8822c_mac_tbl,
3760 .agc_tbl = &rtw8822c_agc_tbl,
3761 .bb_tbl = &rtw8822c_bb_tbl,
3762 .rfk_init_tbl = &rtw8822c_array_mp_cal_init_tbl,
3763 .rf_tbl = {&rtw8822c_rf_a_tbl, &rtw8822c_rf_b_tbl},
3764 .rfe_defs = rtw8822c_rfe_defs,
3765 .rfe_defs_size = ARRAY_SIZE(rtw8822c_rfe_defs),
3766 .en_dis_dpd = true,
3767 .dpd_ratemask = DIS_DPD_RATEALL,
3768
3769 .coex_para_ver = 0x19062706,
3770 .bt_desired_ver = 0x6,
3771 .scbd_support = true,
3772 .new_scbd10_def = true,
3773 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF,
3774 .bt_rssi_type = COEX_BTRSSI_DBM,
3775 .ant_isolation = 15,
3776 .rssi_tolerance = 2,
3777 .wl_rssi_step = wl_rssi_step_8822c,
3778 .bt_rssi_step = bt_rssi_step_8822c,
3779 .table_sant_num = ARRAY_SIZE(table_sant_8822c),
3780 .table_sant = table_sant_8822c,
3781 .table_nsant_num = ARRAY_SIZE(table_nsant_8822c),
3782 .table_nsant = table_nsant_8822c,
3783 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8822c),
3784 .tdma_sant = tdma_sant_8822c,
3785 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8822c),
3786 .tdma_nsant = tdma_nsant_8822c,
3787 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8822c),
3788 .wl_rf_para_tx = rf_para_tx_8822c,
3789 .wl_rf_para_rx = rf_para_rx_8822c,
3790 .bt_afh_span_bw20 = 0x24,
3791 .bt_afh_span_bw40 = 0x36,
3792 .afh_5g_num = ARRAY_SIZE(afh_5g_8822c),
3793 .afh_5g = afh_5g_8822c,
3794 };
3795 EXPORT_SYMBOL(rtw8822c_hw_spec);
3796
3797 MODULE_FIRMWARE("rtw88/rtw8822c_fw.bin");