drivers/thermal/mtk

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This source file includes following definitions.
raw_to_mcelsius
mtk_thermal_get_bank
mtk_thermal_put_bank
mtk_thermal_bank_temperature
mtk_read_temp
mtk_thermal_init_bank
of_get_phys_base
mtk_thermal_get_calibration_data
mtk_thermal_probe
mtk_thermal_remove
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015 MediaTek Inc.
   4  * Author: Hanyi Wu <hanyi.wu@mediatek.com>
   5  *         Sascha Hauer <s.hauer@pengutronix.de>
   6  *         Dawei Chien <dawei.chien@mediatek.com>
   7  *         Louis Yu <louis.yu@mediatek.com>
   8  */
   9 
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/nvmem-consumer.h>
  16 #include <linux/of.h>
  17 #include <linux/of_address.h>
  18 #include <linux/of_device.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/slab.h>
  21 #include <linux/io.h>
  22 #include <linux/thermal.h>
  23 #include <linux/reset.h>
  24 #include <linux/types.h>
  25 
  26 /* AUXADC Registers */
  27 #define AUXADC_CON1_SET_V       0x008
  28 #define AUXADC_CON1_CLR_V       0x00c
  29 #define AUXADC_CON2_V           0x010
  30 #define AUXADC_DATA(channel)    (0x14 + (channel) * 4)
  31 
  32 #define APMIXED_SYS_TS_CON1     0x604
  33 
  34 /* Thermal Controller Registers */
  35 #define TEMP_MONCTL0            0x000
  36 #define TEMP_MONCTL1            0x004
  37 #define TEMP_MONCTL2            0x008
  38 #define TEMP_MONIDET0           0x014
  39 #define TEMP_MONIDET1           0x018
  40 #define TEMP_MSRCTL0            0x038
  41 #define TEMP_AHBPOLL            0x040
  42 #define TEMP_AHBTO              0x044
  43 #define TEMP_ADCPNP0            0x048
  44 #define TEMP_ADCPNP1            0x04c
  45 #define TEMP_ADCPNP2            0x050
  46 #define TEMP_ADCPNP3            0x0b4
  47 
  48 #define TEMP_ADCMUX             0x054
  49 #define TEMP_ADCEN              0x060
  50 #define TEMP_PNPMUXADDR         0x064
  51 #define TEMP_ADCMUXADDR         0x068
  52 #define TEMP_ADCENADDR          0x074
  53 #define TEMP_ADCVALIDADDR       0x078
  54 #define TEMP_ADCVOLTADDR        0x07c
  55 #define TEMP_RDCTRL             0x080
  56 #define TEMP_ADCVALIDMASK       0x084
  57 #define TEMP_ADCVOLTAGESHIFT    0x088
  58 #define TEMP_ADCWRITECTRL       0x08c
  59 #define TEMP_MSR0               0x090
  60 #define TEMP_MSR1               0x094
  61 #define TEMP_MSR2               0x098
  62 #define TEMP_MSR3               0x0B8
  63 
  64 #define TEMP_SPARE0             0x0f0
  65 
  66 #define TEMP_ADCPNP0_1          0x148
  67 #define TEMP_ADCPNP1_1          0x14c
  68 #define TEMP_ADCPNP2_1          0x150
  69 #define TEMP_MSR0_1             0x190
  70 #define TEMP_MSR1_1             0x194
  71 #define TEMP_MSR2_1             0x198
  72 #define TEMP_ADCPNP3_1          0x1b4
  73 #define TEMP_MSR3_1             0x1B8
  74 
  75 #define PTPCORESEL              0x400
  76 
  77 #define TEMP_MONCTL1_PERIOD_UNIT(x)     ((x) & 0x3ff)
  78 
  79 #define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16)
  80 #define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff)
  81 
  82 #define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x)       (x)
  83 
  84 #define TEMP_ADCWRITECTRL_ADC_PNP_WRITE         BIT(0)
  85 #define TEMP_ADCWRITECTRL_ADC_MUX_WRITE         BIT(1)
  86 
  87 #define TEMP_ADCVALIDMASK_VALID_HIGH            BIT(5)
  88 #define TEMP_ADCVALIDMASK_VALID_POS(bit)        (bit)
  89 
  90 /* MT8173 thermal sensors */
  91 #define MT8173_TS1      0
  92 #define MT8173_TS2      1
  93 #define MT8173_TS3      2
  94 #define MT8173_TS4      3
  95 #define MT8173_TSABB    4
  96 
  97 /* AUXADC channel 11 is used for the temperature sensors */
  98 #define MT8173_TEMP_AUXADC_CHANNEL      11
  99 
 100 /* The total number of temperature sensors in the MT8173 */
 101 #define MT8173_NUM_SENSORS              5
 102 
 103 /* The number of banks in the MT8173 */
 104 #define MT8173_NUM_ZONES                4
 105 
 106 /* The number of sensing points per bank */
 107 #define MT8173_NUM_SENSORS_PER_ZONE     4
 108 
 109 /* The number of controller in the MT8173 */
 110 #define MT8173_NUM_CONTROLLER           1
 111 
 112 /* The calibration coefficient of sensor  */
 113 #define MT8173_CALIBRATION      165
 114 
 115 /*
 116  * Layout of the fuses providing the calibration data
 117  * These macros could be used for MT8183, MT8173, MT2701, and MT2712.
 118  * MT8183 has 6 sensors and needs 6 VTS calibration data.
 119  * MT8173 has 5 sensors and needs 5 VTS calibration data.
 120  * MT2701 has 3 sensors and needs 3 VTS calibration data.
 121  * MT2712 has 4 sensors and needs 4 VTS calibration data.
 122  */
 123 #define CALIB_BUF0_VALID                BIT(0)
 124 #define CALIB_BUF1_ADC_GE(x)            (((x) >> 22) & 0x3ff)
 125 #define CALIB_BUF0_VTS_TS1(x)           (((x) >> 17) & 0x1ff)
 126 #define CALIB_BUF0_VTS_TS2(x)           (((x) >> 8) & 0x1ff)
 127 #define CALIB_BUF1_VTS_TS3(x)           (((x) >> 0) & 0x1ff)
 128 #define CALIB_BUF2_VTS_TS4(x)           (((x) >> 23) & 0x1ff)
 129 #define CALIB_BUF2_VTS_TS5(x)           (((x) >> 5) & 0x1ff)
 130 #define CALIB_BUF2_VTS_TSABB(x)         (((x) >> 14) & 0x1ff)
 131 #define CALIB_BUF0_DEGC_CALI(x)         (((x) >> 1) & 0x3f)
 132 #define CALIB_BUF0_O_SLOPE(x)           (((x) >> 26) & 0x3f)
 133 #define CALIB_BUF0_O_SLOPE_SIGN(x)      (((x) >> 7) & 0x1)
 134 #define CALIB_BUF1_ID(x)                (((x) >> 9) & 0x1)
 135 
 136 enum {
 137         VTS1,
 138         VTS2,
 139         VTS3,
 140         VTS4,
 141         VTS5,
 142         VTSABB,
 143         MAX_NUM_VTS,
 144 };
 145 
 146 /* MT2701 thermal sensors */
 147 #define MT2701_TS1      0
 148 #define MT2701_TS2      1
 149 #define MT2701_TSABB    2
 150 
 151 /* AUXADC channel 11 is used for the temperature sensors */
 152 #define MT2701_TEMP_AUXADC_CHANNEL      11
 153 
 154 /* The total number of temperature sensors in the MT2701 */
 155 #define MT2701_NUM_SENSORS      3
 156 
 157 /* The number of sensing points per bank */
 158 #define MT2701_NUM_SENSORS_PER_ZONE     3
 159 
 160 /* The number of controller in the MT2701 */
 161 #define MT2701_NUM_CONTROLLER           1
 162 
 163 /* The calibration coefficient of sensor  */
 164 #define MT2701_CALIBRATION      165
 165 
 166 /* MT2712 thermal sensors */
 167 #define MT2712_TS1      0
 168 #define MT2712_TS2      1
 169 #define MT2712_TS3      2
 170 #define MT2712_TS4      3
 171 
 172 /* AUXADC channel 11 is used for the temperature sensors */
 173 #define MT2712_TEMP_AUXADC_CHANNEL      11
 174 
 175 /* The total number of temperature sensors in the MT2712 */
 176 #define MT2712_NUM_SENSORS      4
 177 
 178 /* The number of sensing points per bank */
 179 #define MT2712_NUM_SENSORS_PER_ZONE     4
 180 
 181 /* The number of controller in the MT2712 */
 182 #define MT2712_NUM_CONTROLLER           1
 183 
 184 /* The calibration coefficient of sensor  */
 185 #define MT2712_CALIBRATION      165
 186 
 187 #define MT7622_TEMP_AUXADC_CHANNEL      11
 188 #define MT7622_NUM_SENSORS              1
 189 #define MT7622_NUM_ZONES                1
 190 #define MT7622_NUM_SENSORS_PER_ZONE     1
 191 #define MT7622_TS1      0
 192 #define MT7622_NUM_CONTROLLER           1
 193 
 194 /* The maximum number of banks */
 195 #define MAX_NUM_ZONES           8
 196 
 197 /* The calibration coefficient of sensor  */
 198 #define MT7622_CALIBRATION      165
 199 
 200 /* MT8183 thermal sensors */
 201 #define MT8183_TS1      0
 202 #define MT8183_TS2      1
 203 #define MT8183_TS3      2
 204 #define MT8183_TS4      3
 205 #define MT8183_TS5      4
 206 #define MT8183_TSABB    5
 207 
 208 /* AUXADC channel  is used for the temperature sensors */
 209 #define MT8183_TEMP_AUXADC_CHANNEL      11
 210 
 211 /* The total number of temperature sensors in the MT8183 */
 212 #define MT8183_NUM_SENSORS      6
 213 
 214 /* The number of sensing points per bank */
 215 #define MT8183_NUM_SENSORS_PER_ZONE      6
 216 
 217 /* The number of controller in the MT8183 */
 218 #define MT8183_NUM_CONTROLLER           2
 219 
 220 /* The calibration coefficient of sensor  */
 221 #define MT8183_CALIBRATION      153
 222 
 223 struct mtk_thermal;
 224 
 225 struct thermal_bank_cfg {
 226         unsigned int num_sensors;
 227         const int *sensors;
 228 };
 229 
 230 struct mtk_thermal_bank {
 231         struct mtk_thermal *mt;
 232         int id;
 233 };
 234 
 235 struct mtk_thermal_data {
 236         s32 num_banks;
 237         s32 num_sensors;
 238         s32 auxadc_channel;
 239         const int *vts_index;
 240         const int *sensor_mux_values;
 241         const int *msr;
 242         const int *adcpnp;
 243         const int cali_val;
 244         const int num_controller;
 245         const int *controller_offset;
 246         bool need_switch_bank;
 247         struct thermal_bank_cfg bank_data[MAX_NUM_ZONES];
 248 };
 249 
 250 struct mtk_thermal {
 251         struct device *dev;
 252         void __iomem *thermal_base;
 253 
 254         struct clk *clk_peri_therm;
 255         struct clk *clk_auxadc;
 256         /* lock: for getting and putting banks */
 257         struct mutex lock;
 258 
 259         /* Calibration values */
 260         s32 adc_ge;
 261         s32 degc_cali;
 262         s32 o_slope;
 263         s32 vts[MAX_NUM_VTS];
 264 
 265         const struct mtk_thermal_data *conf;
 266         struct mtk_thermal_bank banks[MAX_NUM_ZONES];
 267 };
 268 
 269 /* MT8183 thermal sensor data */
 270 static const int mt8183_bank_data[MT8183_NUM_SENSORS] = {
 271         MT8183_TS1, MT8183_TS2, MT8183_TS3, MT8183_TS4, MT8183_TS5, MT8183_TSABB
 272 };
 273 
 274 static const int mt8183_msr[MT8183_NUM_SENSORS_PER_ZONE] = {
 275         TEMP_MSR0_1, TEMP_MSR1_1, TEMP_MSR2_1, TEMP_MSR1, TEMP_MSR0, TEMP_MSR3_1
 276 };
 277 
 278 static const int mt8183_adcpnp[MT8183_NUM_SENSORS_PER_ZONE] = {
 279         TEMP_ADCPNP0_1, TEMP_ADCPNP1_1, TEMP_ADCPNP2_1,
 280         TEMP_ADCPNP1, TEMP_ADCPNP0, TEMP_ADCPNP3_1
 281 };
 282 
 283 static const int mt8183_mux_values[MT8183_NUM_SENSORS] = { 0, 1, 2, 3, 4, 0 };
 284 static const int mt8183_tc_offset[MT8183_NUM_CONTROLLER] = {0x0, 0x100};
 285 
 286 static const int mt8183_vts_index[MT8183_NUM_SENSORS] = {
 287         VTS1, VTS2, VTS3, VTS4, VTS5, VTSABB
 288 };
 289 
 290 /* MT8173 thermal sensor data */
 291 static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = {
 292         { MT8173_TS2, MT8173_TS3 },
 293         { MT8173_TS2, MT8173_TS4 },
 294         { MT8173_TS1, MT8173_TS2, MT8173_TSABB },
 295         { MT8173_TS2 },
 296 };
 297 
 298 static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = {
 299         TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
 300 };
 301 
 302 static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = {
 303         TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
 304 };
 305 
 306 static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
 307 static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, };
 308 
 309 static const int mt8173_vts_index[MT8173_NUM_SENSORS] = {
 310         VTS1, VTS2, VTS3, VTS4, VTSABB
 311 };
 312 
 313 /* MT2701 thermal sensor data */
 314 static const int mt2701_bank_data[MT2701_NUM_SENSORS] = {
 315         MT2701_TS1, MT2701_TS2, MT2701_TSABB
 316 };
 317 
 318 static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = {
 319         TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
 320 };
 321 
 322 static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = {
 323         TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
 324 };
 325 
 326 static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 };
 327 static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, };
 328 
 329 static const int mt2701_vts_index[MT2701_NUM_SENSORS] = {
 330         VTS1, VTS2, VTS3
 331 };
 332 
 333 /* MT2712 thermal sensor data */
 334 static const int mt2712_bank_data[MT2712_NUM_SENSORS] = {
 335         MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4
 336 };
 337 
 338 static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = {
 339         TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
 340 };
 341 
 342 static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = {
 343         TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
 344 };
 345 
 346 static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 };
 347 static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, };
 348 
 349 static const int mt2712_vts_index[MT2712_NUM_SENSORS] = {
 350         VTS1, VTS2, VTS3, VTS4
 351 };
 352 
 353 /* MT7622 thermal sensor data */
 354 static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, };
 355 static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
 356 static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
 357 static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, };
 358 static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
 359 static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
 360 
 361 /**
 362  * The MT8173 thermal controller has four banks. Each bank can read up to
 363  * four temperature sensors simultaneously. The MT8173 has a total of 5
 364  * temperature sensors. We use each bank to measure a certain area of the
 365  * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
 366  * areas, hence is used in different banks.
 367  *
 368  * The thermal core only gets the maximum temperature of all banks, so
 369  * the bank concept wouldn't be necessary here. However, the SVS (Smart
 370  * Voltage Scaling) unit makes its decisions based on the same bank
 371  * data, and this indeed needs the temperatures of the individual banks
 372  * for making better decisions.
 373  */
 374 static const struct mtk_thermal_data mt8173_thermal_data = {
 375         .auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL,
 376         .num_banks = MT8173_NUM_ZONES,
 377         .num_sensors = MT8173_NUM_SENSORS,
 378         .vts_index = mt8173_vts_index,
 379         .cali_val = MT8173_CALIBRATION,
 380         .num_controller = MT8173_NUM_CONTROLLER,
 381         .controller_offset = mt8173_tc_offset,
 382         .need_switch_bank = true,
 383         .bank_data = {
 384                 {
 385                         .num_sensors = 2,
 386                         .sensors = mt8173_bank_data[0],
 387                 }, {
 388                         .num_sensors = 2,
 389                         .sensors = mt8173_bank_data[1],
 390                 }, {
 391                         .num_sensors = 3,
 392                         .sensors = mt8173_bank_data[2],
 393                 }, {
 394                         .num_sensors = 1,
 395                         .sensors = mt8173_bank_data[3],
 396                 },
 397         },
 398         .msr = mt8173_msr,
 399         .adcpnp = mt8173_adcpnp,
 400         .sensor_mux_values = mt8173_mux_values,
 401 };
 402 
 403 /**
 404  * The MT2701 thermal controller has one bank, which can read up to
 405  * three temperature sensors simultaneously. The MT2701 has a total of 3
 406  * temperature sensors.
 407  *
 408  * The thermal core only gets the maximum temperature of this one bank,
 409  * so the bank concept wouldn't be necessary here. However, the SVS (Smart
 410  * Voltage Scaling) unit makes its decisions based on the same bank
 411  * data.
 412  */
 413 static const struct mtk_thermal_data mt2701_thermal_data = {
 414         .auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL,
 415         .num_banks = 1,
 416         .num_sensors = MT2701_NUM_SENSORS,
 417         .vts_index = mt2701_vts_index,
 418         .cali_val = MT2701_CALIBRATION,
 419         .num_controller = MT2701_NUM_CONTROLLER,
 420         .controller_offset = mt2701_tc_offset,
 421         .need_switch_bank = true,
 422         .bank_data = {
 423                 {
 424                         .num_sensors = 3,
 425                         .sensors = mt2701_bank_data,
 426                 },
 427         },
 428         .msr = mt2701_msr,
 429         .adcpnp = mt2701_adcpnp,
 430         .sensor_mux_values = mt2701_mux_values,
 431 };
 432 
 433 /**
 434  * The MT2712 thermal controller has one bank, which can read up to
 435  * four temperature sensors simultaneously. The MT2712 has a total of 4
 436  * temperature sensors.
 437  *
 438  * The thermal core only gets the maximum temperature of this one bank,
 439  * so the bank concept wouldn't be necessary here. However, the SVS (Smart
 440  * Voltage Scaling) unit makes its decisions based on the same bank
 441  * data.
 442  */
 443 static const struct mtk_thermal_data mt2712_thermal_data = {
 444         .auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL,
 445         .num_banks = 1,
 446         .num_sensors = MT2712_NUM_SENSORS,
 447         .vts_index = mt2712_vts_index,
 448         .cali_val = MT2712_CALIBRATION,
 449         .num_controller = MT2712_NUM_CONTROLLER,
 450         .controller_offset = mt2712_tc_offset,
 451         .need_switch_bank = true,
 452         .bank_data = {
 453                 {
 454                         .num_sensors = 4,
 455                         .sensors = mt2712_bank_data,
 456                 },
 457         },
 458         .msr = mt2712_msr,
 459         .adcpnp = mt2712_adcpnp,
 460         .sensor_mux_values = mt2712_mux_values,
 461 };
 462 
 463 /*
 464  * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data
 465  * access.
 466  */
 467 static const struct mtk_thermal_data mt7622_thermal_data = {
 468         .auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL,
 469         .num_banks = MT7622_NUM_ZONES,
 470         .num_sensors = MT7622_NUM_SENSORS,
 471         .vts_index = mt7622_vts_index,
 472         .cali_val = MT7622_CALIBRATION,
 473         .num_controller = MT7622_NUM_CONTROLLER,
 474         .controller_offset = mt7622_tc_offset,
 475         .need_switch_bank = true,
 476         .bank_data = {
 477                 {
 478                         .num_sensors = 1,
 479                         .sensors = mt7622_bank_data,
 480                 },
 481         },
 482         .msr = mt7622_msr,
 483         .adcpnp = mt7622_adcpnp,
 484         .sensor_mux_values = mt7622_mux_values,
 485 };
 486 
 487 /**
 488  * The MT8183 thermal controller has one bank for the current SW framework.
 489  * The MT8183 has a total of 6 temperature sensors.
 490  * There are two thermal controller to control the six sensor.
 491  * The first one bind 2 sensor, and the other bind 4 sensors.
 492  * The thermal core only gets the maximum temperature of all sensor, so
 493  * the bank concept wouldn't be necessary here. However, the SVS (Smart
 494  * Voltage Scaling) unit makes its decisions based on the same bank
 495  * data, and this indeed needs the temperatures of the individual banks
 496  * for making better decisions.
 497  */
 498 
 499 static const struct mtk_thermal_data mt8183_thermal_data = {
 500         .auxadc_channel = MT8183_TEMP_AUXADC_CHANNEL,
 501         .num_banks = MT8183_NUM_SENSORS_PER_ZONE,
 502         .num_sensors = MT8183_NUM_SENSORS,
 503         .vts_index = mt8183_vts_index,
 504         .cali_val = MT8183_CALIBRATION,
 505         .num_controller = MT8183_NUM_CONTROLLER,
 506         .controller_offset = mt8183_tc_offset,
 507         .need_switch_bank = false,
 508         .bank_data = {
 509                 {
 510                         .num_sensors = 6,
 511                         .sensors = mt8183_bank_data,
 512                 },
 513         },
 514 
 515         .msr = mt8183_msr,
 516         .adcpnp = mt8183_adcpnp,
 517         .sensor_mux_values = mt8183_mux_values,
 518 };
 519 
 520 /**
 521  * raw_to_mcelsius - convert a raw ADC value to mcelsius
 522  * @mt:         The thermal controller
 523  * @raw:        raw ADC value
 524  *
 525  * This converts the raw ADC value to mcelsius using the SoC specific
 526  * calibration constants
 527  */
 528 static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw)
 529 {
 530         s32 tmp;
 531 
 532         raw &= 0xfff;
 533 
 534         tmp = 203450520 << 3;
 535         tmp /= mt->conf->cali_val + mt->o_slope;
 536         tmp /= 10000 + mt->adc_ge;
 537         tmp *= raw - mt->vts[sensno] - 3350;
 538         tmp >>= 3;
 539 
 540         return mt->degc_cali * 500 - tmp;
 541 }
 542 
 543 /**
 544  * mtk_thermal_get_bank - get bank
 545  * @bank:       The bank
 546  *
 547  * The bank registers are banked, we have to select a bank in the
 548  * PTPCORESEL register to access it.
 549  */
 550 static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
 551 {
 552         struct mtk_thermal *mt = bank->mt;
 553         u32 val;
 554 
 555         if (mt->conf->need_switch_bank) {
 556                 mutex_lock(&mt->lock);
 557 
 558                 val = readl(mt->thermal_base + PTPCORESEL);
 559                 val &= ~0xf;
 560                 val |= bank->id;
 561                 writel(val, mt->thermal_base + PTPCORESEL);
 562         }
 563 }
 564 
 565 /**
 566  * mtk_thermal_put_bank - release bank
 567  * @bank:       The bank
 568  *
 569  * release a bank previously taken with mtk_thermal_get_bank,
 570  */
 571 static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
 572 {
 573         struct mtk_thermal *mt = bank->mt;
 574 
 575         if (mt->conf->need_switch_bank)
 576                 mutex_unlock(&mt->lock);
 577 }
 578 
 579 /**
 580  * mtk_thermal_bank_temperature - get the temperature of a bank
 581  * @bank:       The bank
 582  *
 583  * The temperature of a bank is considered the maximum temperature of
 584  * the sensors associated to the bank.
 585  */
 586 static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
 587 {
 588         struct mtk_thermal *mt = bank->mt;
 589         const struct mtk_thermal_data *conf = mt->conf;
 590         int i, temp = INT_MIN, max = INT_MIN;
 591         u32 raw;
 592 
 593         for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {
 594                 raw = readl(mt->thermal_base +
 595                             conf->msr[conf->bank_data[bank->id].sensors[i]]);
 596 
 597                 temp = raw_to_mcelsius(mt,
 598                                        conf->bank_data[bank->id].sensors[i],
 599                                        raw);
 600 
 601                 /*
 602                  * The first read of a sensor often contains very high bogus
 603                  * temperature value. Filter these out so that the system does
 604                  * not immediately shut down.
 605                  */
 606                 if (temp > 200000)
 607                         temp = 0;
 608 
 609                 if (temp > max)
 610                         max = temp;
 611         }
 612 
 613         return max;
 614 }
 615 
 616 static int mtk_read_temp(void *data, int *temperature)
 617 {
 618         struct mtk_thermal *mt = data;
 619         int i;
 620         int tempmax = INT_MIN;
 621 
 622         for (i = 0; i < mt->conf->num_banks; i++) {
 623                 struct mtk_thermal_bank *bank = &mt->banks[i];
 624 
 625                 mtk_thermal_get_bank(bank);
 626 
 627                 tempmax = max(tempmax, mtk_thermal_bank_temperature(bank));
 628 
 629                 mtk_thermal_put_bank(bank);
 630         }
 631 
 632         *temperature = tempmax;
 633 
 634         return 0;
 635 }
 636 
 637 static const struct thermal_zone_of_device_ops mtk_thermal_ops = {
 638         .get_temp = mtk_read_temp,
 639 };
 640 
 641 static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
 642                                   u32 apmixed_phys_base, u32 auxadc_phys_base,
 643                                   int ctrl_id)
 644 {
 645         struct mtk_thermal_bank *bank = &mt->banks[num];
 646         const struct mtk_thermal_data *conf = mt->conf;
 647         int i;
 648 
 649         int offset = mt->conf->controller_offset[ctrl_id];
 650         void __iomem *controller_base = mt->thermal_base + offset;
 651 
 652         bank->id = num;
 653         bank->mt = mt;
 654 
 655         mtk_thermal_get_bank(bank);
 656 
 657         /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
 658         writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1);
 659 
 660         /*
 661          * filt interval is 1 * 46.540us = 46.54us,
 662          * sen interval is 429 * 46.540us = 19.96ms
 663          */
 664         writel(TEMP_MONCTL2_FILTER_INTERVAL(1) |
 665                         TEMP_MONCTL2_SENSOR_INTERVAL(429),
 666                         controller_base + TEMP_MONCTL2);
 667 
 668         /* poll is set to 10u */
 669         writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
 670                controller_base + TEMP_AHBPOLL);
 671 
 672         /* temperature sampling control, 1 sample */
 673         writel(0x0, controller_base + TEMP_MSRCTL0);
 674 
 675         /* exceed this polling time, IRQ would be inserted */
 676         writel(0xffffffff, controller_base + TEMP_AHBTO);
 677 
 678         /* number of interrupts per event, 1 is enough */
 679         writel(0x0, controller_base + TEMP_MONIDET0);
 680         writel(0x0, controller_base + TEMP_MONIDET1);
 681 
 682         /*
 683          * The MT8173 thermal controller does not have its own ADC. Instead it
 684          * uses AHB bus accesses to control the AUXADC. To do this the thermal
 685          * controller has to be programmed with the physical addresses of the
 686          * AUXADC registers and with the various bit positions in the AUXADC.
 687          * Also the thermal controller controls a mux in the APMIXEDSYS register
 688          * space.
 689          */
 690 
 691         /*
 692          * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
 693          * automatically by hw
 694          */
 695         writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX);
 696 
 697         /* AHB address for auxadc mux selection */
 698         writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
 699                controller_base + TEMP_ADCMUXADDR);
 700 
 701         /* AHB address for pnp sensor mux selection */
 702         writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
 703                controller_base + TEMP_PNPMUXADDR);
 704 
 705         /* AHB value for auxadc enable */
 706         writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN);
 707 
 708         /* AHB address for auxadc enable (channel 0 immediate mode selected) */
 709         writel(auxadc_phys_base + AUXADC_CON1_SET_V,
 710                controller_base + TEMP_ADCENADDR);
 711 
 712         /* AHB address for auxadc valid bit */
 713         writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
 714                controller_base + TEMP_ADCVALIDADDR);
 715 
 716         /* AHB address for auxadc voltage output */
 717         writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
 718                controller_base + TEMP_ADCVOLTADDR);
 719 
 720         /* read valid & voltage are at the same register */
 721         writel(0x0, controller_base + TEMP_RDCTRL);
 722 
 723         /* indicate where the valid bit is */
 724         writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
 725                controller_base + TEMP_ADCVALIDMASK);
 726 
 727         /* no shift */
 728         writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT);
 729 
 730         /* enable auxadc mux write transaction */
 731         writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
 732                 controller_base + TEMP_ADCWRITECTRL);
 733 
 734         for (i = 0; i < conf->bank_data[num].num_sensors; i++)
 735                 writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]],
 736                        mt->thermal_base +
 737                        conf->adcpnp[conf->bank_data[num].sensors[i]]);
 738 
 739         writel((1 << conf->bank_data[num].num_sensors) - 1,
 740                controller_base + TEMP_MONCTL0);
 741 
 742         writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
 743                TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
 744                controller_base + TEMP_ADCWRITECTRL);
 745 
 746         mtk_thermal_put_bank(bank);
 747 }
 748 
 749 static u64 of_get_phys_base(struct device_node *np)
 750 {
 751         u64 size64;
 752         const __be32 *regaddr_p;
 753 
 754         regaddr_p = of_get_address(np, 0, &size64, NULL);
 755         if (!regaddr_p)
 756                 return OF_BAD_ADDR;
 757 
 758         return of_translate_address(np, regaddr_p);
 759 }
 760 
 761 static int mtk_thermal_get_calibration_data(struct device *dev,
 762                                             struct mtk_thermal *mt)
 763 {
 764         struct nvmem_cell *cell;
 765         u32 *buf;
 766         size_t len;
 767         int i, ret = 0;
 768 
 769         /* Start with default values */
 770         mt->adc_ge = 512;
 771         for (i = 0; i < mt->conf->num_sensors; i++)
 772                 mt->vts[i] = 260;
 773         mt->degc_cali = 40;
 774         mt->o_slope = 0;
 775 
 776         cell = nvmem_cell_get(dev, "calibration-data");
 777         if (IS_ERR(cell)) {
 778                 if (PTR_ERR(cell) == -EPROBE_DEFER)
 779                         return PTR_ERR(cell);
 780                 return 0;
 781         }
 782 
 783         buf = (u32 *)nvmem_cell_read(cell, &len);
 784 
 785         nvmem_cell_put(cell);
 786 
 787         if (IS_ERR(buf))
 788                 return PTR_ERR(buf);
 789 
 790         if (len < 3 * sizeof(u32)) {
 791                 dev_warn(dev, "invalid calibration data\n");
 792                 ret = -EINVAL;
 793                 goto out;
 794         }
 795 
 796         if (buf[0] & CALIB_BUF0_VALID) {
 797                 mt->adc_ge = CALIB_BUF1_ADC_GE(buf[1]);
 798 
 799                 for (i = 0; i < mt->conf->num_sensors; i++) {
 800                         switch (mt->conf->vts_index[i]) {
 801                         case VTS1:
 802                                 mt->vts[VTS1] = CALIB_BUF0_VTS_TS1(buf[0]);
 803                                 break;
 804                         case VTS2:
 805                                 mt->vts[VTS2] = CALIB_BUF0_VTS_TS2(buf[0]);
 806                                 break;
 807                         case VTS3:
 808                                 mt->vts[VTS3] = CALIB_BUF1_VTS_TS3(buf[1]);
 809                                 break;
 810                         case VTS4:
 811                                 mt->vts[VTS4] = CALIB_BUF2_VTS_TS4(buf[2]);
 812                                 break;
 813                         case VTS5:
 814                                 mt->vts[VTS5] = CALIB_BUF2_VTS_TS5(buf[2]);
 815                                 break;
 816                         case VTSABB:
 817                                 mt->vts[VTSABB] = CALIB_BUF2_VTS_TSABB(buf[2]);
 818                                 break;
 819                         default:
 820                                 break;
 821                         }
 822                 }
 823 
 824                 mt->degc_cali = CALIB_BUF0_DEGC_CALI(buf[0]);
 825                 if (CALIB_BUF1_ID(buf[1]) &
 826                     CALIB_BUF0_O_SLOPE_SIGN(buf[0]))
 827                         mt->o_slope = -CALIB_BUF0_O_SLOPE(buf[0]);
 828                 else
 829                         mt->o_slope = CALIB_BUF0_O_SLOPE(buf[0]);
 830         } else {
 831                 dev_info(dev, "Device not calibrated, using default calibration values\n");
 832         }
 833 
 834 out:
 835         kfree(buf);
 836 
 837         return ret;
 838 }
 839 
 840 static const struct of_device_id mtk_thermal_of_match[] = {
 841         {
 842                 .compatible = "mediatek,mt8173-thermal",
 843                 .data = (void *)&mt8173_thermal_data,
 844         },
 845         {
 846                 .compatible = "mediatek,mt2701-thermal",
 847                 .data = (void *)&mt2701_thermal_data,
 848         },
 849         {
 850                 .compatible = "mediatek,mt2712-thermal",
 851                 .data = (void *)&mt2712_thermal_data,
 852         },
 853         {
 854                 .compatible = "mediatek,mt7622-thermal",
 855                 .data = (void *)&mt7622_thermal_data,
 856         },
 857         {
 858                 .compatible = "mediatek,mt8183-thermal",
 859                 .data = (void *)&mt8183_thermal_data,
 860         }, {
 861         },
 862 };
 863 MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
 864 
 865 static int mtk_thermal_probe(struct platform_device *pdev)
 866 {
 867         int ret, i, ctrl_id;
 868         struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
 869         struct mtk_thermal *mt;
 870         struct resource *res;
 871         u64 auxadc_phys_base, apmixed_phys_base;
 872         struct thermal_zone_device *tzdev;
 873 
 874         mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
 875         if (!mt)
 876                 return -ENOMEM;
 877 
 878         mt->conf = of_device_get_match_data(&pdev->dev);
 879 
 880         mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
 881         if (IS_ERR(mt->clk_peri_therm))
 882                 return PTR_ERR(mt->clk_peri_therm);
 883 
 884         mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
 885         if (IS_ERR(mt->clk_auxadc))
 886                 return PTR_ERR(mt->clk_auxadc);
 887 
 888         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 889         mt->thermal_base = devm_ioremap_resource(&pdev->dev, res);
 890         if (IS_ERR(mt->thermal_base))
 891                 return PTR_ERR(mt->thermal_base);
 892 
 893         ret = mtk_thermal_get_calibration_data(&pdev->dev, mt);
 894         if (ret)
 895                 return ret;
 896 
 897         mutex_init(&mt->lock);
 898 
 899         mt->dev = &pdev->dev;
 900 
 901         auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);
 902         if (!auxadc) {
 903                 dev_err(&pdev->dev, "missing auxadc node\n");
 904                 return -ENODEV;
 905         }
 906 
 907         auxadc_phys_base = of_get_phys_base(auxadc);
 908 
 909         of_node_put(auxadc);
 910 
 911         if (auxadc_phys_base == OF_BAD_ADDR) {
 912                 dev_err(&pdev->dev, "Can't get auxadc phys address\n");
 913                 return -EINVAL;
 914         }
 915 
 916         apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0);
 917         if (!apmixedsys) {
 918                 dev_err(&pdev->dev, "missing apmixedsys node\n");
 919                 return -ENODEV;
 920         }
 921 
 922         apmixed_phys_base = of_get_phys_base(apmixedsys);
 923 
 924         of_node_put(apmixedsys);
 925 
 926         if (apmixed_phys_base == OF_BAD_ADDR) {
 927                 dev_err(&pdev->dev, "Can't get auxadc phys address\n");
 928                 return -EINVAL;
 929         }
 930 
 931         ret = device_reset(&pdev->dev);
 932         if (ret)
 933                 return ret;
 934 
 935         ret = clk_prepare_enable(mt->clk_auxadc);
 936         if (ret) {
 937                 dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
 938                 return ret;
 939         }
 940 
 941         ret = clk_prepare_enable(mt->clk_peri_therm);
 942         if (ret) {
 943                 dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
 944                 goto err_disable_clk_auxadc;
 945         }
 946 
 947         for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
 948                 for (i = 0; i < mt->conf->num_banks; i++)
 949                         mtk_thermal_init_bank(mt, i, apmixed_phys_base,
 950                                               auxadc_phys_base, ctrl_id);
 951 
 952         platform_set_drvdata(pdev, mt);
 953 
 954         tzdev = devm_thermal_zone_of_sensor_register(&pdev->dev, 0, mt,
 955                                                      &mtk_thermal_ops);
 956         if (IS_ERR(tzdev)) {
 957                 ret = PTR_ERR(tzdev);
 958                 goto err_disable_clk_peri_therm;
 959         }
 960 
 961         return 0;
 962 
 963 err_disable_clk_peri_therm:
 964         clk_disable_unprepare(mt->clk_peri_therm);
 965 err_disable_clk_auxadc:
 966         clk_disable_unprepare(mt->clk_auxadc);
 967 
 968         return ret;
 969 }
 970 
 971 static int mtk_thermal_remove(struct platform_device *pdev)
 972 {
 973         struct mtk_thermal *mt = platform_get_drvdata(pdev);
 974 
 975         clk_disable_unprepare(mt->clk_peri_therm);
 976         clk_disable_unprepare(mt->clk_auxadc);
 977 
 978         return 0;
 979 }
 980 
 981 static struct platform_driver mtk_thermal_driver = {
 982         .probe = mtk_thermal_probe,
 983         .remove = mtk_thermal_remove,
 984         .driver = {
 985                 .name = "mtk-thermal",
 986                 .of_match_table = mtk_thermal_of_match,
 987         },
 988 };
 989 
 990 module_platform_driver(mtk_thermal_driver);
 991 
 992 MODULE_AUTHOR("Michael Kao <michael.kao@mediatek.com>");
 993 MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>");
 994 MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>");
 995 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
 996 MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>");
 997 MODULE_DESCRIPTION("Mediatek thermal driver");
 998 MODULE_LICENSE("GPL v2");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/thermal/mtk_thermal.c

DEFINITIONS
