This source file includes following definitions.
- tf_generic_smc
- tf_set_cpu_boot_addr
- tf_prepare_idle
- tf_cache_write_sec
- tf_init_cache
- register_trusted_foundations
- of_register_trusted_foundations
- trusted_foundations_registered
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8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/of.h>
11
12 #include <linux/firmware/trusted_foundations.h>
13
14 #include <asm/firmware.h>
15 #include <asm/hardware/cache-l2x0.h>
16 #include <asm/outercache.h>
17
18 #define TF_CACHE_MAINT 0xfffff100
19
20 #define TF_CACHE_ENABLE 1
21 #define TF_CACHE_DISABLE 2
22
23 #define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200
24
25 #define TF_CPU_PM 0xfffffffc
26 #define TF_CPU_PM_S3 0xffffffe3
27 #define TF_CPU_PM_S2 0xffffffe6
28 #define TF_CPU_PM_S2_NO_MC_CLK 0xffffffe5
29 #define TF_CPU_PM_S1 0xffffffe4
30 #define TF_CPU_PM_S1_NOFLUSH_L2 0xffffffe7
31
32 static unsigned long cpu_boot_addr;
33
34 static void tf_generic_smc(u32 type, u32 arg1, u32 arg2)
35 {
36 register u32 r0 asm("r0") = type;
37 register u32 r1 asm("r1") = arg1;
38 register u32 r2 asm("r2") = arg2;
39
40 asm volatile(
41 ".arch_extension sec\n\t"
42 "stmfd sp!, {r4 - r11}\n\t"
43 __asmeq("%0", "r0")
44 __asmeq("%1", "r1")
45 __asmeq("%2", "r2")
46 "mov r3, #0\n\t"
47 "mov r4, #0\n\t"
48 "smc #0\n\t"
49 "ldmfd sp!, {r4 - r11}\n\t"
50 :
51 : "r" (r0), "r" (r1), "r" (r2)
52 : "memory", "r3", "r12", "lr");
53 }
54
55 static int tf_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
56 {
57 cpu_boot_addr = boot_addr;
58 tf_generic_smc(TF_SET_CPU_BOOT_ADDR_SMC, cpu_boot_addr, 0);
59
60 return 0;
61 }
62
63 static int tf_prepare_idle(unsigned long mode)
64 {
65 switch (mode) {
66 case TF_PM_MODE_LP0:
67 tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S3, cpu_boot_addr);
68 break;
69
70 case TF_PM_MODE_LP1:
71 tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S2, cpu_boot_addr);
72 break;
73
74 case TF_PM_MODE_LP1_NO_MC_CLK:
75 tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S2_NO_MC_CLK,
76 cpu_boot_addr);
77 break;
78
79 case TF_PM_MODE_LP2:
80 tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S1, cpu_boot_addr);
81 break;
82
83 case TF_PM_MODE_LP2_NOFLUSH_L2:
84 tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S1_NOFLUSH_L2,
85 cpu_boot_addr);
86 break;
87
88 default:
89 return -EINVAL;
90 }
91
92 return 0;
93 }
94
95 #ifdef CONFIG_CACHE_L2X0
96 static void tf_cache_write_sec(unsigned long val, unsigned int reg)
97 {
98 u32 l2x0_way_mask = 0xff;
99
100 switch (reg) {
101 case L2X0_CTRL:
102 if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_ASSOCIATIVITY_16)
103 l2x0_way_mask = 0xffff;
104
105 if (val == L2X0_CTRL_EN)
106 tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_ENABLE,
107 l2x0_saved_regs.aux_ctrl);
108 else
109 tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_DISABLE,
110 l2x0_way_mask);
111 break;
112
113 default:
114 break;
115 }
116 }
117
118 static int tf_init_cache(void)
119 {
120 outer_cache.write_sec = tf_cache_write_sec;
121
122 return 0;
123 }
124 #endif
125
126 static const struct firmware_ops trusted_foundations_ops = {
127 .set_cpu_boot_addr = tf_set_cpu_boot_addr,
128 .prepare_idle = tf_prepare_idle,
129 #ifdef CONFIG_CACHE_L2X0
130 .l2x0_init = tf_init_cache,
131 #endif
132 };
133
134 void register_trusted_foundations(struct trusted_foundations_platform_data *pd)
135 {
136
137
138
139
140 register_firmware_ops(&trusted_foundations_ops);
141 }
142
143 void of_register_trusted_foundations(void)
144 {
145 struct device_node *node;
146 struct trusted_foundations_platform_data pdata;
147 int err;
148
149 node = of_find_compatible_node(NULL, NULL, "tlm,trusted-foundations");
150 if (!node)
151 return;
152
153 err = of_property_read_u32(node, "tlm,version-major",
154 &pdata.version_major);
155 if (err != 0)
156 panic("Trusted Foundation: missing version-major property\n");
157 err = of_property_read_u32(node, "tlm,version-minor",
158 &pdata.version_minor);
159 if (err != 0)
160 panic("Trusted Foundation: missing version-minor property\n");
161 register_trusted_foundations(&pdata);
162 }
163
164 bool trusted_foundations_registered(void)
165 {
166 return firmware_ops == &trusted_foundations_ops;
167 }