root/arch/microblaze/pci/xilinx_pci.c

DEFINITIONS

1. xilinx_pci_fixup_bridge
2. xilinx_pci_exclude_device
3. xilinx_early_pci_scan
4. xilinx_early_pci_scan
5. xilinx_pci_init

   1 /*
   2  * PCI support for Xilinx plbv46_pci soft-core which can be used on
   3  * Xilinx Virtex ML410 / ML510 boards.
   4  *
   5  * Copyright 2009 Roderick Colenbrander
   6  * Copyright 2009 Secret Lab Technologies Ltd.
   7  *
   8  * The pci bridge fixup code was copied from ppc4xx_pci.c and was written
   9  * by Benjamin Herrenschmidt.
  10  * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
  11  *
  12  * This file is licensed under the terms of the GNU General Public License
  13  * version 2. This program is licensed "as is" without any warranty of any
  14  * kind, whether express or implied.
  15  */
  16 
  17 #include <linux/ioport.h>
  18 #include <linux/of.h>
  19 #include <linux/of_address.h>
  20 #include <linux/pci.h>
  21 #include <linux/io.h>
  22 
  23 #define XPLB_PCI_ADDR 0x10c
  24 #define XPLB_PCI_DATA 0x110
  25 #define XPLB_PCI_BUS  0x114
  26 
  27 #define PCI_HOST_ENABLE_CMD (PCI_COMMAND_SERR | PCI_COMMAND_PARITY | \
  28                                 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY)
  29 
  30 static struct of_device_id xilinx_pci_match[] = {
  31         { .compatible = "xlnx,plbv46-pci-1.03.a", },
  32         {}
  33 };
  34 
  35 /**
  36  * xilinx_pci_fixup_bridge - Block Xilinx PHB configuration.
  37  */
  38 static void xilinx_pci_fixup_bridge(struct pci_dev *dev)
  39 {
  40         struct pci_controller *hose;
  41         int i;
  42 
  43         if (dev->devfn || dev->bus->self)
  44                 return;
  45 
  46         hose = pci_bus_to_host(dev->bus);
  47         if (!hose)
  48                 return;
  49 
  50         if (!of_match_node(xilinx_pci_match, hose->dn))
  51                 return;
  52 
  53         /* Hide the PCI host BARs from the kernel as their content doesn't
  54          * fit well in the resource management
  55          */
  56         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
  57                 dev->resource[i].start = 0;
  58                 dev->resource[i].end = 0;
  59                 dev->resource[i].flags = 0;
  60         }
  61 
  62         dev_info(&dev->dev, "Hiding Xilinx plb-pci host bridge resources %s\n",
  63                  pci_name(dev));
  64 }
  65 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, xilinx_pci_fixup_bridge);
  66 
  67 #ifdef DEBUG
  68 /**
  69  * xilinx_pci_exclude_device - Don't do config access for non-root bus
  70  *
  71  * This is a hack.  Config access to any bus other than bus 0 does not
  72  * currently work on the ML510 so we prevent it here.
  73  */
  74 static int
  75 xilinx_pci_exclude_device(struct pci_controller *hose, u_char bus, u8 devfn)
  76 {
  77         return (bus != 0);
  78 }
  79 
  80 /**
  81  * xilinx_early_pci_scan - List pci config space for available devices
  82  *
  83  * List pci devices in very early phase.
  84  */
  85 static void __init xilinx_early_pci_scan(struct pci_controller *hose)
  86 {
  87         u32 bus = 0;
  88         u32 val, dev, func, offset;
  89 
  90         /* Currently we have only 2 device connected - up-to 32 devices */
  91         for (dev = 0; dev < 2; dev++) {
  92                 /* List only first function number - up-to 8 functions */
  93                 for (func = 0; func < 1; func++) {
  94                         pr_info("%02x:%02x:%02x", bus, dev, func);
  95                         /* read the first 64 standardized bytes */
  96                         /* Up-to 192 bytes can be list of capabilities */
  97                         for (offset = 0; offset < 64; offset += 4) {
  98                                 early_read_config_dword(hose, bus,
  99                                         PCI_DEVFN(dev, func), offset, &val);
 100                                 if (offset == 0 && val == 0xFFFFFFFF) {
 101                                         pr_cont("\nABSENT");
 102                                         break;
 103                                 }
 104                                 if (!(offset % 0x10))
 105                                         pr_cont("\n%04x:    ", offset);
 106 
 107                                 pr_cont("%08x  ", val);
 108                         }
 109                         pr_info("\n");
 110                 }
 111         }
 112 }
 113 #else
 114 static void __init xilinx_early_pci_scan(struct pci_controller *hose)
 115 {
 116 }
 117 #endif
 118 
 119 /**
 120  * xilinx_pci_init - Find and register a Xilinx PCI host bridge
 121  */
 122 void __init xilinx_pci_init(void)
 123 {
 124         struct pci_controller *hose;
 125         struct resource r;
 126         void __iomem *pci_reg;
 127         struct device_node *pci_node;
 128 
 129         pci_node = of_find_matching_node(NULL, xilinx_pci_match);
 130         if (!pci_node)
 131                 return;
 132 
 133         if (of_address_to_resource(pci_node, 0, &r)) {
 134                 pr_err("xilinx-pci: cannot resolve base address\n");
 135                 return;
 136         }
 137 
 138         hose = pcibios_alloc_controller(pci_node);
 139         if (!hose) {
 140                 pr_err("xilinx-pci: pcibios_alloc_controller() failed\n");
 141                 return;
 142         }
 143 
 144         /* Setup config space */
 145         setup_indirect_pci(hose, r.start + XPLB_PCI_ADDR,
 146                            r.start + XPLB_PCI_DATA,
 147                            INDIRECT_TYPE_SET_CFG_TYPE);
 148 
 149         /* According to the xilinx plbv46_pci documentation the soft-core starts
 150          * a self-init when the bus master enable bit is set. Without this bit
 151          * set the pci bus can't be scanned.
 152          */
 153         early_write_config_word(hose, 0, 0, PCI_COMMAND, PCI_HOST_ENABLE_CMD);
 154 
 155         /* Set the max latency timer to 255 */
 156         early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0xff);
 157 
 158         /* Set the max bus number to 255, and bus/subbus no's to 0 */
 159         pci_reg = of_iomap(pci_node, 0);
 160         WARN_ON(!pci_reg);
 161         out_be32(pci_reg + XPLB_PCI_BUS, 0x000000ff);
 162         iounmap(pci_reg);
 163 
 164         /* Register the host bridge with the linux kernel! */
 165         pci_process_bridge_OF_ranges(hose, pci_node,
 166                                         INDIRECT_TYPE_SET_CFG_TYPE);
 167 
 168         pr_info("xilinx-pci: Registered PCI host bridge\n");
 169         xilinx_early_pci_scan(hose);
 170 }