This source file includes following definitions.
- cpu0_node_has_opp_v2_prop
- cpufreq_dt_platdev_init
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6
7 #include <linux/err.h>
8 #include <linux/of.h>
9 #include <linux/of_device.h>
10 #include <linux/platform_device.h>
11
12 #include "cpufreq-dt.h"
13
14
15
16
17
18 static const struct of_device_id whitelist[] __initconst = {
19 { .compatible = "allwinner,sun4i-a10", },
20 { .compatible = "allwinner,sun5i-a10s", },
21 { .compatible = "allwinner,sun5i-a13", },
22 { .compatible = "allwinner,sun5i-r8", },
23 { .compatible = "allwinner,sun6i-a31", },
24 { .compatible = "allwinner,sun6i-a31s", },
25 { .compatible = "allwinner,sun7i-a20", },
26 { .compatible = "allwinner,sun8i-a23", },
27 { .compatible = "allwinner,sun8i-a83t", },
28 { .compatible = "allwinner,sun8i-h3", },
29
30 { .compatible = "apm,xgene-shadowcat", },
31
32 { .compatible = "arm,integrator-ap", },
33 { .compatible = "arm,integrator-cp", },
34
35 { .compatible = "hisilicon,hi3660", },
36
37 { .compatible = "fsl,imx27", },
38 { .compatible = "fsl,imx51", },
39 { .compatible = "fsl,imx53", },
40
41 { .compatible = "marvell,berlin", },
42 { .compatible = "marvell,pxa250", },
43 { .compatible = "marvell,pxa270", },
44
45 { .compatible = "samsung,exynos3250", },
46 { .compatible = "samsung,exynos4210", },
47 { .compatible = "samsung,exynos5250", },
48 #ifndef CONFIG_BL_SWITCHER
49 { .compatible = "samsung,exynos5800", },
50 #endif
51
52 { .compatible = "renesas,emev2", },
53 { .compatible = "renesas,r7s72100", },
54 { .compatible = "renesas,r8a73a4", },
55 { .compatible = "renesas,r8a7740", },
56 { .compatible = "renesas,r8a7743", },
57 { .compatible = "renesas,r8a7744", },
58 { .compatible = "renesas,r8a7745", },
59 { .compatible = "renesas,r8a7778", },
60 { .compatible = "renesas,r8a7779", },
61 { .compatible = "renesas,r8a7790", },
62 { .compatible = "renesas,r8a7791", },
63 { .compatible = "renesas,r8a7792", },
64 { .compatible = "renesas,r8a7793", },
65 { .compatible = "renesas,r8a7794", },
66 { .compatible = "renesas,sh73a0", },
67
68 { .compatible = "rockchip,rk2928", },
69 { .compatible = "rockchip,rk3036", },
70 { .compatible = "rockchip,rk3066a", },
71 { .compatible = "rockchip,rk3066b", },
72 { .compatible = "rockchip,rk3188", },
73 { .compatible = "rockchip,rk3228", },
74 { .compatible = "rockchip,rk3288", },
75 { .compatible = "rockchip,rk3328", },
76 { .compatible = "rockchip,rk3366", },
77 { .compatible = "rockchip,rk3368", },
78 { .compatible = "rockchip,rk3399",
79 .data = &(struct cpufreq_dt_platform_data)
80 { .have_governor_per_policy = true, },
81 },
82
83 { .compatible = "st-ericsson,u8500", },
84 { .compatible = "st-ericsson,u8540", },
85 { .compatible = "st-ericsson,u9500", },
86 { .compatible = "st-ericsson,u9540", },
87
88 { .compatible = "ti,omap2", },
89 { .compatible = "ti,omap3", },
90 { .compatible = "ti,omap4", },
91 { .compatible = "ti,omap5", },
92
93 { .compatible = "xlnx,zynq-7000", },
94 { .compatible = "xlnx,zynqmp", },
95
96 { }
97 };
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99
100
101
102
103 static const struct of_device_id blacklist[] __initconst = {
104 { .compatible = "allwinner,sun50i-h6", },
105
106 { .compatible = "calxeda,highbank", },
107 { .compatible = "calxeda,ecx-2000", },
108
109 { .compatible = "fsl,imx7d", },
110 { .compatible = "fsl,imx8mq", },
111 { .compatible = "fsl,imx8mm", },
112 { .compatible = "fsl,imx8mn", },
113
114 { .compatible = "marvell,armadaxp", },
115
116 { .compatible = "mediatek,mt2701", },
117 { .compatible = "mediatek,mt2712", },
118 { .compatible = "mediatek,mt7622", },
119 { .compatible = "mediatek,mt7623", },
120 { .compatible = "mediatek,mt817x", },
121 { .compatible = "mediatek,mt8173", },
122 { .compatible = "mediatek,mt8176", },
123 { .compatible = "mediatek,mt8183", },
124
125 { .compatible = "nvidia,tegra124", },
126 { .compatible = "nvidia,tegra210", },
127
128 { .compatible = "qcom,apq8096", },
129 { .compatible = "qcom,msm8996", },
130 { .compatible = "qcom,qcs404", },
131
132 { .compatible = "st,stih407", },
133 { .compatible = "st,stih410", },
134
135 { .compatible = "sigma,tango4", },
136
137 { .compatible = "ti,am33xx", },
138 { .compatible = "ti,am43", },
139 { .compatible = "ti,dra7", },
140
141 { }
142 };
143
144 static bool __init cpu0_node_has_opp_v2_prop(void)
145 {
146 struct device_node *np = of_cpu_device_node_get(0);
147 bool ret = false;
148
149 if (of_get_property(np, "operating-points-v2", NULL))
150 ret = true;
151
152 of_node_put(np);
153 return ret;
154 }
155
156 static int __init cpufreq_dt_platdev_init(void)
157 {
158 struct device_node *np = of_find_node_by_path("/");
159 const struct of_device_id *match;
160 const void *data = NULL;
161
162 if (!np)
163 return -ENODEV;
164
165 match = of_match_node(whitelist, np);
166 if (match) {
167 data = match->data;
168 goto create_pdev;
169 }
170
171 if (cpu0_node_has_opp_v2_prop() && !of_match_node(blacklist, np))
172 goto create_pdev;
173
174 of_node_put(np);
175 return -ENODEV;
176
177 create_pdev:
178 of_node_put(np);
179 return PTR_ERR_OR_ZERO(platform_device_register_data(NULL, "cpufreq-dt",
180 -1, data,
181 sizeof(struct cpufreq_dt_platform_data)));
182 }
183 device_initcall(cpufreq_dt_platdev_init);