drivers/cpufreq/maple-cpufreq.c

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This source file includes following definitions.
maple_scom_switch_freq
maple_scom_query_freq
maple_cpufreq_target
maple_cpufreq_get_speed
maple_cpufreq_cpu_init
maple_cpufreq_init
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  Copyright (C) 2011 Dmitry Eremin-Solenikov
   4  *  Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
   5  *  and                       Markus Demleitner <msdemlei@cl.uni-heidelberg.de>
   6  *
   7  * This driver adds basic cpufreq support for SMU & 970FX based G5 Macs,
   8  * that is iMac G5 and latest single CPU desktop.
   9  */
  10 
  11 #undef DEBUG
  12 
  13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  14 
  15 #include <linux/module.h>
  16 #include <linux/types.h>
  17 #include <linux/errno.h>
  18 #include <linux/kernel.h>
  19 #include <linux/delay.h>
  20 #include <linux/sched.h>
  21 #include <linux/cpufreq.h>
  22 #include <linux/init.h>
  23 #include <linux/completion.h>
  24 #include <linux/mutex.h>
  25 #include <linux/time.h>
  26 #include <linux/of_device.h>
  27 
  28 #define DBG(fmt...) pr_debug(fmt)
  29 
  30 /* see 970FX user manual */
  31 
  32 #define SCOM_PCR 0x0aa001                       /* PCR scom addr */
  33 
  34 #define PCR_HILO_SELECT         0x80000000U     /* 1 = PCR, 0 = PCRH */
  35 #define PCR_SPEED_FULL          0x00000000U     /* 1:1 speed value */
  36 #define PCR_SPEED_HALF          0x00020000U     /* 1:2 speed value */
  37 #define PCR_SPEED_QUARTER       0x00040000U     /* 1:4 speed value */
  38 #define PCR_SPEED_MASK          0x000e0000U     /* speed mask */
  39 #define PCR_SPEED_SHIFT         17
  40 #define PCR_FREQ_REQ_VALID      0x00010000U     /* freq request valid */
  41 #define PCR_VOLT_REQ_VALID      0x00008000U     /* volt request valid */
  42 #define PCR_TARGET_TIME_MASK    0x00006000U     /* target time */
  43 #define PCR_STATLAT_MASK        0x00001f00U     /* STATLAT value */
  44 #define PCR_SNOOPLAT_MASK       0x000000f0U     /* SNOOPLAT value */
  45 #define PCR_SNOOPACC_MASK       0x0000000fU     /* SNOOPACC value */
  46 
  47 #define SCOM_PSR 0x408001                       /* PSR scom addr */
  48 /* warning: PSR is a 64 bits register */
  49 #define PSR_CMD_RECEIVED        0x2000000000000000U   /* command received */
  50 #define PSR_CMD_COMPLETED       0x1000000000000000U   /* command completed */
  51 #define PSR_CUR_SPEED_MASK      0x0300000000000000U   /* current speed */
  52 #define PSR_CUR_SPEED_SHIFT     (56)
  53 
  54 /*
  55  * The G5 only supports two frequencies (Quarter speed is not supported)
  56  */
  57 #define CPUFREQ_HIGH                  0
  58 #define CPUFREQ_LOW                   1
  59 
  60 static struct cpufreq_frequency_table maple_cpu_freqs[] = {
  61         {0, CPUFREQ_HIGH,               0},
  62         {0, CPUFREQ_LOW,                0},
  63         {0, 0,                          CPUFREQ_TABLE_END},
  64 };
  65 
  66 /* Power mode data is an array of the 32 bits PCR values to use for
  67  * the various frequencies, retrieved from the device-tree
  68  */
  69 static int maple_pmode_cur;
  70 
  71 static const u32 *maple_pmode_data;
  72 static int maple_pmode_max;
  73 
  74 /*
  75  * SCOM based frequency switching for 970FX rev3
  76  */
  77 static int maple_scom_switch_freq(int speed_mode)
  78 {
  79         unsigned long flags;
  80         int to;
  81 
  82         local_irq_save(flags);
  83 
  84         /* Clear PCR high */
  85         scom970_write(SCOM_PCR, 0);
  86         /* Clear PCR low */
  87         scom970_write(SCOM_PCR, PCR_HILO_SELECT | 0);
  88         /* Set PCR low */
  89         scom970_write(SCOM_PCR, PCR_HILO_SELECT |
  90                       maple_pmode_data[speed_mode]);
  91 
  92         /* Wait for completion */
  93         for (to = 0; to < 10; to++) {
  94                 unsigned long psr = scom970_read(SCOM_PSR);
  95 
  96                 if ((psr & PSR_CMD_RECEIVED) == 0 &&
  97                     (((psr >> PSR_CUR_SPEED_SHIFT) ^
  98                       (maple_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3)
  99                     == 0)
 100                         break;
 101                 if (psr & PSR_CMD_COMPLETED)
 102                         break;
 103                 udelay(100);
 104         }
 105 
 106         local_irq_restore(flags);
 107 
 108         maple_pmode_cur = speed_mode;
 109         ppc_proc_freq = maple_cpu_freqs[speed_mode].frequency * 1000ul;
 110 
 111         return 0;
 112 }
 113 
 114 static int maple_scom_query_freq(void)
 115 {
 116         unsigned long psr = scom970_read(SCOM_PSR);
 117         int i;
 118 
 119         for (i = 0; i <= maple_pmode_max; i++)
 120                 if ((((psr >> PSR_CUR_SPEED_SHIFT) ^
 121                       (maple_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0)
 122                         break;
 123         return i;
 124 }
 125 
 126 /*
 127  * Common interface to the cpufreq core
 128  */
 129 
 130 static int maple_cpufreq_target(struct cpufreq_policy *policy,
 131         unsigned int index)
 132 {
 133         return maple_scom_switch_freq(index);
 134 }
 135 
 136 static unsigned int maple_cpufreq_get_speed(unsigned int cpu)
 137 {
 138         return maple_cpu_freqs[maple_pmode_cur].frequency;
 139 }
 140 
 141 static int maple_cpufreq_cpu_init(struct cpufreq_policy *policy)
 142 {
 143         cpufreq_generic_init(policy, maple_cpu_freqs, 12000);
 144         return 0;
 145 }
 146 
 147 static struct cpufreq_driver maple_cpufreq_driver = {
 148         .name           = "maple",
 149         .flags          = CPUFREQ_CONST_LOOPS,
 150         .init           = maple_cpufreq_cpu_init,
 151         .verify         = cpufreq_generic_frequency_table_verify,
 152         .target_index   = maple_cpufreq_target,
 153         .get            = maple_cpufreq_get_speed,
 154         .attr           = cpufreq_generic_attr,
 155 };
 156 
 157 static int __init maple_cpufreq_init(void)
 158 {
 159         struct device_node *cpunode;
 160         unsigned int psize;
 161         unsigned long max_freq;
 162         const u32 *valp;
 163         u32 pvr_hi;
 164         int rc = -ENODEV;
 165 
 166         /*
 167          * Behave here like powermac driver which checks machine compatibility
 168          * to ease merging of two drivers in future.
 169          */
 170         if (!of_machine_is_compatible("Momentum,Maple") &&
 171             !of_machine_is_compatible("Momentum,Apache"))
 172                 return 0;
 173 
 174         /* Get first CPU node */
 175         cpunode = of_cpu_device_node_get(0);
 176         if (cpunode == NULL) {
 177                 pr_err("Can't find any CPU 0 node\n");
 178                 goto bail_noprops;
 179         }
 180 
 181         /* Check 970FX for now */
 182         /* we actually don't care on which CPU to access PVR */
 183         pvr_hi = PVR_VER(mfspr(SPRN_PVR));
 184         if (pvr_hi != 0x3c && pvr_hi != 0x44) {
 185                 pr_err("Unsupported CPU version (%x)\n", pvr_hi);
 186                 goto bail_noprops;
 187         }
 188 
 189         /* Look for the powertune data in the device-tree */
 190         /*
 191          * On Maple this property is provided by PIBS in dual-processor config,
 192          * not provided by PIBS in CPU0 config and also not provided by SLOF,
 193          * so YMMV
 194          */
 195         maple_pmode_data = of_get_property(cpunode, "power-mode-data", &psize);
 196         if (!maple_pmode_data) {
 197                 DBG("No power-mode-data !\n");
 198                 goto bail_noprops;
 199         }
 200         maple_pmode_max = psize / sizeof(u32) - 1;
 201 
 202         /*
 203          * From what I see, clock-frequency is always the maximal frequency.
 204          * The current driver can not slew sysclk yet, so we really only deal
 205          * with powertune steps for now. We also only implement full freq and
 206          * half freq in this version. So far, I haven't yet seen a machine
 207          * supporting anything else.
 208          */
 209         valp = of_get_property(cpunode, "clock-frequency", NULL);
 210         if (!valp)
 211                 goto bail_noprops;
 212         max_freq = (*valp)/1000;
 213         maple_cpu_freqs[0].frequency = max_freq;
 214         maple_cpu_freqs[1].frequency = max_freq/2;
 215 
 216         /* Force apply current frequency to make sure everything is in
 217          * sync (voltage is right for example). Firmware may leave us with
 218          * a strange setting ...
 219          */
 220         msleep(10);
 221         maple_pmode_cur = -1;
 222         maple_scom_switch_freq(maple_scom_query_freq());
 223 
 224         pr_info("Registering Maple CPU frequency driver\n");
 225         pr_info("Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
 226                 maple_cpu_freqs[1].frequency/1000,
 227                 maple_cpu_freqs[0].frequency/1000,
 228                 maple_cpu_freqs[maple_pmode_cur].frequency/1000);
 229 
 230         rc = cpufreq_register_driver(&maple_cpufreq_driver);
 231 
 232 bail_noprops:
 233         of_node_put(cpunode);
 234 
 235         return rc;
 236 }
 237 
 238 module_init(maple_cpufreq_init);
 239 
 240 
 241 MODULE_LICENSE("GPL");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/cpufreq/maple-cpufreq.c

DEFINITIONS
