This source file includes following definitions.
- s3c64xx_cpufreq_set_target
- s3c64xx_cpufreq_config_regulator
- s3c64xx_cpufreq_driver_init
- s3c64xx_cpufreq_init
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7
8 #define pr_fmt(fmt) "cpufreq: " fmt
9
10 #include <linux/kernel.h>
11 #include <linux/types.h>
12 #include <linux/init.h>
13 #include <linux/cpufreq.h>
14 #include <linux/clk.h>
15 #include <linux/err.h>
16 #include <linux/regulator/consumer.h>
17 #include <linux/module.h>
18
19 static struct regulator *vddarm;
20 static unsigned long regulator_latency;
21
22 #ifdef CONFIG_CPU_S3C6410
23 struct s3c64xx_dvfs {
24 unsigned int vddarm_min;
25 unsigned int vddarm_max;
26 };
27
28 static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = {
29 [0] = { 1000000, 1150000 },
30 [1] = { 1050000, 1150000 },
31 [2] = { 1100000, 1150000 },
32 [3] = { 1200000, 1350000 },
33 [4] = { 1300000, 1350000 },
34 };
35
36 static struct cpufreq_frequency_table s3c64xx_freq_table[] = {
37 { 0, 0, 66000 },
38 { 0, 0, 100000 },
39 { 0, 0, 133000 },
40 { 0, 1, 200000 },
41 { 0, 1, 222000 },
42 { 0, 1, 266000 },
43 { 0, 2, 333000 },
44 { 0, 2, 400000 },
45 { 0, 2, 532000 },
46 { 0, 2, 533000 },
47 { 0, 3, 667000 },
48 { 0, 4, 800000 },
49 { 0, 0, CPUFREQ_TABLE_END },
50 };
51 #endif
52
53 static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy,
54 unsigned int index)
55 {
56 struct s3c64xx_dvfs *dvfs;
57 unsigned int old_freq, new_freq;
58 int ret;
59
60 old_freq = clk_get_rate(policy->clk) / 1000;
61 new_freq = s3c64xx_freq_table[index].frequency;
62 dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[index].driver_data];
63
64 #ifdef CONFIG_REGULATOR
65 if (vddarm && new_freq > old_freq) {
66 ret = regulator_set_voltage(vddarm,
67 dvfs->vddarm_min,
68 dvfs->vddarm_max);
69 if (ret != 0) {
70 pr_err("Failed to set VDDARM for %dkHz: %d\n",
71 new_freq, ret);
72 return ret;
73 }
74 }
75 #endif
76
77 ret = clk_set_rate(policy->clk, new_freq * 1000);
78 if (ret < 0) {
79 pr_err("Failed to set rate %dkHz: %d\n",
80 new_freq, ret);
81 return ret;
82 }
83
84 #ifdef CONFIG_REGULATOR
85 if (vddarm && new_freq < old_freq) {
86 ret = regulator_set_voltage(vddarm,
87 dvfs->vddarm_min,
88 dvfs->vddarm_max);
89 if (ret != 0) {
90 pr_err("Failed to set VDDARM for %dkHz: %d\n",
91 new_freq, ret);
92 if (clk_set_rate(policy->clk, old_freq * 1000) < 0)
93 pr_err("Failed to restore original clock rate\n");
94
95 return ret;
96 }
97 }
98 #endif
99
100 pr_debug("Set actual frequency %lukHz\n",
101 clk_get_rate(policy->clk) / 1000);
102
103 return 0;
104 }
105
106 #ifdef CONFIG_REGULATOR
107 static void s3c64xx_cpufreq_config_regulator(void)
108 {
109 int count, v, i, found;
110 struct cpufreq_frequency_table *freq;
111 struct s3c64xx_dvfs *dvfs;
112
113 count = regulator_count_voltages(vddarm);
114 if (count < 0) {
115 pr_err("Unable to check supported voltages\n");
116 }
117
118 if (!count)
119 goto out;
120
121 cpufreq_for_each_valid_entry(freq, s3c64xx_freq_table) {
122 dvfs = &s3c64xx_dvfs_table[freq->driver_data];
123 found = 0;
124
125 for (i = 0; i < count; i++) {
126 v = regulator_list_voltage(vddarm, i);
127 if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max)
128 found = 1;
129 }
130
131 if (!found) {
132 pr_debug("%dkHz unsupported by regulator\n",
133 freq->frequency);
134 freq->frequency = CPUFREQ_ENTRY_INVALID;
135 }
136 }
137
138 out:
139
140
141 regulator_latency = 1 * 1000 * 1000;
142 }
143 #endif
144
145 static int s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
146 {
147 struct cpufreq_frequency_table *freq;
148
149 if (policy->cpu != 0)
150 return -EINVAL;
151
152 if (s3c64xx_freq_table == NULL) {
153 pr_err("No frequency information for this CPU\n");
154 return -ENODEV;
155 }
156
157 policy->clk = clk_get(NULL, "armclk");
158 if (IS_ERR(policy->clk)) {
159 pr_err("Unable to obtain ARMCLK: %ld\n",
160 PTR_ERR(policy->clk));
161 return PTR_ERR(policy->clk);
162 }
163
164 #ifdef CONFIG_REGULATOR
165 vddarm = regulator_get(NULL, "vddarm");
166 if (IS_ERR(vddarm)) {
167 pr_err("Failed to obtain VDDARM: %ld\n", PTR_ERR(vddarm));
168 pr_err("Only frequency scaling available\n");
169 vddarm = NULL;
170 } else {
171 s3c64xx_cpufreq_config_regulator();
172 }
173 #endif
174
175 cpufreq_for_each_entry(freq, s3c64xx_freq_table) {
176 unsigned long r;
177
178
179 r = clk_round_rate(policy->clk, freq->frequency * 1000);
180 r /= 1000;
181 if (r != freq->frequency) {
182 pr_debug("%dkHz unsupported by clock\n",
183 freq->frequency);
184 freq->frequency = CPUFREQ_ENTRY_INVALID;
185 }
186
187
188
189 if (!vddarm && freq->frequency > clk_get_rate(policy->clk) / 1000)
190 freq->frequency = CPUFREQ_ENTRY_INVALID;
191 }
192
193
194
195
196
197 cpufreq_generic_init(policy, s3c64xx_freq_table,
198 (500 * 1000) + regulator_latency);
199 return 0;
200 }
201
202 static struct cpufreq_driver s3c64xx_cpufreq_driver = {
203 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
204 .verify = cpufreq_generic_frequency_table_verify,
205 .target_index = s3c64xx_cpufreq_set_target,
206 .get = cpufreq_generic_get,
207 .init = s3c64xx_cpufreq_driver_init,
208 .name = "s3c",
209 };
210
211 static int __init s3c64xx_cpufreq_init(void)
212 {
213 return cpufreq_register_driver(&s3c64xx_cpufreq_driver);
214 }
215 module_init(s3c64xx_cpufreq_init);