root/drivers/cpufreq/pmac64-cpufreq.c

DEFINITIONS

1. g5_smu_switch_volt
2. g5_vdnap_switch_volt
3. g5_scom_switch_freq
4. g5_scom_query_freq
5. g5_dummy_switch_volt
6. g5_pfunc_switch_volt
7. g5_pfunc_switch_freq
8. g5_pfunc_query_freq
9. g5_cpufreq_target
10. g5_cpufreq_get_speed
11. g5_cpufreq_cpu_init
12. g5_neo2_cpufreq_init
13. g5_pm72_cpufreq_init
14. g5_cpufreq_init

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
   4  *  and                       Markus Demleitner <msdemlei@cl.uni-heidelberg.de>
   5  *
   6  * This driver adds basic cpufreq support for SMU & 970FX based G5 Macs,
   7  * that is iMac G5 and latest single CPU desktop.
   8  */
   9 
  10 #undef DEBUG
  11 
  12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13 
  14 #include <linux/module.h>
  15 #include <linux/types.h>
  16 #include <linux/errno.h>
  17 #include <linux/kernel.h>
  18 #include <linux/delay.h>
  19 #include <linux/sched.h>
  20 #include <linux/cpufreq.h>
  21 #include <linux/init.h>
  22 #include <linux/completion.h>
  23 #include <linux/mutex.h>
  24 #include <linux/of_device.h>
  25 #include <asm/prom.h>
  26 #include <asm/machdep.h>
  27 #include <asm/irq.h>
  28 #include <asm/sections.h>
  29 #include <asm/cputable.h>
  30 #include <asm/time.h>
  31 #include <asm/smu.h>
  32 #include <asm/pmac_pfunc.h>
  33 
  34 #define DBG(fmt...) pr_debug(fmt)
  35 
  36 /* see 970FX user manual */
  37 
  38 #define SCOM_PCR 0x0aa001                       /* PCR scom addr */
  39 
  40 #define PCR_HILO_SELECT         0x80000000U     /* 1 = PCR, 0 = PCRH */
  41 #define PCR_SPEED_FULL          0x00000000U     /* 1:1 speed value */
  42 #define PCR_SPEED_HALF          0x00020000U     /* 1:2 speed value */
  43 #define PCR_SPEED_QUARTER       0x00040000U     /* 1:4 speed value */
  44 #define PCR_SPEED_MASK          0x000e0000U     /* speed mask */
  45 #define PCR_SPEED_SHIFT         17
  46 #define PCR_FREQ_REQ_VALID      0x00010000U     /* freq request valid */
  47 #define PCR_VOLT_REQ_VALID      0x00008000U     /* volt request valid */
  48 #define PCR_TARGET_TIME_MASK    0x00006000U     /* target time */
  49 #define PCR_STATLAT_MASK        0x00001f00U     /* STATLAT value */
  50 #define PCR_SNOOPLAT_MASK       0x000000f0U     /* SNOOPLAT value */
  51 #define PCR_SNOOPACC_MASK       0x0000000fU     /* SNOOPACC value */
  52 
  53 #define SCOM_PSR 0x408001                       /* PSR scom addr */
  54 /* warning: PSR is a 64 bits register */
  55 #define PSR_CMD_RECEIVED        0x2000000000000000U   /* command received */
  56 #define PSR_CMD_COMPLETED       0x1000000000000000U   /* command completed */
  57 #define PSR_CUR_SPEED_MASK      0x0300000000000000U   /* current speed */
  58 #define PSR_CUR_SPEED_SHIFT     (56)
  59 
  60 /*
  61  * The G5 only supports two frequencies (Quarter speed is not supported)
  62  */
  63 #define CPUFREQ_HIGH                  0
  64 #define CPUFREQ_LOW                   1
  65 
  66 static struct cpufreq_frequency_table g5_cpu_freqs[] = {
  67         {0, CPUFREQ_HIGH,       0},
  68         {0, CPUFREQ_LOW,        0},
  69         {0, 0,                  CPUFREQ_TABLE_END},
  70 };
  71 
  72 /* Power mode data is an array of the 32 bits PCR values to use for
  73  * the various frequencies, retrieved from the device-tree
  74  */
  75 static int g5_pmode_cur;
  76 
  77 static void (*g5_switch_volt)(int speed_mode);
  78 static int (*g5_switch_freq)(int speed_mode);
  79 static int (*g5_query_freq)(void);
  80 
  81 static unsigned long transition_latency;
  82 
  83 #ifdef CONFIG_PMAC_SMU
  84 
  85 static const u32 *g5_pmode_data;
  86 static int g5_pmode_max;
  87 
  88 static struct smu_sdbp_fvt *g5_fvt_table;       /* table of op. points */
  89 static int g5_fvt_count;                        /* number of op. points */
  90 static int g5_fvt_cur;                          /* current op. point */
  91 
  92 /*
  93  * SMU based voltage switching for Neo2 platforms
  94  */
  95 
  96 static void g5_smu_switch_volt(int speed_mode)
  97 {
  98         struct smu_simple_cmd   cmd;
  99 
 100         DECLARE_COMPLETION_ONSTACK(comp);
 101         smu_queue_simple(&cmd, SMU_CMD_POWER_COMMAND, 8, smu_done_complete,
 102                          &comp, 'V', 'S', 'L', 'E', 'W',
 103                          0xff, g5_fvt_cur+1, speed_mode);
 104         wait_for_completion(&comp);
 105 }
 106 
 107 /*
 108  * Platform function based voltage/vdnap switching for Neo2
 109  */
 110 
 111 static struct pmf_function *pfunc_set_vdnap0;
 112 static struct pmf_function *pfunc_vdnap0_complete;
 113 
 114 static void g5_vdnap_switch_volt(int speed_mode)
 115 {
 116         struct pmf_args args;
 117         u32 slew, done = 0;
 118         unsigned long timeout;
 119 
 120         slew = (speed_mode == CPUFREQ_LOW) ? 1 : 0;
 121         args.count = 1;
 122         args.u[0].p = &slew;
 123 
 124         pmf_call_one(pfunc_set_vdnap0, &args);
 125 
 126         /* It's an irq GPIO so we should be able to just block here,
 127          * I'll do that later after I've properly tested the IRQ code for
 128          * platform functions
 129          */
 130         timeout = jiffies + HZ/10;
 131         while(!time_after(jiffies, timeout)) {
 132                 args.count = 1;
 133                 args.u[0].p = &done;
 134                 pmf_call_one(pfunc_vdnap0_complete, &args);
 135                 if (done)
 136                         break;
 137                 usleep_range(1000, 1000);
 138         }
 139         if (done == 0)
 140                 pr_warn("Timeout in clock slewing !\n");
 141 }
 142 
 143 
 144 /*
 145  * SCOM based frequency switching for 970FX rev3
 146  */
 147 static int g5_scom_switch_freq(int speed_mode)
 148 {
 149         unsigned long flags;
 150         int to;
 151 
 152         /* If frequency is going up, first ramp up the voltage */
 153         if (speed_mode < g5_pmode_cur)
 154                 g5_switch_volt(speed_mode);
 155 
 156         local_irq_save(flags);
 157 
 158         /* Clear PCR high */
 159         scom970_write(SCOM_PCR, 0);
 160         /* Clear PCR low */
 161         scom970_write(SCOM_PCR, PCR_HILO_SELECT | 0);
 162         /* Set PCR low */
 163         scom970_write(SCOM_PCR, PCR_HILO_SELECT |
 164                       g5_pmode_data[speed_mode]);
 165 
 166         /* Wait for completion */
 167         for (to = 0; to < 10; to++) {
 168                 unsigned long psr = scom970_read(SCOM_PSR);
 169 
 170                 if ((psr & PSR_CMD_RECEIVED) == 0 &&
 171                     (((psr >> PSR_CUR_SPEED_SHIFT) ^
 172                       (g5_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3)
 173                     == 0)
 174                         break;
 175                 if (psr & PSR_CMD_COMPLETED)
 176                         break;
 177                 udelay(100);
 178         }
 179 
 180         local_irq_restore(flags);
 181 
 182         /* If frequency is going down, last ramp the voltage */
 183         if (speed_mode > g5_pmode_cur)
 184                 g5_switch_volt(speed_mode);
 185 
 186         g5_pmode_cur = speed_mode;
 187         ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
 188 
 189         return 0;
 190 }
 191 
 192 static int g5_scom_query_freq(void)
 193 {
 194         unsigned long psr = scom970_read(SCOM_PSR);
 195         int i;
 196 
 197         for (i = 0; i <= g5_pmode_max; i++)
 198                 if ((((psr >> PSR_CUR_SPEED_SHIFT) ^
 199                       (g5_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0)
 200                         break;
 201         return i;
 202 }
 203 
 204 /*
 205  * Fake voltage switching for platforms with missing support
 206  */
 207 
 208 static void g5_dummy_switch_volt(int speed_mode)
 209 {
 210 }
 211 
 212 #endif /* CONFIG_PMAC_SMU */
 213 
 214 /*
 215  * Platform function based voltage switching for PowerMac7,2 & 7,3
 216  */
 217 
 218 static struct pmf_function *pfunc_cpu0_volt_high;
 219 static struct pmf_function *pfunc_cpu0_volt_low;
 220 static struct pmf_function *pfunc_cpu1_volt_high;
 221 static struct pmf_function *pfunc_cpu1_volt_low;
 222 
 223 static void g5_pfunc_switch_volt(int speed_mode)
 224 {
 225         if (speed_mode == CPUFREQ_HIGH) {
 226                 if (pfunc_cpu0_volt_high)
 227                         pmf_call_one(pfunc_cpu0_volt_high, NULL);
 228                 if (pfunc_cpu1_volt_high)
 229                         pmf_call_one(pfunc_cpu1_volt_high, NULL);
 230         } else {
 231                 if (pfunc_cpu0_volt_low)
 232                         pmf_call_one(pfunc_cpu0_volt_low, NULL);
 233                 if (pfunc_cpu1_volt_low)
 234                         pmf_call_one(pfunc_cpu1_volt_low, NULL);
 235         }
 236         usleep_range(10000, 10000); /* should be faster , to fix */
 237 }
 238 
 239 /*
 240  * Platform function based frequency switching for PowerMac7,2 & 7,3
 241  */
 242 
 243 static struct pmf_function *pfunc_cpu_setfreq_high;
 244 static struct pmf_function *pfunc_cpu_setfreq_low;
 245 static struct pmf_function *pfunc_cpu_getfreq;
 246 static struct pmf_function *pfunc_slewing_done;
 247 
 248 static int g5_pfunc_switch_freq(int speed_mode)
 249 {
 250         struct pmf_args args;
 251         u32 done = 0;
 252         unsigned long timeout;
 253         int rc;
 254 
 255         DBG("g5_pfunc_switch_freq(%d)\n", speed_mode);
 256 
 257         /* If frequency is going up, first ramp up the voltage */
 258         if (speed_mode < g5_pmode_cur)
 259                 g5_switch_volt(speed_mode);
 260 
 261         /* Do it */
 262         if (speed_mode == CPUFREQ_HIGH)
 263                 rc = pmf_call_one(pfunc_cpu_setfreq_high, NULL);
 264         else
 265                 rc = pmf_call_one(pfunc_cpu_setfreq_low, NULL);
 266 
 267         if (rc)
 268                 pr_warn("pfunc switch error %d\n", rc);
 269 
 270         /* It's an irq GPIO so we should be able to just block here,
 271          * I'll do that later after I've properly tested the IRQ code for
 272          * platform functions
 273          */
 274         timeout = jiffies + HZ/10;
 275         while(!time_after(jiffies, timeout)) {
 276                 args.count = 1;
 277                 args.u[0].p = &done;
 278                 pmf_call_one(pfunc_slewing_done, &args);
 279                 if (done)
 280                         break;
 281                 usleep_range(500, 500);
 282         }
 283         if (done == 0)
 284                 pr_warn("Timeout in clock slewing !\n");
 285 
 286         /* If frequency is going down, last ramp the voltage */
 287         if (speed_mode > g5_pmode_cur)
 288                 g5_switch_volt(speed_mode);
 289 
 290         g5_pmode_cur = speed_mode;
 291         ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
 292 
 293         return 0;
 294 }
 295 
 296 static int g5_pfunc_query_freq(void)
 297 {
 298         struct pmf_args args;
 299         u32 val = 0;
 300 
 301         args.count = 1;
 302         args.u[0].p = &val;
 303         pmf_call_one(pfunc_cpu_getfreq, &args);
 304         return val ? CPUFREQ_HIGH : CPUFREQ_LOW;
 305 }
 306 
 307 
 308 /*
 309  * Common interface to the cpufreq core
 310  */
 311 
 312 static int g5_cpufreq_target(struct cpufreq_policy *policy, unsigned int index)
 313 {
 314         return g5_switch_freq(index);
 315 }
 316 
 317 static unsigned int g5_cpufreq_get_speed(unsigned int cpu)
 318 {
 319         return g5_cpu_freqs[g5_pmode_cur].frequency;
 320 }
 321 
 322 static int g5_cpufreq_cpu_init(struct cpufreq_policy *policy)
 323 {
 324         cpufreq_generic_init(policy, g5_cpu_freqs, transition_latency);
 325         return 0;
 326 }
 327 
 328 static struct cpufreq_driver g5_cpufreq_driver = {
 329         .name           = "powermac",
 330         .flags          = CPUFREQ_CONST_LOOPS,
 331         .init           = g5_cpufreq_cpu_init,
 332         .verify         = cpufreq_generic_frequency_table_verify,
 333         .target_index   = g5_cpufreq_target,
 334         .get            = g5_cpufreq_get_speed,
 335         .attr           = cpufreq_generic_attr,
 336 };
 337 
 338 
 339 #ifdef CONFIG_PMAC_SMU
 340 
 341 static int __init g5_neo2_cpufreq_init(struct device_node *cpunode)
 342 {
 343         unsigned int psize, ssize;
 344         unsigned long max_freq;
 345         char *freq_method, *volt_method;
 346         const u32 *valp;
 347         u32 pvr_hi;
 348         int use_volts_vdnap = 0;
 349         int use_volts_smu = 0;
 350         int rc = -ENODEV;
 351 
 352         /* Check supported platforms */
 353         if (of_machine_is_compatible("PowerMac8,1") ||
 354             of_machine_is_compatible("PowerMac8,2") ||
 355             of_machine_is_compatible("PowerMac9,1") ||
 356             of_machine_is_compatible("PowerMac12,1"))
 357                 use_volts_smu = 1;
 358         else if (of_machine_is_compatible("PowerMac11,2"))
 359                 use_volts_vdnap = 1;
 360         else
 361                 return -ENODEV;
 362 
 363         /* Check 970FX for now */
 364         valp = of_get_property(cpunode, "cpu-version", NULL);
 365         if (!valp) {
 366                 DBG("No cpu-version property !\n");
 367                 goto bail_noprops;
 368         }
 369         pvr_hi = (*valp) >> 16;
 370         if (pvr_hi != 0x3c && pvr_hi != 0x44) {
 371                 pr_err("Unsupported CPU version\n");
 372                 goto bail_noprops;
 373         }
 374 
 375         /* Look for the powertune data in the device-tree */
 376         g5_pmode_data = of_get_property(cpunode, "power-mode-data",&psize);
 377         if (!g5_pmode_data) {
 378                 DBG("No power-mode-data !\n");
 379                 goto bail_noprops;
 380         }
 381         g5_pmode_max = psize / sizeof(u32) - 1;
 382 
 383         if (use_volts_smu) {
 384                 const struct smu_sdbp_header *shdr;
 385 
 386                 /* Look for the FVT table */
 387                 shdr = smu_get_sdb_partition(SMU_SDB_FVT_ID, NULL);
 388                 if (!shdr)
 389                         goto bail_noprops;
 390                 g5_fvt_table = (struct smu_sdbp_fvt *)&shdr[1];
 391                 ssize = (shdr->len * sizeof(u32)) - sizeof(*shdr);
 392                 g5_fvt_count = ssize / sizeof(*g5_fvt_table);
 393                 g5_fvt_cur = 0;
 394 
 395                 /* Sanity checking */
 396                 if (g5_fvt_count < 1 || g5_pmode_max < 1)
 397                         goto bail_noprops;
 398 
 399                 g5_switch_volt = g5_smu_switch_volt;
 400                 volt_method = "SMU";
 401         } else if (use_volts_vdnap) {
 402                 struct device_node *root;
 403 
 404                 root = of_find_node_by_path("/");
 405                 if (root == NULL) {
 406                         pr_err("Can't find root of device tree\n");
 407                         goto bail_noprops;
 408                 }
 409                 pfunc_set_vdnap0 = pmf_find_function(root, "set-vdnap0");
 410                 pfunc_vdnap0_complete =
 411                         pmf_find_function(root, "slewing-done");
 412                 of_node_put(root);
 413                 if (pfunc_set_vdnap0 == NULL ||
 414                     pfunc_vdnap0_complete == NULL) {
 415                         pr_err("Can't find required platform function\n");
 416                         goto bail_noprops;
 417                 }
 418 
 419                 g5_switch_volt = g5_vdnap_switch_volt;
 420                 volt_method = "GPIO";
 421         } else {
 422                 g5_switch_volt = g5_dummy_switch_volt;
 423                 volt_method = "none";
 424         }
 425 
 426         /*
 427          * From what I see, clock-frequency is always the maximal frequency.
 428          * The current driver can not slew sysclk yet, so we really only deal
 429          * with powertune steps for now. We also only implement full freq and
 430          * half freq in this version. So far, I haven't yet seen a machine
 431          * supporting anything else.
 432          */
 433         valp = of_get_property(cpunode, "clock-frequency", NULL);
 434         if (!valp)
 435                 return -ENODEV;
 436         max_freq = (*valp)/1000;
 437         g5_cpu_freqs[0].frequency = max_freq;
 438         g5_cpu_freqs[1].frequency = max_freq/2;
 439 
 440         /* Set callbacks */
 441         transition_latency = 12000;
 442         g5_switch_freq = g5_scom_switch_freq;
 443         g5_query_freq = g5_scom_query_freq;
 444         freq_method = "SCOM";
 445 
 446         /* Force apply current frequency to make sure everything is in
 447          * sync (voltage is right for example). Firmware may leave us with
 448          * a strange setting ...
 449          */
 450         g5_switch_volt(CPUFREQ_HIGH);
 451         msleep(10);
 452         g5_pmode_cur = -1;
 453         g5_switch_freq(g5_query_freq());
 454 
 455         pr_info("Registering G5 CPU frequency driver\n");
 456         pr_info("Frequency method: %s, Voltage method: %s\n",
 457                 freq_method, volt_method);
 458         pr_info("Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
 459                 g5_cpu_freqs[1].frequency/1000,
 460                 g5_cpu_freqs[0].frequency/1000,
 461                 g5_cpu_freqs[g5_pmode_cur].frequency/1000);
 462 
 463         rc = cpufreq_register_driver(&g5_cpufreq_driver);
 464 
 465         /* We keep the CPU node on hold... hopefully, Apple G5 don't have
 466          * hotplug CPU with a dynamic device-tree ...
 467          */
 468         return rc;
 469 
 470  bail_noprops:
 471         of_node_put(cpunode);
 472 
 473         return rc;
 474 }
 475 
 476 #endif /* CONFIG_PMAC_SMU */
 477 
 478 
 479 static int __init g5_pm72_cpufreq_init(struct device_node *cpunode)
 480 {
 481         struct device_node *cpuid = NULL, *hwclock = NULL;
 482         const u8 *eeprom = NULL;
 483         const u32 *valp;
 484         u64 max_freq, min_freq, ih, il;
 485         int has_volt = 1, rc = 0;
 486 
 487         DBG("cpufreq: Initializing for PowerMac7,2, PowerMac7,3 and"
 488             " RackMac3,1...\n");
 489 
 490         /* Lookup the cpuid eeprom node */
 491         cpuid = of_find_node_by_path("/u3@0,f8000000/i2c@f8001000/cpuid@a0");
 492         if (cpuid != NULL)
 493                 eeprom = of_get_property(cpuid, "cpuid", NULL);
 494         if (eeprom == NULL) {
 495                 pr_err("Can't find cpuid EEPROM !\n");
 496                 rc = -ENODEV;
 497                 goto bail;
 498         }
 499 
 500         /* Lookup the i2c hwclock */
 501         for_each_node_by_name(hwclock, "i2c-hwclock") {
 502                 const char *loc = of_get_property(hwclock,
 503                                 "hwctrl-location", NULL);
 504                 if (loc == NULL)
 505                         continue;
 506                 if (strcmp(loc, "CPU CLOCK"))
 507                         continue;
 508                 if (!of_get_property(hwclock, "platform-get-frequency", NULL))
 509                         continue;
 510                 break;
 511         }
 512         if (hwclock == NULL) {
 513                 pr_err("Can't find i2c clock chip !\n");
 514                 rc = -ENODEV;
 515                 goto bail;
 516         }
 517 
 518         DBG("cpufreq: i2c clock chip found: %pOF\n", hwclock);
 519 
 520         /* Now get all the platform functions */
 521         pfunc_cpu_getfreq =
 522                 pmf_find_function(hwclock, "get-frequency");
 523         pfunc_cpu_setfreq_high =
 524                 pmf_find_function(hwclock, "set-frequency-high");
 525         pfunc_cpu_setfreq_low =
 526                 pmf_find_function(hwclock, "set-frequency-low");
 527         pfunc_slewing_done =
 528                 pmf_find_function(hwclock, "slewing-done");
 529         pfunc_cpu0_volt_high =
 530                 pmf_find_function(hwclock, "set-voltage-high-0");
 531         pfunc_cpu0_volt_low =
 532                 pmf_find_function(hwclock, "set-voltage-low-0");
 533         pfunc_cpu1_volt_high =
 534                 pmf_find_function(hwclock, "set-voltage-high-1");
 535         pfunc_cpu1_volt_low =
 536                 pmf_find_function(hwclock, "set-voltage-low-1");
 537 
 538         /* Check we have minimum requirements */
 539         if (pfunc_cpu_getfreq == NULL || pfunc_cpu_setfreq_high == NULL ||
 540             pfunc_cpu_setfreq_low == NULL || pfunc_slewing_done == NULL) {
 541                 pr_err("Can't find platform functions !\n");
 542                 rc = -ENODEV;
 543                 goto bail;
 544         }
 545 
 546         /* Check that we have complete sets */
 547         if (pfunc_cpu0_volt_high == NULL || pfunc_cpu0_volt_low == NULL) {
 548                 pmf_put_function(pfunc_cpu0_volt_high);
 549                 pmf_put_function(pfunc_cpu0_volt_low);
 550                 pfunc_cpu0_volt_high = pfunc_cpu0_volt_low = NULL;
 551                 has_volt = 0;
 552         }
 553         if (!has_volt ||
 554             pfunc_cpu1_volt_high == NULL || pfunc_cpu1_volt_low == NULL) {
 555                 pmf_put_function(pfunc_cpu1_volt_high);
 556                 pmf_put_function(pfunc_cpu1_volt_low);
 557                 pfunc_cpu1_volt_high = pfunc_cpu1_volt_low = NULL;
 558         }
 559 
 560         /* Note: The device tree also contains a "platform-set-values"
 561          * function for which I haven't quite figured out the usage. It
 562          * might have to be called on init and/or wakeup, I'm not too sure
 563          * but things seem to work fine without it so far ...
 564          */
 565 
 566         /* Get max frequency from device-tree */
 567         valp = of_get_property(cpunode, "clock-frequency", NULL);
 568         if (!valp) {
 569                 pr_err("Can't find CPU frequency !\n");
 570                 rc = -ENODEV;
 571                 goto bail;
 572         }
 573 
 574         max_freq = (*valp)/1000;
 575 
 576         /* Now calculate reduced frequency by using the cpuid input freq
 577          * ratio. This requires 64 bits math unless we are willing to lose
 578          * some precision
 579          */
 580         ih = *((u32 *)(eeprom + 0x10));
 581         il = *((u32 *)(eeprom + 0x20));
 582 
 583         /* Check for machines with no useful settings */
 584         if (il == ih) {
 585                 pr_warn("No low frequency mode available on this model !\n");
 586                 rc = -ENODEV;
 587                 goto bail;
 588         }
 589 
 590         min_freq = 0;
 591         if (ih != 0 && il != 0)
 592                 min_freq = (max_freq * il) / ih;
 593 
 594         /* Sanity check */
 595         if (min_freq >= max_freq || min_freq < 1000) {
 596                 pr_err("Can't calculate low frequency !\n");
 597                 rc = -ENXIO;
 598                 goto bail;
 599         }
 600         g5_cpu_freqs[0].frequency = max_freq;
 601         g5_cpu_freqs[1].frequency = min_freq;
 602 
 603         /* Based on a measurement on Xserve G5, rounded up. */
 604         transition_latency = 10 * NSEC_PER_MSEC;
 605 
 606         /* Set callbacks */
 607         g5_switch_volt = g5_pfunc_switch_volt;
 608         g5_switch_freq = g5_pfunc_switch_freq;
 609         g5_query_freq = g5_pfunc_query_freq;
 610 
 611         /* Force apply current frequency to make sure everything is in
 612          * sync (voltage is right for example). Firmware may leave us with
 613          * a strange setting ...
 614          */
 615         g5_switch_volt(CPUFREQ_HIGH);
 616         msleep(10);
 617         g5_pmode_cur = -1;
 618         g5_switch_freq(g5_query_freq());
 619 
 620         pr_info("Registering G5 CPU frequency driver\n");
 621         pr_info("Frequency method: i2c/pfunc, Voltage method: %s\n",
 622                 has_volt ? "i2c/pfunc" : "none");
 623         pr_info("Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
 624                 g5_cpu_freqs[1].frequency/1000,
 625                 g5_cpu_freqs[0].frequency/1000,
 626                 g5_cpu_freqs[g5_pmode_cur].frequency/1000);
 627 
 628         rc = cpufreq_register_driver(&g5_cpufreq_driver);
 629  bail:
 630         if (rc != 0) {
 631                 pmf_put_function(pfunc_cpu_getfreq);
 632                 pmf_put_function(pfunc_cpu_setfreq_high);
 633                 pmf_put_function(pfunc_cpu_setfreq_low);
 634                 pmf_put_function(pfunc_slewing_done);
 635                 pmf_put_function(pfunc_cpu0_volt_high);
 636                 pmf_put_function(pfunc_cpu0_volt_low);
 637                 pmf_put_function(pfunc_cpu1_volt_high);
 638                 pmf_put_function(pfunc_cpu1_volt_low);
 639         }
 640         of_node_put(hwclock);
 641         of_node_put(cpuid);
 642         of_node_put(cpunode);
 643 
 644         return rc;
 645 }
 646 
 647 static int __init g5_cpufreq_init(void)
 648 {
 649         struct device_node *cpunode;
 650         int rc = 0;
 651 
 652         /* Get first CPU node */
 653         cpunode = of_cpu_device_node_get(0);
 654         if (cpunode == NULL) {
 655                 pr_err("Can't find any CPU node\n");
 656                 return -ENODEV;
 657         }
 658 
 659         if (of_machine_is_compatible("PowerMac7,2") ||
 660             of_machine_is_compatible("PowerMac7,3") ||
 661             of_machine_is_compatible("RackMac3,1"))
 662                 rc = g5_pm72_cpufreq_init(cpunode);
 663 #ifdef CONFIG_PMAC_SMU
 664         else
 665                 rc = g5_neo2_cpufreq_init(cpunode);
 666 #endif /* CONFIG_PMAC_SMU */
 667 
 668         return rc;
 669 }
 670 
 671 module_init(g5_cpufreq_init);
 672 
 673 
 674 MODULE_LICENSE("GPL");