drivers/mfd/lpc

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This source file includes following definitions.
lpc_ich_restore_config_space
lpc_ich_enable_acpi_space
lpc_ich_enable_gpio_space
lpc_ich_enable_pmc_space
lpc_ich_finalize_wdt_cell
lpc_ich_finalize_gpio_cell
lpc_ich_check_conflict_gpio
lpc_ich_init_gpio
lpc_ich_init_wdt
lpc_ich_init_spi
lpc_ich_probe
lpc_ich_remove
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  lpc_ich.c - LPC interface for Intel ICH
   4  *
   5  *  LPC bridge function of the Intel ICH contains many other
   6  *  functional units, such as Interrupt controllers, Timers,
   7  *  Power Management, System Management, GPIO, RTC, and LPC
   8  *  Configuration Registers.
   9  *
  10  *  This driver is derived from lpc_sch.
  11 
  12  *  Copyright (c) 2011 Extreme Engineering Solution, Inc.
  13  *  Author: Aaron Sierra <asierra@xes-inc.com>
  14  *
  15  *  This driver supports the following I/O Controller hubs:
  16  *      (See the intel documentation on http://developer.intel.com.)
  17  *      document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
  18  *      document number 290687-002, 298242-027: 82801BA (ICH2)
  19  *      document number 290733-003, 290739-013: 82801CA (ICH3-S)
  20  *      document number 290716-001, 290718-007: 82801CAM (ICH3-M)
  21  *      document number 290744-001, 290745-025: 82801DB (ICH4)
  22  *      document number 252337-001, 252663-008: 82801DBM (ICH4-M)
  23  *      document number 273599-001, 273645-002: 82801E (C-ICH)
  24  *      document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
  25  *      document number 300641-004, 300884-013: 6300ESB
  26  *      document number 301473-002, 301474-026: 82801F (ICH6)
  27  *      document number 313082-001, 313075-006: 631xESB, 632xESB
  28  *      document number 307013-003, 307014-024: 82801G (ICH7)
  29  *      document number 322896-001, 322897-001: NM10
  30  *      document number 313056-003, 313057-017: 82801H (ICH8)
  31  *      document number 316972-004, 316973-012: 82801I (ICH9)
  32  *      document number 319973-002, 319974-002: 82801J (ICH10)
  33  *      document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
  34  *      document number 320066-003, 320257-008: EP80597 (IICH)
  35  *      document number 324645-001, 324646-001: Cougar Point (CPT)
  36  */
  37 
  38 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  39 
  40 #include <linux/kernel.h>
  41 #include <linux/module.h>
  42 #include <linux/errno.h>
  43 #include <linux/acpi.h>
  44 #include <linux/pci.h>
  45 #include <linux/mfd/core.h>
  46 #include <linux/mfd/lpc_ich.h>
  47 #include <linux/platform_data/itco_wdt.h>
  48 
  49 #define ACPIBASE                0x40
  50 #define ACPIBASE_GPE_OFF        0x28
  51 #define ACPIBASE_GPE_END        0x2f
  52 #define ACPIBASE_SMI_OFF        0x30
  53 #define ACPIBASE_SMI_END        0x33
  54 #define ACPIBASE_PMC_OFF        0x08
  55 #define ACPIBASE_PMC_END        0x0c
  56 #define ACPIBASE_TCO_OFF        0x60
  57 #define ACPIBASE_TCO_END        0x7f
  58 #define ACPICTRL_PMCBASE        0x44
  59 
  60 #define ACPIBASE_GCS_OFF        0x3410
  61 #define ACPIBASE_GCS_END        0x3414
  62 
  63 #define SPIBASE_BYT             0x54
  64 #define SPIBASE_BYT_SZ          512
  65 #define SPIBASE_BYT_EN          BIT(1)
  66 
  67 #define SPIBASE_LPT             0x3800
  68 #define SPIBASE_LPT_SZ          512
  69 #define BCR                     0xdc
  70 #define BCR_WPD                 BIT(0)
  71 
  72 #define SPIBASE_APL_SZ          4096
  73 
  74 #define GPIOBASE_ICH0           0x58
  75 #define GPIOCTRL_ICH0           0x5C
  76 #define GPIOBASE_ICH6           0x48
  77 #define GPIOCTRL_ICH6           0x4C
  78 
  79 #define RCBABASE                0xf0
  80 
  81 #define wdt_io_res(i) wdt_res(0, i)
  82 #define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i)
  83 #define wdt_res(b, i) (&wdt_ich_res[(b) + (i)])
  84 
  85 struct lpc_ich_priv {
  86         int chipset;
  87 
  88         int abase;              /* ACPI base */
  89         int actrl_pbase;        /* ACPI control or PMC base */
  90         int gbase;              /* GPIO base */
  91         int gctrl;              /* GPIO control */
  92 
  93         int abase_save;         /* Cached ACPI base value */
  94         int actrl_pbase_save;           /* Cached ACPI control or PMC base value */
  95         int gctrl_save;         /* Cached GPIO control value */
  96 };
  97 
  98 static struct resource wdt_ich_res[] = {
  99         /* ACPI - TCO */
 100         {
 101                 .flags = IORESOURCE_IO,
 102         },
 103         /* ACPI - SMI */
 104         {
 105                 .flags = IORESOURCE_IO,
 106         },
 107         /* GCS or PMC */
 108         {
 109                 .flags = IORESOURCE_MEM,
 110         },
 111 };
 112 
 113 static struct resource gpio_ich_res[] = {
 114         /* GPIO */
 115         {
 116                 .flags = IORESOURCE_IO,
 117         },
 118         /* ACPI - GPE0 */
 119         {
 120                 .flags = IORESOURCE_IO,
 121         },
 122 };
 123 
 124 static struct resource intel_spi_res[] = {
 125         {
 126                 .flags = IORESOURCE_MEM,
 127         }
 128 };
 129 
 130 static struct mfd_cell lpc_ich_wdt_cell = {
 131         .name = "iTCO_wdt",
 132         .num_resources = ARRAY_SIZE(wdt_ich_res),
 133         .resources = wdt_ich_res,
 134         .ignore_resource_conflicts = true,
 135 };
 136 
 137 static struct mfd_cell lpc_ich_gpio_cell = {
 138         .name = "gpio_ich",
 139         .num_resources = ARRAY_SIZE(gpio_ich_res),
 140         .resources = gpio_ich_res,
 141         .ignore_resource_conflicts = true,
 142 };
 143 
 144 
 145 static struct mfd_cell lpc_ich_spi_cell = {
 146         .name = "intel-spi",
 147         .num_resources = ARRAY_SIZE(intel_spi_res),
 148         .resources = intel_spi_res,
 149         .ignore_resource_conflicts = true,
 150 };
 151 
 152 /* chipset related info */
 153 enum lpc_chipsets {
 154         LPC_ICH = 0,    /* ICH */
 155         LPC_ICH0,       /* ICH0 */
 156         LPC_ICH2,       /* ICH2 */
 157         LPC_ICH2M,      /* ICH2-M */
 158         LPC_ICH3,       /* ICH3-S */
 159         LPC_ICH3M,      /* ICH3-M */
 160         LPC_ICH4,       /* ICH4 */
 161         LPC_ICH4M,      /* ICH4-M */
 162         LPC_CICH,       /* C-ICH */
 163         LPC_ICH5,       /* ICH5 & ICH5R */
 164         LPC_6300ESB,    /* 6300ESB */
 165         LPC_ICH6,       /* ICH6 & ICH6R */
 166         LPC_ICH6M,      /* ICH6-M */
 167         LPC_ICH6W,      /* ICH6W & ICH6RW */
 168         LPC_631XESB,    /* 631xESB/632xESB */
 169         LPC_ICH7,       /* ICH7 & ICH7R */
 170         LPC_ICH7DH,     /* ICH7DH */
 171         LPC_ICH7M,      /* ICH7-M & ICH7-U */
 172         LPC_ICH7MDH,    /* ICH7-M DH */
 173         LPC_NM10,       /* NM10 */
 174         LPC_ICH8,       /* ICH8 & ICH8R */
 175         LPC_ICH8DH,     /* ICH8DH */
 176         LPC_ICH8DO,     /* ICH8DO */
 177         LPC_ICH8M,      /* ICH8M */
 178         LPC_ICH8ME,     /* ICH8M-E */
 179         LPC_ICH9,       /* ICH9 */
 180         LPC_ICH9R,      /* ICH9R */
 181         LPC_ICH9DH,     /* ICH9DH */
 182         LPC_ICH9DO,     /* ICH9DO */
 183         LPC_ICH9M,      /* ICH9M */
 184         LPC_ICH9ME,     /* ICH9M-E */
 185         LPC_ICH10,      /* ICH10 */
 186         LPC_ICH10R,     /* ICH10R */
 187         LPC_ICH10D,     /* ICH10D */
 188         LPC_ICH10DO,    /* ICH10DO */
 189         LPC_PCH,        /* PCH Desktop Full Featured */
 190         LPC_PCHM,       /* PCH Mobile Full Featured */
 191         LPC_P55,        /* P55 */
 192         LPC_PM55,       /* PM55 */
 193         LPC_H55,        /* H55 */
 194         LPC_QM57,       /* QM57 */
 195         LPC_H57,        /* H57 */
 196         LPC_HM55,       /* HM55 */
 197         LPC_Q57,        /* Q57 */
 198         LPC_HM57,       /* HM57 */
 199         LPC_PCHMSFF,    /* PCH Mobile SFF Full Featured */
 200         LPC_QS57,       /* QS57 */
 201         LPC_3400,       /* 3400 */
 202         LPC_3420,       /* 3420 */
 203         LPC_3450,       /* 3450 */
 204         LPC_EP80579,    /* EP80579 */
 205         LPC_CPT,        /* Cougar Point */
 206         LPC_CPTD,       /* Cougar Point Desktop */
 207         LPC_CPTM,       /* Cougar Point Mobile */
 208         LPC_PBG,        /* Patsburg */
 209         LPC_DH89XXCC,   /* DH89xxCC */
 210         LPC_PPT,        /* Panther Point */
 211         LPC_LPT,        /* Lynx Point */
 212         LPC_LPT_LP,     /* Lynx Point-LP */
 213         LPC_WBG,        /* Wellsburg */
 214         LPC_AVN,        /* Avoton SoC */
 215         LPC_BAYTRAIL,   /* Bay Trail SoC */
 216         LPC_COLETO,     /* Coleto Creek */
 217         LPC_WPT_LP,     /* Wildcat Point-LP */
 218         LPC_BRASWELL,   /* Braswell SoC */
 219         LPC_LEWISBURG,  /* Lewisburg */
 220         LPC_9S,         /* 9 Series */
 221         LPC_APL,        /* Apollo Lake SoC */
 222         LPC_GLK,        /* Gemini Lake SoC */
 223         LPC_COUGARMOUNTAIN,/* Cougar Mountain SoC*/
 224 };
 225 
 226 static struct lpc_ich_info lpc_chipset_info[] = {
 227         [LPC_ICH] = {
 228                 .name = "ICH",
 229                 .iTCO_version = 1,
 230         },
 231         [LPC_ICH0] = {
 232                 .name = "ICH0",
 233                 .iTCO_version = 1,
 234         },
 235         [LPC_ICH2] = {
 236                 .name = "ICH2",
 237                 .iTCO_version = 1,
 238         },
 239         [LPC_ICH2M] = {
 240                 .name = "ICH2-M",
 241                 .iTCO_version = 1,
 242         },
 243         [LPC_ICH3] = {
 244                 .name = "ICH3-S",
 245                 .iTCO_version = 1,
 246         },
 247         [LPC_ICH3M] = {
 248                 .name = "ICH3-M",
 249                 .iTCO_version = 1,
 250         },
 251         [LPC_ICH4] = {
 252                 .name = "ICH4",
 253                 .iTCO_version = 1,
 254         },
 255         [LPC_ICH4M] = {
 256                 .name = "ICH4-M",
 257                 .iTCO_version = 1,
 258         },
 259         [LPC_CICH] = {
 260                 .name = "C-ICH",
 261                 .iTCO_version = 1,
 262         },
 263         [LPC_ICH5] = {
 264                 .name = "ICH5 or ICH5R",
 265                 .iTCO_version = 1,
 266         },
 267         [LPC_6300ESB] = {
 268                 .name = "6300ESB",
 269                 .iTCO_version = 1,
 270         },
 271         [LPC_ICH6] = {
 272                 .name = "ICH6 or ICH6R",
 273                 .iTCO_version = 2,
 274                 .gpio_version = ICH_V6_GPIO,
 275         },
 276         [LPC_ICH6M] = {
 277                 .name = "ICH6-M",
 278                 .iTCO_version = 2,
 279                 .gpio_version = ICH_V6_GPIO,
 280         },
 281         [LPC_ICH6W] = {
 282                 .name = "ICH6W or ICH6RW",
 283                 .iTCO_version = 2,
 284                 .gpio_version = ICH_V6_GPIO,
 285         },
 286         [LPC_631XESB] = {
 287                 .name = "631xESB/632xESB",
 288                 .iTCO_version = 2,
 289                 .gpio_version = ICH_V6_GPIO,
 290         },
 291         [LPC_ICH7] = {
 292                 .name = "ICH7 or ICH7R",
 293                 .iTCO_version = 2,
 294                 .gpio_version = ICH_V7_GPIO,
 295         },
 296         [LPC_ICH7DH] = {
 297                 .name = "ICH7DH",
 298                 .iTCO_version = 2,
 299                 .gpio_version = ICH_V7_GPIO,
 300         },
 301         [LPC_ICH7M] = {
 302                 .name = "ICH7-M or ICH7-U",
 303                 .iTCO_version = 2,
 304                 .gpio_version = ICH_V7_GPIO,
 305         },
 306         [LPC_ICH7MDH] = {
 307                 .name = "ICH7-M DH",
 308                 .iTCO_version = 2,
 309                 .gpio_version = ICH_V7_GPIO,
 310         },
 311         [LPC_NM10] = {
 312                 .name = "NM10",
 313                 .iTCO_version = 2,
 314                 .gpio_version = ICH_V7_GPIO,
 315         },
 316         [LPC_ICH8] = {
 317                 .name = "ICH8 or ICH8R",
 318                 .iTCO_version = 2,
 319                 .gpio_version = ICH_V7_GPIO,
 320         },
 321         [LPC_ICH8DH] = {
 322                 .name = "ICH8DH",
 323                 .iTCO_version = 2,
 324                 .gpio_version = ICH_V7_GPIO,
 325         },
 326         [LPC_ICH8DO] = {
 327                 .name = "ICH8DO",
 328                 .iTCO_version = 2,
 329                 .gpio_version = ICH_V7_GPIO,
 330         },
 331         [LPC_ICH8M] = {
 332                 .name = "ICH8M",
 333                 .iTCO_version = 2,
 334                 .gpio_version = ICH_V7_GPIO,
 335         },
 336         [LPC_ICH8ME] = {
 337                 .name = "ICH8M-E",
 338                 .iTCO_version = 2,
 339                 .gpio_version = ICH_V7_GPIO,
 340         },
 341         [LPC_ICH9] = {
 342                 .name = "ICH9",
 343                 .iTCO_version = 2,
 344                 .gpio_version = ICH_V9_GPIO,
 345         },
 346         [LPC_ICH9R] = {
 347                 .name = "ICH9R",
 348                 .iTCO_version = 2,
 349                 .gpio_version = ICH_V9_GPIO,
 350         },
 351         [LPC_ICH9DH] = {
 352                 .name = "ICH9DH",
 353                 .iTCO_version = 2,
 354                 .gpio_version = ICH_V9_GPIO,
 355         },
 356         [LPC_ICH9DO] = {
 357                 .name = "ICH9DO",
 358                 .iTCO_version = 2,
 359                 .gpio_version = ICH_V9_GPIO,
 360         },
 361         [LPC_ICH9M] = {
 362                 .name = "ICH9M",
 363                 .iTCO_version = 2,
 364                 .gpio_version = ICH_V9_GPIO,
 365         },
 366         [LPC_ICH9ME] = {
 367                 .name = "ICH9M-E",
 368                 .iTCO_version = 2,
 369                 .gpio_version = ICH_V9_GPIO,
 370         },
 371         [LPC_ICH10] = {
 372                 .name = "ICH10",
 373                 .iTCO_version = 2,
 374                 .gpio_version = ICH_V10CONS_GPIO,
 375         },
 376         [LPC_ICH10R] = {
 377                 .name = "ICH10R",
 378                 .iTCO_version = 2,
 379                 .gpio_version = ICH_V10CONS_GPIO,
 380         },
 381         [LPC_ICH10D] = {
 382                 .name = "ICH10D",
 383                 .iTCO_version = 2,
 384                 .gpio_version = ICH_V10CORP_GPIO,
 385         },
 386         [LPC_ICH10DO] = {
 387                 .name = "ICH10DO",
 388                 .iTCO_version = 2,
 389                 .gpio_version = ICH_V10CORP_GPIO,
 390         },
 391         [LPC_PCH] = {
 392                 .name = "PCH Desktop Full Featured",
 393                 .iTCO_version = 2,
 394                 .gpio_version = ICH_V5_GPIO,
 395         },
 396         [LPC_PCHM] = {
 397                 .name = "PCH Mobile Full Featured",
 398                 .iTCO_version = 2,
 399                 .gpio_version = ICH_V5_GPIO,
 400         },
 401         [LPC_P55] = {
 402                 .name = "P55",
 403                 .iTCO_version = 2,
 404                 .gpio_version = ICH_V5_GPIO,
 405         },
 406         [LPC_PM55] = {
 407                 .name = "PM55",
 408                 .iTCO_version = 2,
 409                 .gpio_version = ICH_V5_GPIO,
 410         },
 411         [LPC_H55] = {
 412                 .name = "H55",
 413                 .iTCO_version = 2,
 414                 .gpio_version = ICH_V5_GPIO,
 415         },
 416         [LPC_QM57] = {
 417                 .name = "QM57",
 418                 .iTCO_version = 2,
 419                 .gpio_version = ICH_V5_GPIO,
 420         },
 421         [LPC_H57] = {
 422                 .name = "H57",
 423                 .iTCO_version = 2,
 424                 .gpio_version = ICH_V5_GPIO,
 425         },
 426         [LPC_HM55] = {
 427                 .name = "HM55",
 428                 .iTCO_version = 2,
 429                 .gpio_version = ICH_V5_GPIO,
 430         },
 431         [LPC_Q57] = {
 432                 .name = "Q57",
 433                 .iTCO_version = 2,
 434                 .gpio_version = ICH_V5_GPIO,
 435         },
 436         [LPC_HM57] = {
 437                 .name = "HM57",
 438                 .iTCO_version = 2,
 439                 .gpio_version = ICH_V5_GPIO,
 440         },
 441         [LPC_PCHMSFF] = {
 442                 .name = "PCH Mobile SFF Full Featured",
 443                 .iTCO_version = 2,
 444                 .gpio_version = ICH_V5_GPIO,
 445         },
 446         [LPC_QS57] = {
 447                 .name = "QS57",
 448                 .iTCO_version = 2,
 449                 .gpio_version = ICH_V5_GPIO,
 450         },
 451         [LPC_3400] = {
 452                 .name = "3400",
 453                 .iTCO_version = 2,
 454                 .gpio_version = ICH_V5_GPIO,
 455         },
 456         [LPC_3420] = {
 457                 .name = "3420",
 458                 .iTCO_version = 2,
 459                 .gpio_version = ICH_V5_GPIO,
 460         },
 461         [LPC_3450] = {
 462                 .name = "3450",
 463                 .iTCO_version = 2,
 464                 .gpio_version = ICH_V5_GPIO,
 465         },
 466         [LPC_EP80579] = {
 467                 .name = "EP80579",
 468                 .iTCO_version = 2,
 469         },
 470         [LPC_CPT] = {
 471                 .name = "Cougar Point",
 472                 .iTCO_version = 2,
 473                 .gpio_version = ICH_V5_GPIO,
 474         },
 475         [LPC_CPTD] = {
 476                 .name = "Cougar Point Desktop",
 477                 .iTCO_version = 2,
 478                 .gpio_version = ICH_V5_GPIO,
 479         },
 480         [LPC_CPTM] = {
 481                 .name = "Cougar Point Mobile",
 482                 .iTCO_version = 2,
 483                 .gpio_version = ICH_V5_GPIO,
 484         },
 485         [LPC_PBG] = {
 486                 .name = "Patsburg",
 487                 .iTCO_version = 2,
 488         },
 489         [LPC_DH89XXCC] = {
 490                 .name = "DH89xxCC",
 491                 .iTCO_version = 2,
 492         },
 493         [LPC_PPT] = {
 494                 .name = "Panther Point",
 495                 .iTCO_version = 2,
 496                 .gpio_version = ICH_V5_GPIO,
 497         },
 498         [LPC_LPT] = {
 499                 .name = "Lynx Point",
 500                 .iTCO_version = 2,
 501                 .gpio_version = ICH_V5_GPIO,
 502                 .spi_type = INTEL_SPI_LPT,
 503         },
 504         [LPC_LPT_LP] = {
 505                 .name = "Lynx Point_LP",
 506                 .iTCO_version = 2,
 507                 .spi_type = INTEL_SPI_LPT,
 508         },
 509         [LPC_WBG] = {
 510                 .name = "Wellsburg",
 511                 .iTCO_version = 2,
 512         },
 513         [LPC_AVN] = {
 514                 .name = "Avoton SoC",
 515                 .iTCO_version = 3,
 516                 .gpio_version = AVOTON_GPIO,
 517                 .spi_type = INTEL_SPI_BYT,
 518         },
 519         [LPC_BAYTRAIL] = {
 520                 .name = "Bay Trail SoC",
 521                 .iTCO_version = 3,
 522                 .spi_type = INTEL_SPI_BYT,
 523         },
 524         [LPC_COLETO] = {
 525                 .name = "Coleto Creek",
 526                 .iTCO_version = 2,
 527         },
 528         [LPC_WPT_LP] = {
 529                 .name = "Wildcat Point_LP",
 530                 .iTCO_version = 2,
 531                 .spi_type = INTEL_SPI_LPT,
 532         },
 533         [LPC_BRASWELL] = {
 534                 .name = "Braswell SoC",
 535                 .iTCO_version = 3,
 536                 .spi_type = INTEL_SPI_BYT,
 537         },
 538         [LPC_LEWISBURG] = {
 539                 .name = "Lewisburg",
 540                 .iTCO_version = 2,
 541         },
 542         [LPC_9S] = {
 543                 .name = "9 Series",
 544                 .iTCO_version = 2,
 545                 .gpio_version = ICH_V5_GPIO,
 546         },
 547         [LPC_APL] = {
 548                 .name = "Apollo Lake SoC",
 549                 .iTCO_version = 5,
 550                 .spi_type = INTEL_SPI_BXT,
 551         },
 552         [LPC_GLK] = {
 553                 .name = "Gemini Lake SoC",
 554                 .spi_type = INTEL_SPI_BXT,
 555         },
 556         [LPC_COUGARMOUNTAIN] = {
 557                 .name = "Cougar Mountain SoC",
 558                 .iTCO_version = 3,
 559         },
 560 };
 561 
 562 /*
 563  * This data only exists for exporting the supported PCI ids
 564  * via MODULE_DEVICE_TABLE.  We do not actually register a
 565  * pci_driver, because the I/O Controller Hub has also other
 566  * functions that probably will be registered by other drivers.
 567  */
 568 static const struct pci_device_id lpc_ich_ids[] = {
 569         { PCI_VDEVICE(INTEL, 0x0f1c), LPC_BAYTRAIL},
 570         { PCI_VDEVICE(INTEL, 0x1c41), LPC_CPT},
 571         { PCI_VDEVICE(INTEL, 0x1c42), LPC_CPTD},
 572         { PCI_VDEVICE(INTEL, 0x1c43), LPC_CPTM},
 573         { PCI_VDEVICE(INTEL, 0x1c44), LPC_CPT},
 574         { PCI_VDEVICE(INTEL, 0x1c45), LPC_CPT},
 575         { PCI_VDEVICE(INTEL, 0x1c46), LPC_CPT},
 576         { PCI_VDEVICE(INTEL, 0x1c47), LPC_CPT},
 577         { PCI_VDEVICE(INTEL, 0x1c48), LPC_CPT},
 578         { PCI_VDEVICE(INTEL, 0x1c49), LPC_CPT},
 579         { PCI_VDEVICE(INTEL, 0x1c4a), LPC_CPT},
 580         { PCI_VDEVICE(INTEL, 0x1c4b), LPC_CPT},
 581         { PCI_VDEVICE(INTEL, 0x1c4c), LPC_CPT},
 582         { PCI_VDEVICE(INTEL, 0x1c4d), LPC_CPT},
 583         { PCI_VDEVICE(INTEL, 0x1c4e), LPC_CPT},
 584         { PCI_VDEVICE(INTEL, 0x1c4f), LPC_CPT},
 585         { PCI_VDEVICE(INTEL, 0x1c50), LPC_CPT},
 586         { PCI_VDEVICE(INTEL, 0x1c51), LPC_CPT},
 587         { PCI_VDEVICE(INTEL, 0x1c52), LPC_CPT},
 588         { PCI_VDEVICE(INTEL, 0x1c53), LPC_CPT},
 589         { PCI_VDEVICE(INTEL, 0x1c54), LPC_CPT},
 590         { PCI_VDEVICE(INTEL, 0x1c55), LPC_CPT},
 591         { PCI_VDEVICE(INTEL, 0x1c56), LPC_CPT},
 592         { PCI_VDEVICE(INTEL, 0x1c57), LPC_CPT},
 593         { PCI_VDEVICE(INTEL, 0x1c58), LPC_CPT},
 594         { PCI_VDEVICE(INTEL, 0x1c59), LPC_CPT},
 595         { PCI_VDEVICE(INTEL, 0x1c5a), LPC_CPT},
 596         { PCI_VDEVICE(INTEL, 0x1c5b), LPC_CPT},
 597         { PCI_VDEVICE(INTEL, 0x1c5c), LPC_CPT},
 598         { PCI_VDEVICE(INTEL, 0x1c5d), LPC_CPT},
 599         { PCI_VDEVICE(INTEL, 0x1c5e), LPC_CPT},
 600         { PCI_VDEVICE(INTEL, 0x1c5f), LPC_CPT},
 601         { PCI_VDEVICE(INTEL, 0x1d40), LPC_PBG},
 602         { PCI_VDEVICE(INTEL, 0x1d41), LPC_PBG},
 603         { PCI_VDEVICE(INTEL, 0x1e40), LPC_PPT},
 604         { PCI_VDEVICE(INTEL, 0x1e41), LPC_PPT},
 605         { PCI_VDEVICE(INTEL, 0x1e42), LPC_PPT},
 606         { PCI_VDEVICE(INTEL, 0x1e43), LPC_PPT},
 607         { PCI_VDEVICE(INTEL, 0x1e44), LPC_PPT},
 608         { PCI_VDEVICE(INTEL, 0x1e45), LPC_PPT},
 609         { PCI_VDEVICE(INTEL, 0x1e46), LPC_PPT},
 610         { PCI_VDEVICE(INTEL, 0x1e47), LPC_PPT},
 611         { PCI_VDEVICE(INTEL, 0x1e48), LPC_PPT},
 612         { PCI_VDEVICE(INTEL, 0x1e49), LPC_PPT},
 613         { PCI_VDEVICE(INTEL, 0x1e4a), LPC_PPT},
 614         { PCI_VDEVICE(INTEL, 0x1e4b), LPC_PPT},
 615         { PCI_VDEVICE(INTEL, 0x1e4c), LPC_PPT},
 616         { PCI_VDEVICE(INTEL, 0x1e4d), LPC_PPT},
 617         { PCI_VDEVICE(INTEL, 0x1e4e), LPC_PPT},
 618         { PCI_VDEVICE(INTEL, 0x1e4f), LPC_PPT},
 619         { PCI_VDEVICE(INTEL, 0x1e50), LPC_PPT},
 620         { PCI_VDEVICE(INTEL, 0x1e51), LPC_PPT},
 621         { PCI_VDEVICE(INTEL, 0x1e52), LPC_PPT},
 622         { PCI_VDEVICE(INTEL, 0x1e53), LPC_PPT},
 623         { PCI_VDEVICE(INTEL, 0x1e54), LPC_PPT},
 624         { PCI_VDEVICE(INTEL, 0x1e55), LPC_PPT},
 625         { PCI_VDEVICE(INTEL, 0x1e56), LPC_PPT},
 626         { PCI_VDEVICE(INTEL, 0x1e57), LPC_PPT},
 627         { PCI_VDEVICE(INTEL, 0x1e58), LPC_PPT},
 628         { PCI_VDEVICE(INTEL, 0x1e59), LPC_PPT},
 629         { PCI_VDEVICE(INTEL, 0x1e5a), LPC_PPT},
 630         { PCI_VDEVICE(INTEL, 0x1e5b), LPC_PPT},
 631         { PCI_VDEVICE(INTEL, 0x1e5c), LPC_PPT},
 632         { PCI_VDEVICE(INTEL, 0x1e5d), LPC_PPT},
 633         { PCI_VDEVICE(INTEL, 0x1e5e), LPC_PPT},
 634         { PCI_VDEVICE(INTEL, 0x1e5f), LPC_PPT},
 635         { PCI_VDEVICE(INTEL, 0x1f38), LPC_AVN},
 636         { PCI_VDEVICE(INTEL, 0x1f39), LPC_AVN},
 637         { PCI_VDEVICE(INTEL, 0x1f3a), LPC_AVN},
 638         { PCI_VDEVICE(INTEL, 0x1f3b), LPC_AVN},
 639         { PCI_VDEVICE(INTEL, 0x229c), LPC_BRASWELL},
 640         { PCI_VDEVICE(INTEL, 0x2310), LPC_DH89XXCC},
 641         { PCI_VDEVICE(INTEL, 0x2390), LPC_COLETO},
 642         { PCI_VDEVICE(INTEL, 0x2410), LPC_ICH},
 643         { PCI_VDEVICE(INTEL, 0x2420), LPC_ICH0},
 644         { PCI_VDEVICE(INTEL, 0x2440), LPC_ICH2},
 645         { PCI_VDEVICE(INTEL, 0x244c), LPC_ICH2M},
 646         { PCI_VDEVICE(INTEL, 0x2450), LPC_CICH},
 647         { PCI_VDEVICE(INTEL, 0x2480), LPC_ICH3},
 648         { PCI_VDEVICE(INTEL, 0x248c), LPC_ICH3M},
 649         { PCI_VDEVICE(INTEL, 0x24c0), LPC_ICH4},
 650         { PCI_VDEVICE(INTEL, 0x24cc), LPC_ICH4M},
 651         { PCI_VDEVICE(INTEL, 0x24d0), LPC_ICH5},
 652         { PCI_VDEVICE(INTEL, 0x25a1), LPC_6300ESB},
 653         { PCI_VDEVICE(INTEL, 0x2640), LPC_ICH6},
 654         { PCI_VDEVICE(INTEL, 0x2641), LPC_ICH6M},
 655         { PCI_VDEVICE(INTEL, 0x2642), LPC_ICH6W},
 656         { PCI_VDEVICE(INTEL, 0x2670), LPC_631XESB},
 657         { PCI_VDEVICE(INTEL, 0x2671), LPC_631XESB},
 658         { PCI_VDEVICE(INTEL, 0x2672), LPC_631XESB},
 659         { PCI_VDEVICE(INTEL, 0x2673), LPC_631XESB},
 660         { PCI_VDEVICE(INTEL, 0x2674), LPC_631XESB},
 661         { PCI_VDEVICE(INTEL, 0x2675), LPC_631XESB},
 662         { PCI_VDEVICE(INTEL, 0x2676), LPC_631XESB},
 663         { PCI_VDEVICE(INTEL, 0x2677), LPC_631XESB},
 664         { PCI_VDEVICE(INTEL, 0x2678), LPC_631XESB},
 665         { PCI_VDEVICE(INTEL, 0x2679), LPC_631XESB},
 666         { PCI_VDEVICE(INTEL, 0x267a), LPC_631XESB},
 667         { PCI_VDEVICE(INTEL, 0x267b), LPC_631XESB},
 668         { PCI_VDEVICE(INTEL, 0x267c), LPC_631XESB},
 669         { PCI_VDEVICE(INTEL, 0x267d), LPC_631XESB},
 670         { PCI_VDEVICE(INTEL, 0x267e), LPC_631XESB},
 671         { PCI_VDEVICE(INTEL, 0x267f), LPC_631XESB},
 672         { PCI_VDEVICE(INTEL, 0x27b0), LPC_ICH7DH},
 673         { PCI_VDEVICE(INTEL, 0x27b8), LPC_ICH7},
 674         { PCI_VDEVICE(INTEL, 0x27b9), LPC_ICH7M},
 675         { PCI_VDEVICE(INTEL, 0x27bc), LPC_NM10},
 676         { PCI_VDEVICE(INTEL, 0x27bd), LPC_ICH7MDH},
 677         { PCI_VDEVICE(INTEL, 0x2810), LPC_ICH8},
 678         { PCI_VDEVICE(INTEL, 0x2811), LPC_ICH8ME},
 679         { PCI_VDEVICE(INTEL, 0x2812), LPC_ICH8DH},
 680         { PCI_VDEVICE(INTEL, 0x2814), LPC_ICH8DO},
 681         { PCI_VDEVICE(INTEL, 0x2815), LPC_ICH8M},
 682         { PCI_VDEVICE(INTEL, 0x2912), LPC_ICH9DH},
 683         { PCI_VDEVICE(INTEL, 0x2914), LPC_ICH9DO},
 684         { PCI_VDEVICE(INTEL, 0x2916), LPC_ICH9R},
 685         { PCI_VDEVICE(INTEL, 0x2917), LPC_ICH9ME},
 686         { PCI_VDEVICE(INTEL, 0x2918), LPC_ICH9},
 687         { PCI_VDEVICE(INTEL, 0x2919), LPC_ICH9M},
 688         { PCI_VDEVICE(INTEL, 0x3197), LPC_GLK},
 689         { PCI_VDEVICE(INTEL, 0x2b9c), LPC_COUGARMOUNTAIN},
 690         { PCI_VDEVICE(INTEL, 0x3a14), LPC_ICH10DO},
 691         { PCI_VDEVICE(INTEL, 0x3a16), LPC_ICH10R},
 692         { PCI_VDEVICE(INTEL, 0x3a18), LPC_ICH10},
 693         { PCI_VDEVICE(INTEL, 0x3a1a), LPC_ICH10D},
 694         { PCI_VDEVICE(INTEL, 0x3b00), LPC_PCH},
 695         { PCI_VDEVICE(INTEL, 0x3b01), LPC_PCHM},
 696         { PCI_VDEVICE(INTEL, 0x3b02), LPC_P55},
 697         { PCI_VDEVICE(INTEL, 0x3b03), LPC_PM55},
 698         { PCI_VDEVICE(INTEL, 0x3b06), LPC_H55},
 699         { PCI_VDEVICE(INTEL, 0x3b07), LPC_QM57},
 700         { PCI_VDEVICE(INTEL, 0x3b08), LPC_H57},
 701         { PCI_VDEVICE(INTEL, 0x3b09), LPC_HM55},
 702         { PCI_VDEVICE(INTEL, 0x3b0a), LPC_Q57},
 703         { PCI_VDEVICE(INTEL, 0x3b0b), LPC_HM57},
 704         { PCI_VDEVICE(INTEL, 0x3b0d), LPC_PCHMSFF},
 705         { PCI_VDEVICE(INTEL, 0x3b0f), LPC_QS57},
 706         { PCI_VDEVICE(INTEL, 0x3b12), LPC_3400},
 707         { PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
 708         { PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
 709         { PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
 710         { PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL},
 711         { PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
 712         { PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
 713         { PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
 714         { PCI_VDEVICE(INTEL, 0x8c43), LPC_LPT},
 715         { PCI_VDEVICE(INTEL, 0x8c44), LPC_LPT},
 716         { PCI_VDEVICE(INTEL, 0x8c45), LPC_LPT},
 717         { PCI_VDEVICE(INTEL, 0x8c46), LPC_LPT},
 718         { PCI_VDEVICE(INTEL, 0x8c47), LPC_LPT},
 719         { PCI_VDEVICE(INTEL, 0x8c48), LPC_LPT},
 720         { PCI_VDEVICE(INTEL, 0x8c49), LPC_LPT},
 721         { PCI_VDEVICE(INTEL, 0x8c4a), LPC_LPT},
 722         { PCI_VDEVICE(INTEL, 0x8c4b), LPC_LPT},
 723         { PCI_VDEVICE(INTEL, 0x8c4c), LPC_LPT},
 724         { PCI_VDEVICE(INTEL, 0x8c4d), LPC_LPT},
 725         { PCI_VDEVICE(INTEL, 0x8c4e), LPC_LPT},
 726         { PCI_VDEVICE(INTEL, 0x8c4f), LPC_LPT},
 727         { PCI_VDEVICE(INTEL, 0x8c50), LPC_LPT},
 728         { PCI_VDEVICE(INTEL, 0x8c51), LPC_LPT},
 729         { PCI_VDEVICE(INTEL, 0x8c52), LPC_LPT},
 730         { PCI_VDEVICE(INTEL, 0x8c53), LPC_LPT},
 731         { PCI_VDEVICE(INTEL, 0x8c54), LPC_LPT},
 732         { PCI_VDEVICE(INTEL, 0x8c55), LPC_LPT},
 733         { PCI_VDEVICE(INTEL, 0x8c56), LPC_LPT},
 734         { PCI_VDEVICE(INTEL, 0x8c57), LPC_LPT},
 735         { PCI_VDEVICE(INTEL, 0x8c58), LPC_LPT},
 736         { PCI_VDEVICE(INTEL, 0x8c59), LPC_LPT},
 737         { PCI_VDEVICE(INTEL, 0x8c5a), LPC_LPT},
 738         { PCI_VDEVICE(INTEL, 0x8c5b), LPC_LPT},
 739         { PCI_VDEVICE(INTEL, 0x8c5c), LPC_LPT},
 740         { PCI_VDEVICE(INTEL, 0x8c5d), LPC_LPT},
 741         { PCI_VDEVICE(INTEL, 0x8c5e), LPC_LPT},
 742         { PCI_VDEVICE(INTEL, 0x8c5f), LPC_LPT},
 743         { PCI_VDEVICE(INTEL, 0x8cc1), LPC_9S},
 744         { PCI_VDEVICE(INTEL, 0x8cc2), LPC_9S},
 745         { PCI_VDEVICE(INTEL, 0x8cc3), LPC_9S},
 746         { PCI_VDEVICE(INTEL, 0x8cc4), LPC_9S},
 747         { PCI_VDEVICE(INTEL, 0x8cc6), LPC_9S},
 748         { PCI_VDEVICE(INTEL, 0x8d40), LPC_WBG},
 749         { PCI_VDEVICE(INTEL, 0x8d41), LPC_WBG},
 750         { PCI_VDEVICE(INTEL, 0x8d42), LPC_WBG},
 751         { PCI_VDEVICE(INTEL, 0x8d43), LPC_WBG},
 752         { PCI_VDEVICE(INTEL, 0x8d44), LPC_WBG},
 753         { PCI_VDEVICE(INTEL, 0x8d45), LPC_WBG},
 754         { PCI_VDEVICE(INTEL, 0x8d46), LPC_WBG},
 755         { PCI_VDEVICE(INTEL, 0x8d47), LPC_WBG},
 756         { PCI_VDEVICE(INTEL, 0x8d48), LPC_WBG},
 757         { PCI_VDEVICE(INTEL, 0x8d49), LPC_WBG},
 758         { PCI_VDEVICE(INTEL, 0x8d4a), LPC_WBG},
 759         { PCI_VDEVICE(INTEL, 0x8d4b), LPC_WBG},
 760         { PCI_VDEVICE(INTEL, 0x8d4c), LPC_WBG},
 761         { PCI_VDEVICE(INTEL, 0x8d4d), LPC_WBG},
 762         { PCI_VDEVICE(INTEL, 0x8d4e), LPC_WBG},
 763         { PCI_VDEVICE(INTEL, 0x8d4f), LPC_WBG},
 764         { PCI_VDEVICE(INTEL, 0x8d50), LPC_WBG},
 765         { PCI_VDEVICE(INTEL, 0x8d51), LPC_WBG},
 766         { PCI_VDEVICE(INTEL, 0x8d52), LPC_WBG},
 767         { PCI_VDEVICE(INTEL, 0x8d53), LPC_WBG},
 768         { PCI_VDEVICE(INTEL, 0x8d54), LPC_WBG},
 769         { PCI_VDEVICE(INTEL, 0x8d55), LPC_WBG},
 770         { PCI_VDEVICE(INTEL, 0x8d56), LPC_WBG},
 771         { PCI_VDEVICE(INTEL, 0x8d57), LPC_WBG},
 772         { PCI_VDEVICE(INTEL, 0x8d58), LPC_WBG},
 773         { PCI_VDEVICE(INTEL, 0x8d59), LPC_WBG},
 774         { PCI_VDEVICE(INTEL, 0x8d5a), LPC_WBG},
 775         { PCI_VDEVICE(INTEL, 0x8d5b), LPC_WBG},
 776         { PCI_VDEVICE(INTEL, 0x8d5c), LPC_WBG},
 777         { PCI_VDEVICE(INTEL, 0x8d5d), LPC_WBG},
 778         { PCI_VDEVICE(INTEL, 0x8d5e), LPC_WBG},
 779         { PCI_VDEVICE(INTEL, 0x8d5f), LPC_WBG},
 780         { PCI_VDEVICE(INTEL, 0x9c40), LPC_LPT_LP},
 781         { PCI_VDEVICE(INTEL, 0x9c41), LPC_LPT_LP},
 782         { PCI_VDEVICE(INTEL, 0x9c42), LPC_LPT_LP},
 783         { PCI_VDEVICE(INTEL, 0x9c43), LPC_LPT_LP},
 784         { PCI_VDEVICE(INTEL, 0x9c44), LPC_LPT_LP},
 785         { PCI_VDEVICE(INTEL, 0x9c45), LPC_LPT_LP},
 786         { PCI_VDEVICE(INTEL, 0x9c46), LPC_LPT_LP},
 787         { PCI_VDEVICE(INTEL, 0x9c47), LPC_LPT_LP},
 788         { PCI_VDEVICE(INTEL, 0x9cc1), LPC_WPT_LP},
 789         { PCI_VDEVICE(INTEL, 0x9cc2), LPC_WPT_LP},
 790         { PCI_VDEVICE(INTEL, 0x9cc3), LPC_WPT_LP},
 791         { PCI_VDEVICE(INTEL, 0x9cc5), LPC_WPT_LP},
 792         { PCI_VDEVICE(INTEL, 0x9cc6), LPC_WPT_LP},
 793         { PCI_VDEVICE(INTEL, 0x9cc7), LPC_WPT_LP},
 794         { PCI_VDEVICE(INTEL, 0x9cc9), LPC_WPT_LP},
 795         { PCI_VDEVICE(INTEL, 0xa1c1), LPC_LEWISBURG},
 796         { PCI_VDEVICE(INTEL, 0xa1c2), LPC_LEWISBURG},
 797         { PCI_VDEVICE(INTEL, 0xa1c3), LPC_LEWISBURG},
 798         { PCI_VDEVICE(INTEL, 0xa1c4), LPC_LEWISBURG},
 799         { PCI_VDEVICE(INTEL, 0xa1c5), LPC_LEWISBURG},
 800         { PCI_VDEVICE(INTEL, 0xa1c6), LPC_LEWISBURG},
 801         { PCI_VDEVICE(INTEL, 0xa1c7), LPC_LEWISBURG},
 802         { PCI_VDEVICE(INTEL, 0xa242), LPC_LEWISBURG},
 803         { PCI_VDEVICE(INTEL, 0xa243), LPC_LEWISBURG},
 804         { 0, },                 /* End of list */
 805 };
 806 MODULE_DEVICE_TABLE(pci, lpc_ich_ids);
 807 
 808 static void lpc_ich_restore_config_space(struct pci_dev *dev)
 809 {
 810         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
 811 
 812         if (priv->abase_save >= 0) {
 813                 pci_write_config_byte(dev, priv->abase, priv->abase_save);
 814                 priv->abase_save = -1;
 815         }
 816 
 817         if (priv->actrl_pbase_save >= 0) {
 818                 pci_write_config_byte(dev, priv->actrl_pbase,
 819                         priv->actrl_pbase_save);
 820                 priv->actrl_pbase_save = -1;
 821         }
 822 
 823         if (priv->gctrl_save >= 0) {
 824                 pci_write_config_byte(dev, priv->gctrl, priv->gctrl_save);
 825                 priv->gctrl_save = -1;
 826         }
 827 }
 828 
 829 static void lpc_ich_enable_acpi_space(struct pci_dev *dev)
 830 {
 831         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
 832         u8 reg_save;
 833 
 834         switch (lpc_chipset_info[priv->chipset].iTCO_version) {
 835         case 3:
 836                 /*
 837                  * Some chipsets (eg Avoton) enable the ACPI space in the
 838                  * ACPI BASE register.
 839                  */
 840                 pci_read_config_byte(dev, priv->abase, &reg_save);
 841                 pci_write_config_byte(dev, priv->abase, reg_save | 0x2);
 842                 priv->abase_save = reg_save;
 843                 break;
 844         default:
 845                 /*
 846                  * Most chipsets enable the ACPI space in the ACPI control
 847                  * register.
 848                  */
 849                 pci_read_config_byte(dev, priv->actrl_pbase, &reg_save);
 850                 pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x80);
 851                 priv->actrl_pbase_save = reg_save;
 852                 break;
 853         }
 854 }
 855 
 856 static void lpc_ich_enable_gpio_space(struct pci_dev *dev)
 857 {
 858         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
 859         u8 reg_save;
 860 
 861         pci_read_config_byte(dev, priv->gctrl, &reg_save);
 862         pci_write_config_byte(dev, priv->gctrl, reg_save | 0x10);
 863         priv->gctrl_save = reg_save;
 864 }
 865 
 866 static void lpc_ich_enable_pmc_space(struct pci_dev *dev)
 867 {
 868         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
 869         u8 reg_save;
 870 
 871         pci_read_config_byte(dev, priv->actrl_pbase, &reg_save);
 872         pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x2);
 873 
 874         priv->actrl_pbase_save = reg_save;
 875 }
 876 
 877 static int lpc_ich_finalize_wdt_cell(struct pci_dev *dev)
 878 {
 879         struct itco_wdt_platform_data *pdata;
 880         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
 881         struct lpc_ich_info *info;
 882         struct mfd_cell *cell = &lpc_ich_wdt_cell;
 883 
 884         pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
 885         if (!pdata)
 886                 return -ENOMEM;
 887 
 888         info = &lpc_chipset_info[priv->chipset];
 889 
 890         pdata->version = info->iTCO_version;
 891         strlcpy(pdata->name, info->name, sizeof(pdata->name));
 892 
 893         cell->platform_data = pdata;
 894         cell->pdata_size = sizeof(*pdata);
 895         return 0;
 896 }
 897 
 898 static void lpc_ich_finalize_gpio_cell(struct pci_dev *dev)
 899 {
 900         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
 901         struct mfd_cell *cell = &lpc_ich_gpio_cell;
 902 
 903         cell->platform_data = &lpc_chipset_info[priv->chipset];
 904         cell->pdata_size = sizeof(struct lpc_ich_info);
 905 }
 906 
 907 /*
 908  * We don't check for resource conflict globally. There are 2 or 3 independent
 909  * GPIO groups and it's enough to have access to one of these to instantiate
 910  * the device.
 911  */
 912 static int lpc_ich_check_conflict_gpio(struct resource *res)
 913 {
 914         int ret;
 915         u8 use_gpio = 0;
 916 
 917         if (resource_size(res) >= 0x50 &&
 918             !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3"))
 919                 use_gpio |= 1 << 2;
 920 
 921         if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2"))
 922                 use_gpio |= 1 << 1;
 923 
 924         ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1");
 925         if (!ret)
 926                 use_gpio |= 1 << 0;
 927 
 928         return use_gpio ? use_gpio : ret;
 929 }
 930 
 931 static int lpc_ich_init_gpio(struct pci_dev *dev)
 932 {
 933         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
 934         u32 base_addr_cfg;
 935         u32 base_addr;
 936         int ret;
 937         bool acpi_conflict = false;
 938         struct resource *res;
 939 
 940         /* Setup power management base register */
 941         pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
 942         base_addr = base_addr_cfg & 0x0000ff80;
 943         if (!base_addr) {
 944                 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
 945                 lpc_ich_gpio_cell.num_resources--;
 946                 goto gpe0_done;
 947         }
 948 
 949         res = &gpio_ich_res[ICH_RES_GPE0];
 950         res->start = base_addr + ACPIBASE_GPE_OFF;
 951         res->end = base_addr + ACPIBASE_GPE_END;
 952         ret = acpi_check_resource_conflict(res);
 953         if (ret) {
 954                 /*
 955                  * This isn't fatal for the GPIO, but we have to make sure that
 956                  * the platform_device subsystem doesn't see this resource
 957                  * or it will register an invalid region.
 958                  */
 959                 lpc_ich_gpio_cell.num_resources--;
 960                 acpi_conflict = true;
 961         } else {
 962                 lpc_ich_enable_acpi_space(dev);
 963         }
 964 
 965 gpe0_done:
 966         /* Setup GPIO base register */
 967         pci_read_config_dword(dev, priv->gbase, &base_addr_cfg);
 968         base_addr = base_addr_cfg & 0x0000ff80;
 969         if (!base_addr) {
 970                 dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n");
 971                 ret = -ENODEV;
 972                 goto gpio_done;
 973         }
 974 
 975         /* Older devices provide fewer GPIO and have a smaller resource size. */
 976         res = &gpio_ich_res[ICH_RES_GPIO];
 977         res->start = base_addr;
 978         switch (lpc_chipset_info[priv->chipset].gpio_version) {
 979         case ICH_V5_GPIO:
 980         case ICH_V10CORP_GPIO:
 981                 res->end = res->start + 128 - 1;
 982                 break;
 983         default:
 984                 res->end = res->start + 64 - 1;
 985                 break;
 986         }
 987 
 988         ret = lpc_ich_check_conflict_gpio(res);
 989         if (ret < 0) {
 990                 /* this isn't necessarily fatal for the GPIO */
 991                 acpi_conflict = true;
 992                 goto gpio_done;
 993         }
 994         lpc_chipset_info[priv->chipset].use_gpio = ret;
 995         lpc_ich_enable_gpio_space(dev);
 996 
 997         lpc_ich_finalize_gpio_cell(dev);
 998         ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO,
 999                               &lpc_ich_gpio_cell, 1, NULL, 0, NULL);
1000 
1001 gpio_done:
1002         if (acpi_conflict)
1003                 pr_warn("Resource conflict(s) found affecting %s\n",
1004                                 lpc_ich_gpio_cell.name);
1005         return ret;
1006 }
1007 
1008 static int lpc_ich_init_wdt(struct pci_dev *dev)
1009 {
1010         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1011         u32 base_addr_cfg;
1012         u32 base_addr;
1013         int ret;
1014         struct resource *res;
1015 
1016         /* If we have ACPI based watchdog use that instead */
1017         if (acpi_has_watchdog())
1018                 return -ENODEV;
1019 
1020         /* Setup power management base register */
1021         pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
1022         base_addr = base_addr_cfg & 0x0000ff80;
1023         if (!base_addr) {
1024                 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
1025                 ret = -ENODEV;
1026                 goto wdt_done;
1027         }
1028 
1029         res = wdt_io_res(ICH_RES_IO_TCO);
1030         res->start = base_addr + ACPIBASE_TCO_OFF;
1031         res->end = base_addr + ACPIBASE_TCO_END;
1032 
1033         res = wdt_io_res(ICH_RES_IO_SMI);
1034         res->start = base_addr + ACPIBASE_SMI_OFF;
1035         res->end = base_addr + ACPIBASE_SMI_END;
1036 
1037         lpc_ich_enable_acpi_space(dev);
1038 
1039         /*
1040          * iTCO v2:
1041          * Get the Memory-Mapped GCS register. To get access to it
1042          * we have to read RCBA from PCI Config space 0xf0 and use
1043          * it as base. GCS = RCBA + ICH6_GCS(0x3410).
1044          *
1045          * iTCO v3:
1046          * Get the Power Management Configuration register.  To get access
1047          * to it we have to read the PMC BASE from config space and address
1048          * the register at offset 0x8.
1049          */
1050         if (lpc_chipset_info[priv->chipset].iTCO_version == 1) {
1051                 /* Don't register iomem for TCO ver 1 */
1052                 lpc_ich_wdt_cell.num_resources--;
1053         } else if (lpc_chipset_info[priv->chipset].iTCO_version == 2) {
1054                 pci_read_config_dword(dev, RCBABASE, &base_addr_cfg);
1055                 base_addr = base_addr_cfg & 0xffffc000;
1056                 if (!(base_addr_cfg & 1)) {
1057                         dev_notice(&dev->dev, "RCBA is disabled by "
1058                                         "hardware/BIOS, device disabled\n");
1059                         ret = -ENODEV;
1060                         goto wdt_done;
1061                 }
1062                 res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
1063                 res->start = base_addr + ACPIBASE_GCS_OFF;
1064                 res->end = base_addr + ACPIBASE_GCS_END;
1065         } else if (lpc_chipset_info[priv->chipset].iTCO_version == 3) {
1066                 lpc_ich_enable_pmc_space(dev);
1067                 pci_read_config_dword(dev, ACPICTRL_PMCBASE, &base_addr_cfg);
1068                 base_addr = base_addr_cfg & 0xfffffe00;
1069 
1070                 res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
1071                 res->start = base_addr + ACPIBASE_PMC_OFF;
1072                 res->end = base_addr + ACPIBASE_PMC_END;
1073         }
1074 
1075         ret = lpc_ich_finalize_wdt_cell(dev);
1076         if (ret)
1077                 goto wdt_done;
1078 
1079         ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO,
1080                               &lpc_ich_wdt_cell, 1, NULL, 0, NULL);
1081 
1082 wdt_done:
1083         return ret;
1084 }
1085 
1086 static int lpc_ich_init_spi(struct pci_dev *dev)
1087 {
1088         struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1089         struct resource *res = &intel_spi_res[0];
1090         struct intel_spi_boardinfo *info;
1091         u32 spi_base, rcba, bcr;
1092 
1093         info = devm_kzalloc(&dev->dev, sizeof(*info), GFP_KERNEL);
1094         if (!info)
1095                 return -ENOMEM;
1096 
1097         info->type = lpc_chipset_info[priv->chipset].spi_type;
1098 
1099         switch (info->type) {
1100         case INTEL_SPI_BYT:
1101                 pci_read_config_dword(dev, SPIBASE_BYT, &spi_base);
1102                 if (spi_base & SPIBASE_BYT_EN) {
1103                         res->start = spi_base & ~(SPIBASE_BYT_SZ - 1);
1104                         res->end = res->start + SPIBASE_BYT_SZ - 1;
1105                 }
1106                 break;
1107 
1108         case INTEL_SPI_LPT:
1109                 pci_read_config_dword(dev, RCBABASE, &rcba);
1110                 if (rcba & 1) {
1111                         spi_base = round_down(rcba, SPIBASE_LPT_SZ);
1112                         res->start = spi_base + SPIBASE_LPT;
1113                         res->end = res->start + SPIBASE_LPT_SZ - 1;
1114 
1115                         pci_read_config_dword(dev, BCR, &bcr);
1116                         info->writeable = !!(bcr & BCR_WPD);
1117                 }
1118                 break;
1119 
1120         case INTEL_SPI_BXT: {
1121                 unsigned int p2sb = PCI_DEVFN(13, 0);
1122                 unsigned int spi = PCI_DEVFN(13, 2);
1123                 struct pci_bus *bus = dev->bus;
1124 
1125                 /*
1126                  * The P2SB is hidden by BIOS and we need to unhide it in
1127                  * order to read BAR of the SPI flash device. Once that is
1128                  * done we hide it again.
1129                  */
1130                 pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x0);
1131                 pci_bus_read_config_dword(bus, spi, PCI_BASE_ADDRESS_0,
1132                                           &spi_base);
1133                 if (spi_base != ~0) {
1134                         res->start = spi_base & 0xfffffff0;
1135                         res->end = res->start + SPIBASE_APL_SZ - 1;
1136 
1137                         pci_bus_read_config_dword(bus, spi, BCR, &bcr);
1138                         info->writeable = !!(bcr & BCR_WPD);
1139                 }
1140 
1141                 pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x1);
1142                 break;
1143         }
1144 
1145         default:
1146                 return -EINVAL;
1147         }
1148 
1149         if (!res->start)
1150                 return -ENODEV;
1151 
1152         lpc_ich_spi_cell.platform_data = info;
1153         lpc_ich_spi_cell.pdata_size = sizeof(*info);
1154 
1155         return mfd_add_devices(&dev->dev, PLATFORM_DEVID_NONE,
1156                                &lpc_ich_spi_cell, 1, NULL, 0, NULL);
1157 }
1158 
1159 static int lpc_ich_probe(struct pci_dev *dev,
1160                                 const struct pci_device_id *id)
1161 {
1162         struct lpc_ich_priv *priv;
1163         int ret;
1164         bool cell_added = false;
1165 
1166         priv = devm_kzalloc(&dev->dev,
1167                             sizeof(struct lpc_ich_priv), GFP_KERNEL);
1168         if (!priv)
1169                 return -ENOMEM;
1170 
1171         priv->chipset = id->driver_data;
1172 
1173         priv->actrl_pbase_save = -1;
1174         priv->abase_save = -1;
1175 
1176         priv->abase = ACPIBASE;
1177         priv->actrl_pbase = ACPICTRL_PMCBASE;
1178 
1179         priv->gctrl_save = -1;
1180         if (priv->chipset <= LPC_ICH5) {
1181                 priv->gbase = GPIOBASE_ICH0;
1182                 priv->gctrl = GPIOCTRL_ICH0;
1183         } else {
1184                 priv->gbase = GPIOBASE_ICH6;
1185                 priv->gctrl = GPIOCTRL_ICH6;
1186         }
1187 
1188         pci_set_drvdata(dev, priv);
1189 
1190         if (lpc_chipset_info[priv->chipset].iTCO_version) {
1191                 ret = lpc_ich_init_wdt(dev);
1192                 if (!ret)
1193                         cell_added = true;
1194         }
1195 
1196         if (lpc_chipset_info[priv->chipset].gpio_version) {
1197                 ret = lpc_ich_init_gpio(dev);
1198                 if (!ret)
1199                         cell_added = true;
1200         }
1201 
1202         if (lpc_chipset_info[priv->chipset].spi_type) {
1203                 ret = lpc_ich_init_spi(dev);
1204                 if (!ret)
1205                         cell_added = true;
1206         }
1207 
1208         /*
1209          * We only care if at least one or none of the cells registered
1210          * successfully.
1211          */
1212         if (!cell_added) {
1213                 dev_warn(&dev->dev, "No MFD cells added\n");
1214                 lpc_ich_restore_config_space(dev);
1215                 return -ENODEV;
1216         }
1217 
1218         return 0;
1219 }
1220 
1221 static void lpc_ich_remove(struct pci_dev *dev)
1222 {
1223         mfd_remove_devices(&dev->dev);
1224         lpc_ich_restore_config_space(dev);
1225 }
1226 
1227 static struct pci_driver lpc_ich_driver = {
1228         .name           = "lpc_ich",
1229         .id_table       = lpc_ich_ids,
1230         .probe          = lpc_ich_probe,
1231         .remove         = lpc_ich_remove,
1232 };
1233 
1234 module_pci_driver(lpc_ich_driver);
1235 
1236 MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>");
1237 MODULE_DESCRIPTION("LPC interface for Intel ICH");
1238 MODULE_LICENSE("GPL");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/mfd/lpc_ich.c

DEFINITIONS
