This source file includes following definitions.
- ezx_pcap_putget
- ezx_pcap_write
- ezx_pcap_read
- ezx_pcap_set_bits
- irq_to_pcap
- pcap_to_irq
- pcap_mask_irq
- pcap_unmask_irq
- pcap_msr_work
- pcap_isr_work
- pcap_irq_handler
- pcap_set_ts_bits
- pcap_disable_adc
- pcap_adc_trigger
- pcap_adc_irq
- pcap_adc_async
- pcap_adc_sync_cb
- pcap_adc_sync
- pcap_remove_subdev
- pcap_add_subdev
- ezx_pcap_remove
- ezx_pcap_probe
- ezx_pcap_init
- ezx_pcap_exit
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7
8
9 #include <linux/module.h>
10 #include <linux/kernel.h>
11 #include <linux/platform_device.h>
12 #include <linux/interrupt.h>
13 #include <linux/irq.h>
14 #include <linux/mfd/ezx-pcap.h>
15 #include <linux/spi/spi.h>
16 #include <linux/gpio.h>
17 #include <linux/slab.h>
18
19 #define PCAP_ADC_MAXQ 8
20 struct pcap_adc_request {
21 u8 bank;
22 u8 ch[2];
23 u32 flags;
24 void (*callback)(void *, u16[]);
25 void *data;
26 };
27
28 struct pcap_adc_sync_request {
29 u16 res[2];
30 struct completion completion;
31 };
32
33 struct pcap_chip {
34 struct spi_device *spi;
35
36
37 u32 buf;
38 spinlock_t io_lock;
39
40
41 unsigned int irq_base;
42 u32 msr;
43 struct work_struct isr_work;
44 struct work_struct msr_work;
45 struct workqueue_struct *workqueue;
46
47
48 struct pcap_adc_request *adc_queue[PCAP_ADC_MAXQ];
49 u8 adc_head;
50 u8 adc_tail;
51 spinlock_t adc_lock;
52 };
53
54
55 static int ezx_pcap_putget(struct pcap_chip *pcap, u32 *data)
56 {
57 struct spi_transfer t;
58 struct spi_message m;
59 int status;
60
61 memset(&t, 0, sizeof(t));
62 spi_message_init(&m);
63 t.len = sizeof(u32);
64 spi_message_add_tail(&t, &m);
65
66 pcap->buf = *data;
67 t.tx_buf = (u8 *) &pcap->buf;
68 t.rx_buf = (u8 *) &pcap->buf;
69 status = spi_sync(pcap->spi, &m);
70
71 if (status == 0)
72 *data = pcap->buf;
73
74 return status;
75 }
76
77 int ezx_pcap_write(struct pcap_chip *pcap, u8 reg_num, u32 value)
78 {
79 unsigned long flags;
80 int ret;
81
82 spin_lock_irqsave(&pcap->io_lock, flags);
83 value &= PCAP_REGISTER_VALUE_MASK;
84 value |= PCAP_REGISTER_WRITE_OP_BIT
85 | (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
86 ret = ezx_pcap_putget(pcap, &value);
87 spin_unlock_irqrestore(&pcap->io_lock, flags);
88
89 return ret;
90 }
91 EXPORT_SYMBOL_GPL(ezx_pcap_write);
92
93 int ezx_pcap_read(struct pcap_chip *pcap, u8 reg_num, u32 *value)
94 {
95 unsigned long flags;
96 int ret;
97
98 spin_lock_irqsave(&pcap->io_lock, flags);
99 *value = PCAP_REGISTER_READ_OP_BIT
100 | (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
101
102 ret = ezx_pcap_putget(pcap, value);
103 spin_unlock_irqrestore(&pcap->io_lock, flags);
104
105 return ret;
106 }
107 EXPORT_SYMBOL_GPL(ezx_pcap_read);
108
109 int ezx_pcap_set_bits(struct pcap_chip *pcap, u8 reg_num, u32 mask, u32 val)
110 {
111 unsigned long flags;
112 int ret;
113 u32 tmp = PCAP_REGISTER_READ_OP_BIT |
114 (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
115
116 spin_lock_irqsave(&pcap->io_lock, flags);
117 ret = ezx_pcap_putget(pcap, &tmp);
118 if (ret)
119 goto out_unlock;
120
121 tmp &= (PCAP_REGISTER_VALUE_MASK & ~mask);
122 tmp |= (val & mask) | PCAP_REGISTER_WRITE_OP_BIT |
123 (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
124
125 ret = ezx_pcap_putget(pcap, &tmp);
126 out_unlock:
127 spin_unlock_irqrestore(&pcap->io_lock, flags);
128
129 return ret;
130 }
131 EXPORT_SYMBOL_GPL(ezx_pcap_set_bits);
132
133
134 int irq_to_pcap(struct pcap_chip *pcap, int irq)
135 {
136 return irq - pcap->irq_base;
137 }
138 EXPORT_SYMBOL_GPL(irq_to_pcap);
139
140 int pcap_to_irq(struct pcap_chip *pcap, int irq)
141 {
142 return pcap->irq_base + irq;
143 }
144 EXPORT_SYMBOL_GPL(pcap_to_irq);
145
146 static void pcap_mask_irq(struct irq_data *d)
147 {
148 struct pcap_chip *pcap = irq_data_get_irq_chip_data(d);
149
150 pcap->msr |= 1 << irq_to_pcap(pcap, d->irq);
151 queue_work(pcap->workqueue, &pcap->msr_work);
152 }
153
154 static void pcap_unmask_irq(struct irq_data *d)
155 {
156 struct pcap_chip *pcap = irq_data_get_irq_chip_data(d);
157
158 pcap->msr &= ~(1 << irq_to_pcap(pcap, d->irq));
159 queue_work(pcap->workqueue, &pcap->msr_work);
160 }
161
162 static struct irq_chip pcap_irq_chip = {
163 .name = "pcap",
164 .irq_disable = pcap_mask_irq,
165 .irq_mask = pcap_mask_irq,
166 .irq_unmask = pcap_unmask_irq,
167 };
168
169 static void pcap_msr_work(struct work_struct *work)
170 {
171 struct pcap_chip *pcap = container_of(work, struct pcap_chip, msr_work);
172
173 ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);
174 }
175
176 static void pcap_isr_work(struct work_struct *work)
177 {
178 struct pcap_chip *pcap = container_of(work, struct pcap_chip, isr_work);
179 struct pcap_platform_data *pdata = dev_get_platdata(&pcap->spi->dev);
180 u32 msr, isr, int_sel, service;
181 int irq;
182
183 do {
184 ezx_pcap_read(pcap, PCAP_REG_MSR, &msr);
185 ezx_pcap_read(pcap, PCAP_REG_ISR, &isr);
186
187
188 if (!(pdata->config & PCAP_SECOND_PORT)) {
189 ezx_pcap_read(pcap, PCAP_REG_INT_SEL, &int_sel);
190 isr &= ~int_sel;
191 }
192
193 ezx_pcap_write(pcap, PCAP_REG_MSR, isr | msr);
194 ezx_pcap_write(pcap, PCAP_REG_ISR, isr);
195
196 local_irq_disable();
197 service = isr & ~msr;
198 for (irq = pcap->irq_base; service; service >>= 1, irq++) {
199 if (service & 1)
200 generic_handle_irq(irq);
201 }
202 local_irq_enable();
203 ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);
204 } while (gpio_get_value(pdata->gpio));
205 }
206
207 static void pcap_irq_handler(struct irq_desc *desc)
208 {
209 struct pcap_chip *pcap = irq_desc_get_handler_data(desc);
210
211 desc->irq_data.chip->irq_ack(&desc->irq_data);
212 queue_work(pcap->workqueue, &pcap->isr_work);
213 }
214
215
216 void pcap_set_ts_bits(struct pcap_chip *pcap, u32 bits)
217 {
218 unsigned long flags;
219 u32 tmp;
220
221 spin_lock_irqsave(&pcap->adc_lock, flags);
222 ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
223 tmp &= ~(PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
224 tmp |= bits & (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
225 ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
226 spin_unlock_irqrestore(&pcap->adc_lock, flags);
227 }
228 EXPORT_SYMBOL_GPL(pcap_set_ts_bits);
229
230 static void pcap_disable_adc(struct pcap_chip *pcap)
231 {
232 u32 tmp;
233
234 ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
235 tmp &= ~(PCAP_ADC_ADEN|PCAP_ADC_BATT_I_ADC|PCAP_ADC_BATT_I_POLARITY);
236 ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
237 }
238
239 static void pcap_adc_trigger(struct pcap_chip *pcap)
240 {
241 unsigned long flags;
242 u32 tmp;
243 u8 head;
244
245 spin_lock_irqsave(&pcap->adc_lock, flags);
246 head = pcap->adc_head;
247 if (!pcap->adc_queue[head]) {
248
249 pcap_disable_adc(pcap);
250 spin_unlock_irqrestore(&pcap->adc_lock, flags);
251 return;
252 }
253
254 ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
255 tmp &= (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);
256 tmp |= pcap->adc_queue[head]->flags | PCAP_ADC_ADEN;
257
258 if (pcap->adc_queue[head]->bank == PCAP_ADC_BANK_1)
259 tmp |= PCAP_ADC_AD_SEL1;
260
261 ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
262 spin_unlock_irqrestore(&pcap->adc_lock, flags);
263 ezx_pcap_write(pcap, PCAP_REG_ADR, PCAP_ADR_ASC);
264 }
265
266 static irqreturn_t pcap_adc_irq(int irq, void *_pcap)
267 {
268 struct pcap_chip *pcap = _pcap;
269 struct pcap_adc_request *req;
270 u16 res[2];
271 u32 tmp;
272
273 spin_lock(&pcap->adc_lock);
274 req = pcap->adc_queue[pcap->adc_head];
275
276 if (WARN(!req, "adc irq without pending request\n")) {
277 spin_unlock(&pcap->adc_lock);
278 return IRQ_HANDLED;
279 }
280
281
282 ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
283 tmp &= ~(PCAP_ADC_ADA1_MASK | PCAP_ADC_ADA2_MASK);
284 tmp |= (req->ch[0] << PCAP_ADC_ADA1_SHIFT);
285 tmp |= (req->ch[1] << PCAP_ADC_ADA2_SHIFT);
286 ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
287 ezx_pcap_read(pcap, PCAP_REG_ADR, &tmp);
288 res[0] = (tmp & PCAP_ADR_ADD1_MASK) >> PCAP_ADR_ADD1_SHIFT;
289 res[1] = (tmp & PCAP_ADR_ADD2_MASK) >> PCAP_ADR_ADD2_SHIFT;
290
291 pcap->adc_queue[pcap->adc_head] = NULL;
292 pcap->adc_head = (pcap->adc_head + 1) & (PCAP_ADC_MAXQ - 1);
293 spin_unlock(&pcap->adc_lock);
294
295
296 req->callback(req->data, res);
297 kfree(req);
298
299
300 pcap_adc_trigger(pcap);
301
302 return IRQ_HANDLED;
303 }
304
305 int pcap_adc_async(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[],
306 void *callback, void *data)
307 {
308 struct pcap_adc_request *req;
309 unsigned long irq_flags;
310
311
312 req = kmalloc(sizeof(struct pcap_adc_request), GFP_KERNEL);
313 if (!req)
314 return -ENOMEM;
315
316 req->bank = bank;
317 req->flags = flags;
318 req->ch[0] = ch[0];
319 req->ch[1] = ch[1];
320 req->callback = callback;
321 req->data = data;
322
323 spin_lock_irqsave(&pcap->adc_lock, irq_flags);
324 if (pcap->adc_queue[pcap->adc_tail]) {
325 spin_unlock_irqrestore(&pcap->adc_lock, irq_flags);
326 kfree(req);
327 return -EBUSY;
328 }
329 pcap->adc_queue[pcap->adc_tail] = req;
330 pcap->adc_tail = (pcap->adc_tail + 1) & (PCAP_ADC_MAXQ - 1);
331 spin_unlock_irqrestore(&pcap->adc_lock, irq_flags);
332
333
334 pcap_adc_trigger(pcap);
335
336 return 0;
337 }
338 EXPORT_SYMBOL_GPL(pcap_adc_async);
339
340 static void pcap_adc_sync_cb(void *param, u16 res[])
341 {
342 struct pcap_adc_sync_request *req = param;
343
344 req->res[0] = res[0];
345 req->res[1] = res[1];
346 complete(&req->completion);
347 }
348
349 int pcap_adc_sync(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[],
350 u16 res[])
351 {
352 struct pcap_adc_sync_request sync_data;
353 int ret;
354
355 init_completion(&sync_data.completion);
356 ret = pcap_adc_async(pcap, bank, flags, ch, pcap_adc_sync_cb,
357 &sync_data);
358 if (ret)
359 return ret;
360 wait_for_completion(&sync_data.completion);
361 res[0] = sync_data.res[0];
362 res[1] = sync_data.res[1];
363
364 return 0;
365 }
366 EXPORT_SYMBOL_GPL(pcap_adc_sync);
367
368
369 static int pcap_remove_subdev(struct device *dev, void *unused)
370 {
371 platform_device_unregister(to_platform_device(dev));
372 return 0;
373 }
374
375 static int pcap_add_subdev(struct pcap_chip *pcap,
376 struct pcap_subdev *subdev)
377 {
378 struct platform_device *pdev;
379 int ret;
380
381 pdev = platform_device_alloc(subdev->name, subdev->id);
382 if (!pdev)
383 return -ENOMEM;
384
385 pdev->dev.parent = &pcap->spi->dev;
386 pdev->dev.platform_data = subdev->platform_data;
387
388 ret = platform_device_add(pdev);
389 if (ret)
390 platform_device_put(pdev);
391
392 return ret;
393 }
394
395 static int ezx_pcap_remove(struct spi_device *spi)
396 {
397 struct pcap_chip *pcap = spi_get_drvdata(spi);
398 unsigned long flags;
399 int i;
400
401
402 device_for_each_child(&spi->dev, NULL, pcap_remove_subdev);
403
404
405 spin_lock_irqsave(&pcap->adc_lock, flags);
406 for (i = 0; i < PCAP_ADC_MAXQ; i++)
407 kfree(pcap->adc_queue[i]);
408 spin_unlock_irqrestore(&pcap->adc_lock, flags);
409
410
411 for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)
412 irq_set_chip_and_handler(i, NULL, NULL);
413
414 destroy_workqueue(pcap->workqueue);
415
416 return 0;
417 }
418
419 static int ezx_pcap_probe(struct spi_device *spi)
420 {
421 struct pcap_platform_data *pdata = dev_get_platdata(&spi->dev);
422 struct pcap_chip *pcap;
423 int i, adc_irq;
424 int ret = -ENODEV;
425
426
427 if (!pdata)
428 goto ret;
429
430 pcap = devm_kzalloc(&spi->dev, sizeof(*pcap), GFP_KERNEL);
431 if (!pcap) {
432 ret = -ENOMEM;
433 goto ret;
434 }
435
436 spin_lock_init(&pcap->io_lock);
437 spin_lock_init(&pcap->adc_lock);
438 INIT_WORK(&pcap->isr_work, pcap_isr_work);
439 INIT_WORK(&pcap->msr_work, pcap_msr_work);
440 spi_set_drvdata(spi, pcap);
441
442
443 spi->bits_per_word = 32;
444 spi->mode = SPI_MODE_0 | (pdata->config & PCAP_CS_AH ? SPI_CS_HIGH : 0);
445 ret = spi_setup(spi);
446 if (ret)
447 goto ret;
448
449 pcap->spi = spi;
450
451
452 pcap->irq_base = pdata->irq_base;
453 pcap->workqueue = create_singlethread_workqueue("pcapd");
454 if (!pcap->workqueue) {
455 ret = -ENOMEM;
456 dev_err(&spi->dev, "can't create pcap thread\n");
457 goto ret;
458 }
459
460
461 if (!(pdata->config & PCAP_SECOND_PORT))
462 ezx_pcap_write(pcap, PCAP_REG_INT_SEL,
463 (1 << PCAP_IRQ_ADCDONE2));
464
465
466 for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++) {
467 irq_set_chip_and_handler(i, &pcap_irq_chip, handle_simple_irq);
468 irq_set_chip_data(i, pcap);
469 irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE);
470 }
471
472
473 ezx_pcap_write(pcap, PCAP_REG_MSR, PCAP_MASK_ALL_INTERRUPT);
474 ezx_pcap_write(pcap, PCAP_REG_ISR, PCAP_CLEAR_INTERRUPT_REGISTER);
475 pcap->msr = PCAP_MASK_ALL_INTERRUPT;
476
477 irq_set_irq_type(spi->irq, IRQ_TYPE_EDGE_RISING);
478 irq_set_chained_handler_and_data(spi->irq, pcap_irq_handler, pcap);
479 irq_set_irq_wake(spi->irq, 1);
480
481
482 adc_irq = pcap_to_irq(pcap, (pdata->config & PCAP_SECOND_PORT) ?
483 PCAP_IRQ_ADCDONE2 : PCAP_IRQ_ADCDONE);
484
485 ret = devm_request_irq(&spi->dev, adc_irq, pcap_adc_irq, 0, "ADC",
486 pcap);
487 if (ret)
488 goto free_irqchip;
489
490
491 for (i = 0; i < pdata->num_subdevs; i++) {
492 ret = pcap_add_subdev(pcap, &pdata->subdevs[i]);
493 if (ret)
494 goto remove_subdevs;
495 }
496
497
498 if (pdata->init)
499 pdata->init(pcap);
500
501 return 0;
502
503 remove_subdevs:
504 device_for_each_child(&spi->dev, NULL, pcap_remove_subdev);
505 free_irqchip:
506 for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)
507 irq_set_chip_and_handler(i, NULL, NULL);
508
509 destroy_workqueue(pcap->workqueue);
510 ret:
511 return ret;
512 }
513
514 static struct spi_driver ezxpcap_driver = {
515 .probe = ezx_pcap_probe,
516 .remove = ezx_pcap_remove,
517 .driver = {
518 .name = "ezx-pcap",
519 },
520 };
521
522 static int __init ezx_pcap_init(void)
523 {
524 return spi_register_driver(&ezxpcap_driver);
525 }
526
527 static void __exit ezx_pcap_exit(void)
528 {
529 spi_unregister_driver(&ezxpcap_driver);
530 }
531
532 subsys_initcall(ezx_pcap_init);
533 module_exit(ezx_pcap_exit);
534
535 MODULE_LICENSE("GPL");
536 MODULE_AUTHOR("Daniel Ribeiro / Harald Welte");
537 MODULE_DESCRIPTION("Motorola PCAP2 ASIC Driver");
538 MODULE_ALIAS("spi:ezx-pcap");