drivers/mfd/db8500-prcmu.c

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
db8500_prcmu_enable_dsipll
db8500_prcmu_disable_dsipll
db8500_prcmu_set_display_clocks
db8500_prcmu_read
db8500_prcmu_write
db8500_prcmu_write_masked
prcmu_get_fw_version
prcmu_has_arm_maxopp
prcmu_set_rc_a2p
prcmu_get_rc_p2a
prcmu_get_xp70_current_state
prcmu_config_clkout
db8500_prcmu_set_power_state
db8500_prcmu_get_power_state_result
config_wakeups
db8500_prcmu_enable_wakeups
db8500_prcmu_config_abb_event_readout
db8500_prcmu_get_abb_event_buffer
db8500_prcmu_set_arm_opp
db8500_prcmu_get_arm_opp
db8500_prcmu_get_ddr_opp
request_even_slower_clocks
db8500_prcmu_set_ape_opp
db8500_prcmu_get_ape_opp
db8500_prcmu_request_ape_opp_100_voltage
prcmu_release_usb_wakeup_state
request_pll
db8500_prcmu_set_epod
prcmu_configure_auto_pm
prcmu_is_auto_pm_enabled
request_sysclk
request_timclk
request_clock
request_sga_clock
plldsi_locked
request_plldsi
request_dsiclk
request_dsiescclk
db8500_prcmu_request_clock
pll_rate
clock_rate
armss_rate
dsiclk_rate
dsiescclk_rate
prcmu_clock_rate
clock_source_rate
clock_divider
round_clock_rate
round_armss_rate
round_plldsi_rate
round_dsiclk_rate
round_dsiescclk_rate
prcmu_round_clock_rate
set_clock_rate
set_armss_rate
set_plldsi_rate
set_dsiclk_rate
set_dsiescclk_rate
prcmu_set_clock_rate
db8500_prcmu_config_esram0_deep_sleep
db8500_prcmu_config_hotdog
db8500_prcmu_config_hotmon
config_hot_period
db8500_prcmu_start_temp_sense
db8500_prcmu_stop_temp_sense
prcmu_a9wdog
db8500_prcmu_config_a9wdog
db8500_prcmu_enable_a9wdog
db8500_prcmu_disable_a9wdog
db8500_prcmu_kick_a9wdog
db8500_prcmu_load_a9wdog
prcmu_abb_read
prcmu_abb_write_masked
prcmu_abb_write
prcmu_ac_wake_req
prcmu_ac_sleep_req
db8500_prcmu_is_ac_wake_requested
db8500_prcmu_system_reset
db8500_prcmu_get_reset_code
db8500_prcmu_modem_reset
ack_dbb_wakeup
print_unknown_header_warning
read_mailbox_0
read_mailbox_1
read_mailbox_2
read_mailbox_3
read_mailbox_4
read_mailbox_5
read_mailbox_6
read_mailbox_7
prcmu_irq_handler
prcmu_irq_thread_fn
prcmu_mask_work
prcmu_irq_mask
prcmu_irq_unmask
noop
fw_project_name
db8500_irq_map
db8500_irq_init
dbx500_fw_version_init
db8500_prcmu_early_init
init_prcm_registers
db8500_prcmu_register_ab8500
db8500_prcmu_probe
db8500_prcmu_init
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * DB8500 PRCM Unit driver
   4  *
   5  * Copyright (C) STMicroelectronics 2009
   6  * Copyright (C) ST-Ericsson SA 2010
   7  *
   8  * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
   9  * Author: Sundar Iyer <sundar.iyer@stericsson.com>
  10  * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
  11  *
  12  * U8500 PRCM Unit interface driver
  13  */
  14 #include <linux/init.h>
  15 #include <linux/export.h>
  16 #include <linux/kernel.h>
  17 #include <linux/delay.h>
  18 #include <linux/errno.h>
  19 #include <linux/err.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/io.h>
  22 #include <linux/slab.h>
  23 #include <linux/mutex.h>
  24 #include <linux/completion.h>
  25 #include <linux/irq.h>
  26 #include <linux/jiffies.h>
  27 #include <linux/bitops.h>
  28 #include <linux/fs.h>
  29 #include <linux/of.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/uaccess.h>
  33 #include <linux/mfd/core.h>
  34 #include <linux/mfd/dbx500-prcmu.h>
  35 #include <linux/mfd/abx500/ab8500.h>
  36 #include <linux/regulator/db8500-prcmu.h>
  37 #include <linux/regulator/machine.h>
  38 #include <linux/platform_data/ux500_wdt.h>
  39 #include "dbx500-prcmu-regs.h"
  40 
  41 /* Index of different voltages to be used when accessing AVSData */
  42 #define PRCM_AVS_BASE           0x2FC
  43 #define PRCM_AVS_VBB_RET        (PRCM_AVS_BASE + 0x0)
  44 #define PRCM_AVS_VBB_MAX_OPP    (PRCM_AVS_BASE + 0x1)
  45 #define PRCM_AVS_VBB_100_OPP    (PRCM_AVS_BASE + 0x2)
  46 #define PRCM_AVS_VBB_50_OPP     (PRCM_AVS_BASE + 0x3)
  47 #define PRCM_AVS_VARM_MAX_OPP   (PRCM_AVS_BASE + 0x4)
  48 #define PRCM_AVS_VARM_100_OPP   (PRCM_AVS_BASE + 0x5)
  49 #define PRCM_AVS_VARM_50_OPP    (PRCM_AVS_BASE + 0x6)
  50 #define PRCM_AVS_VARM_RET       (PRCM_AVS_BASE + 0x7)
  51 #define PRCM_AVS_VAPE_100_OPP   (PRCM_AVS_BASE + 0x8)
  52 #define PRCM_AVS_VAPE_50_OPP    (PRCM_AVS_BASE + 0x9)
  53 #define PRCM_AVS_VMOD_100_OPP   (PRCM_AVS_BASE + 0xA)
  54 #define PRCM_AVS_VMOD_50_OPP    (PRCM_AVS_BASE + 0xB)
  55 #define PRCM_AVS_VSAFE          (PRCM_AVS_BASE + 0xC)
  56 
  57 #define PRCM_AVS_VOLTAGE                0
  58 #define PRCM_AVS_VOLTAGE_MASK           0x3f
  59 #define PRCM_AVS_ISSLOWSTARTUP          6
  60 #define PRCM_AVS_ISSLOWSTARTUP_MASK     (1 << PRCM_AVS_ISSLOWSTARTUP)
  61 #define PRCM_AVS_ISMODEENABLE           7
  62 #define PRCM_AVS_ISMODEENABLE_MASK      (1 << PRCM_AVS_ISMODEENABLE)
  63 
  64 #define PRCM_BOOT_STATUS        0xFFF
  65 #define PRCM_ROMCODE_A2P        0xFFE
  66 #define PRCM_ROMCODE_P2A        0xFFD
  67 #define PRCM_XP70_CUR_PWR_STATE 0xFFC      /* 4 BYTES */
  68 
  69 #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */
  70 
  71 #define _PRCM_MBOX_HEADER               0xFE8 /* 16 bytes */
  72 #define PRCM_MBOX_HEADER_REQ_MB0        (_PRCM_MBOX_HEADER + 0x0)
  73 #define PRCM_MBOX_HEADER_REQ_MB1        (_PRCM_MBOX_HEADER + 0x1)
  74 #define PRCM_MBOX_HEADER_REQ_MB2        (_PRCM_MBOX_HEADER + 0x2)
  75 #define PRCM_MBOX_HEADER_REQ_MB3        (_PRCM_MBOX_HEADER + 0x3)
  76 #define PRCM_MBOX_HEADER_REQ_MB4        (_PRCM_MBOX_HEADER + 0x4)
  77 #define PRCM_MBOX_HEADER_REQ_MB5        (_PRCM_MBOX_HEADER + 0x5)
  78 #define PRCM_MBOX_HEADER_ACK_MB0        (_PRCM_MBOX_HEADER + 0x8)
  79 
  80 /* Req Mailboxes */
  81 #define PRCM_REQ_MB0 0xFDC /* 12 bytes  */
  82 #define PRCM_REQ_MB1 0xFD0 /* 12 bytes  */
  83 #define PRCM_REQ_MB2 0xFC0 /* 16 bytes  */
  84 #define PRCM_REQ_MB3 0xE4C /* 372 bytes  */
  85 #define PRCM_REQ_MB4 0xE48 /* 4 bytes  */
  86 #define PRCM_REQ_MB5 0xE44 /* 4 bytes  */
  87 
  88 /* Ack Mailboxes */
  89 #define PRCM_ACK_MB0 0xE08 /* 52 bytes  */
  90 #define PRCM_ACK_MB1 0xE04 /* 4 bytes */
  91 #define PRCM_ACK_MB2 0xE00 /* 4 bytes */
  92 #define PRCM_ACK_MB3 0xDFC /* 4 bytes */
  93 #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */
  94 #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */
  95 
  96 /* Mailbox 0 headers */
  97 #define MB0H_POWER_STATE_TRANS          0
  98 #define MB0H_CONFIG_WAKEUPS_EXE         1
  99 #define MB0H_READ_WAKEUP_ACK            3
 100 #define MB0H_CONFIG_WAKEUPS_SLEEP       4
 101 
 102 #define MB0H_WAKEUP_EXE 2
 103 #define MB0H_WAKEUP_SLEEP 5
 104 
 105 /* Mailbox 0 REQs */
 106 #define PRCM_REQ_MB0_AP_POWER_STATE     (PRCM_REQ_MB0 + 0x0)
 107 #define PRCM_REQ_MB0_AP_PLL_STATE       (PRCM_REQ_MB0 + 0x1)
 108 #define PRCM_REQ_MB0_ULP_CLOCK_STATE    (PRCM_REQ_MB0 + 0x2)
 109 #define PRCM_REQ_MB0_DO_NOT_WFI         (PRCM_REQ_MB0 + 0x3)
 110 #define PRCM_REQ_MB0_WAKEUP_8500        (PRCM_REQ_MB0 + 0x4)
 111 #define PRCM_REQ_MB0_WAKEUP_4500        (PRCM_REQ_MB0 + 0x8)
 112 
 113 /* Mailbox 0 ACKs */
 114 #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS  (PRCM_ACK_MB0 + 0x0)
 115 #define PRCM_ACK_MB0_READ_POINTER       (PRCM_ACK_MB0 + 0x1)
 116 #define PRCM_ACK_MB0_WAKEUP_0_8500      (PRCM_ACK_MB0 + 0x4)
 117 #define PRCM_ACK_MB0_WAKEUP_0_4500      (PRCM_ACK_MB0 + 0x8)
 118 #define PRCM_ACK_MB0_WAKEUP_1_8500      (PRCM_ACK_MB0 + 0x1C)
 119 #define PRCM_ACK_MB0_WAKEUP_1_4500      (PRCM_ACK_MB0 + 0x20)
 120 #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20
 121 
 122 /* Mailbox 1 headers */
 123 #define MB1H_ARM_APE_OPP 0x0
 124 #define MB1H_RESET_MODEM 0x2
 125 #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3
 126 #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4
 127 #define MB1H_RELEASE_USB_WAKEUP 0x5
 128 #define MB1H_PLL_ON_OFF 0x6
 129 
 130 /* Mailbox 1 Requests */
 131 #define PRCM_REQ_MB1_ARM_OPP                    (PRCM_REQ_MB1 + 0x0)
 132 #define PRCM_REQ_MB1_APE_OPP                    (PRCM_REQ_MB1 + 0x1)
 133 #define PRCM_REQ_MB1_PLL_ON_OFF                 (PRCM_REQ_MB1 + 0x4)
 134 #define PLL_SOC0_OFF    0x1
 135 #define PLL_SOC0_ON     0x2
 136 #define PLL_SOC1_OFF    0x4
 137 #define PLL_SOC1_ON     0x8
 138 
 139 /* Mailbox 1 ACKs */
 140 #define PRCM_ACK_MB1_CURRENT_ARM_OPP    (PRCM_ACK_MB1 + 0x0)
 141 #define PRCM_ACK_MB1_CURRENT_APE_OPP    (PRCM_ACK_MB1 + 0x1)
 142 #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2)
 143 #define PRCM_ACK_MB1_DVFS_STATUS        (PRCM_ACK_MB1 + 0x3)
 144 
 145 /* Mailbox 2 headers */
 146 #define MB2H_DPS        0x0
 147 #define MB2H_AUTO_PWR   0x1
 148 
 149 /* Mailbox 2 REQs */
 150 #define PRCM_REQ_MB2_SVA_MMDSP          (PRCM_REQ_MB2 + 0x0)
 151 #define PRCM_REQ_MB2_SVA_PIPE           (PRCM_REQ_MB2 + 0x1)
 152 #define PRCM_REQ_MB2_SIA_MMDSP          (PRCM_REQ_MB2 + 0x2)
 153 #define PRCM_REQ_MB2_SIA_PIPE           (PRCM_REQ_MB2 + 0x3)
 154 #define PRCM_REQ_MB2_SGA                (PRCM_REQ_MB2 + 0x4)
 155 #define PRCM_REQ_MB2_B2R2_MCDE          (PRCM_REQ_MB2 + 0x5)
 156 #define PRCM_REQ_MB2_ESRAM12            (PRCM_REQ_MB2 + 0x6)
 157 #define PRCM_REQ_MB2_ESRAM34            (PRCM_REQ_MB2 + 0x7)
 158 #define PRCM_REQ_MB2_AUTO_PM_SLEEP      (PRCM_REQ_MB2 + 0x8)
 159 #define PRCM_REQ_MB2_AUTO_PM_IDLE       (PRCM_REQ_MB2 + 0xC)
 160 
 161 /* Mailbox 2 ACKs */
 162 #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0)
 163 #define HWACC_PWR_ST_OK 0xFE
 164 
 165 /* Mailbox 3 headers */
 166 #define MB3H_ANC        0x0
 167 #define MB3H_SIDETONE   0x1
 168 #define MB3H_SYSCLK     0xE
 169 
 170 /* Mailbox 3 Requests */
 171 #define PRCM_REQ_MB3_ANC_FIR_COEFF      (PRCM_REQ_MB3 + 0x0)
 172 #define PRCM_REQ_MB3_ANC_IIR_COEFF      (PRCM_REQ_MB3 + 0x20)
 173 #define PRCM_REQ_MB3_ANC_SHIFTER        (PRCM_REQ_MB3 + 0x60)
 174 #define PRCM_REQ_MB3_ANC_WARP           (PRCM_REQ_MB3 + 0x64)
 175 #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN  (PRCM_REQ_MB3 + 0x68)
 176 #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C)
 177 #define PRCM_REQ_MB3_SYSCLK_MGT         (PRCM_REQ_MB3 + 0x16C)
 178 
 179 /* Mailbox 4 headers */
 180 #define MB4H_DDR_INIT   0x0
 181 #define MB4H_MEM_ST     0x1
 182 #define MB4H_HOTDOG     0x12
 183 #define MB4H_HOTMON     0x13
 184 #define MB4H_HOT_PERIOD 0x14
 185 #define MB4H_A9WDOG_CONF 0x16
 186 #define MB4H_A9WDOG_EN   0x17
 187 #define MB4H_A9WDOG_DIS  0x18
 188 #define MB4H_A9WDOG_LOAD 0x19
 189 #define MB4H_A9WDOG_KICK 0x20
 190 
 191 /* Mailbox 4 Requests */
 192 #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE       (PRCM_REQ_MB4 + 0x0)
 193 #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE        (PRCM_REQ_MB4 + 0x1)
 194 #define PRCM_REQ_MB4_ESRAM0_ST                  (PRCM_REQ_MB4 + 0x3)
 195 #define PRCM_REQ_MB4_HOTDOG_THRESHOLD           (PRCM_REQ_MB4 + 0x0)
 196 #define PRCM_REQ_MB4_HOTMON_LOW                 (PRCM_REQ_MB4 + 0x0)
 197 #define PRCM_REQ_MB4_HOTMON_HIGH                (PRCM_REQ_MB4 + 0x1)
 198 #define PRCM_REQ_MB4_HOTMON_CONFIG              (PRCM_REQ_MB4 + 0x2)
 199 #define PRCM_REQ_MB4_HOT_PERIOD                 (PRCM_REQ_MB4 + 0x0)
 200 #define HOTMON_CONFIG_LOW                       BIT(0)
 201 #define HOTMON_CONFIG_HIGH                      BIT(1)
 202 #define PRCM_REQ_MB4_A9WDOG_0                   (PRCM_REQ_MB4 + 0x0)
 203 #define PRCM_REQ_MB4_A9WDOG_1                   (PRCM_REQ_MB4 + 0x1)
 204 #define PRCM_REQ_MB4_A9WDOG_2                   (PRCM_REQ_MB4 + 0x2)
 205 #define PRCM_REQ_MB4_A9WDOG_3                   (PRCM_REQ_MB4 + 0x3)
 206 #define A9WDOG_AUTO_OFF_EN                      BIT(7)
 207 #define A9WDOG_AUTO_OFF_DIS                     0
 208 #define A9WDOG_ID_MASK                          0xf
 209 
 210 /* Mailbox 5 Requests */
 211 #define PRCM_REQ_MB5_I2C_SLAVE_OP       (PRCM_REQ_MB5 + 0x0)
 212 #define PRCM_REQ_MB5_I2C_HW_BITS        (PRCM_REQ_MB5 + 0x1)
 213 #define PRCM_REQ_MB5_I2C_REG            (PRCM_REQ_MB5 + 0x2)
 214 #define PRCM_REQ_MB5_I2C_VAL            (PRCM_REQ_MB5 + 0x3)
 215 #define PRCMU_I2C_WRITE(slave) (((slave) << 1) | BIT(6))
 216 #define PRCMU_I2C_READ(slave) (((slave) << 1) | BIT(0) | BIT(6))
 217 #define PRCMU_I2C_STOP_EN               BIT(3)
 218 
 219 /* Mailbox 5 ACKs */
 220 #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1)
 221 #define PRCM_ACK_MB5_I2C_VAL    (PRCM_ACK_MB5 + 0x3)
 222 #define I2C_WR_OK 0x1
 223 #define I2C_RD_OK 0x2
 224 
 225 #define NUM_MB 8
 226 #define MBOX_BIT BIT
 227 #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
 228 
 229 /*
 230  * Wakeups/IRQs
 231  */
 232 
 233 #define WAKEUP_BIT_RTC BIT(0)
 234 #define WAKEUP_BIT_RTT0 BIT(1)
 235 #define WAKEUP_BIT_RTT1 BIT(2)
 236 #define WAKEUP_BIT_HSI0 BIT(3)
 237 #define WAKEUP_BIT_HSI1 BIT(4)
 238 #define WAKEUP_BIT_CA_WAKE BIT(5)
 239 #define WAKEUP_BIT_USB BIT(6)
 240 #define WAKEUP_BIT_ABB BIT(7)
 241 #define WAKEUP_BIT_ABB_FIFO BIT(8)
 242 #define WAKEUP_BIT_SYSCLK_OK BIT(9)
 243 #define WAKEUP_BIT_CA_SLEEP BIT(10)
 244 #define WAKEUP_BIT_AC_WAKE_ACK BIT(11)
 245 #define WAKEUP_BIT_SIDE_TONE_OK BIT(12)
 246 #define WAKEUP_BIT_ANC_OK BIT(13)
 247 #define WAKEUP_BIT_SW_ERROR BIT(14)
 248 #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15)
 249 #define WAKEUP_BIT_ARM BIT(17)
 250 #define WAKEUP_BIT_HOTMON_LOW BIT(18)
 251 #define WAKEUP_BIT_HOTMON_HIGH BIT(19)
 252 #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20)
 253 #define WAKEUP_BIT_GPIO0 BIT(23)
 254 #define WAKEUP_BIT_GPIO1 BIT(24)
 255 #define WAKEUP_BIT_GPIO2 BIT(25)
 256 #define WAKEUP_BIT_GPIO3 BIT(26)
 257 #define WAKEUP_BIT_GPIO4 BIT(27)
 258 #define WAKEUP_BIT_GPIO5 BIT(28)
 259 #define WAKEUP_BIT_GPIO6 BIT(29)
 260 #define WAKEUP_BIT_GPIO7 BIT(30)
 261 #define WAKEUP_BIT_GPIO8 BIT(31)
 262 
 263 static struct {
 264         bool valid;
 265         struct prcmu_fw_version version;
 266 } fw_info;
 267 
 268 static struct irq_domain *db8500_irq_domain;
 269 
 270 /*
 271  * This vector maps irq numbers to the bits in the bit field used in
 272  * communication with the PRCMU firmware.
 273  *
 274  * The reason for having this is to keep the irq numbers contiguous even though
 275  * the bits in the bit field are not. (The bits also have a tendency to move
 276  * around, to further complicate matters.)
 277  */
 278 #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name))
 279 #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name)
 280 
 281 #define IRQ_PRCMU_RTC 0
 282 #define IRQ_PRCMU_RTT0 1
 283 #define IRQ_PRCMU_RTT1 2
 284 #define IRQ_PRCMU_HSI0 3
 285 #define IRQ_PRCMU_HSI1 4
 286 #define IRQ_PRCMU_CA_WAKE 5
 287 #define IRQ_PRCMU_USB 6
 288 #define IRQ_PRCMU_ABB 7
 289 #define IRQ_PRCMU_ABB_FIFO 8
 290 #define IRQ_PRCMU_ARM 9
 291 #define IRQ_PRCMU_MODEM_SW_RESET_REQ 10
 292 #define IRQ_PRCMU_GPIO0 11
 293 #define IRQ_PRCMU_GPIO1 12
 294 #define IRQ_PRCMU_GPIO2 13
 295 #define IRQ_PRCMU_GPIO3 14
 296 #define IRQ_PRCMU_GPIO4 15
 297 #define IRQ_PRCMU_GPIO5 16
 298 #define IRQ_PRCMU_GPIO6 17
 299 #define IRQ_PRCMU_GPIO7 18
 300 #define IRQ_PRCMU_GPIO8 19
 301 #define IRQ_PRCMU_CA_SLEEP 20
 302 #define IRQ_PRCMU_HOTMON_LOW 21
 303 #define IRQ_PRCMU_HOTMON_HIGH 22
 304 #define NUM_PRCMU_WAKEUPS 23
 305 
 306 static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = {
 307         IRQ_ENTRY(RTC),
 308         IRQ_ENTRY(RTT0),
 309         IRQ_ENTRY(RTT1),
 310         IRQ_ENTRY(HSI0),
 311         IRQ_ENTRY(HSI1),
 312         IRQ_ENTRY(CA_WAKE),
 313         IRQ_ENTRY(USB),
 314         IRQ_ENTRY(ABB),
 315         IRQ_ENTRY(ABB_FIFO),
 316         IRQ_ENTRY(CA_SLEEP),
 317         IRQ_ENTRY(ARM),
 318         IRQ_ENTRY(HOTMON_LOW),
 319         IRQ_ENTRY(HOTMON_HIGH),
 320         IRQ_ENTRY(MODEM_SW_RESET_REQ),
 321         IRQ_ENTRY(GPIO0),
 322         IRQ_ENTRY(GPIO1),
 323         IRQ_ENTRY(GPIO2),
 324         IRQ_ENTRY(GPIO3),
 325         IRQ_ENTRY(GPIO4),
 326         IRQ_ENTRY(GPIO5),
 327         IRQ_ENTRY(GPIO6),
 328         IRQ_ENTRY(GPIO7),
 329         IRQ_ENTRY(GPIO8)
 330 };
 331 
 332 #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1)
 333 #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name)
 334 static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = {
 335         WAKEUP_ENTRY(RTC),
 336         WAKEUP_ENTRY(RTT0),
 337         WAKEUP_ENTRY(RTT1),
 338         WAKEUP_ENTRY(HSI0),
 339         WAKEUP_ENTRY(HSI1),
 340         WAKEUP_ENTRY(USB),
 341         WAKEUP_ENTRY(ABB),
 342         WAKEUP_ENTRY(ABB_FIFO),
 343         WAKEUP_ENTRY(ARM)
 344 };
 345 
 346 /*
 347  * mb0_transfer - state needed for mailbox 0 communication.
 348  * @lock:               The transaction lock.
 349  * @dbb_events_lock:    A lock used to handle concurrent access to (parts of)
 350  *                      the request data.
 351  * @mask_work:          Work structure used for (un)masking wakeup interrupts.
 352  * @req:                Request data that need to persist between requests.
 353  */
 354 static struct {
 355         spinlock_t lock;
 356         spinlock_t dbb_irqs_lock;
 357         struct work_struct mask_work;
 358         struct mutex ac_wake_lock;
 359         struct completion ac_wake_work;
 360         struct {
 361                 u32 dbb_irqs;
 362                 u32 dbb_wakeups;
 363                 u32 abb_events;
 364         } req;
 365 } mb0_transfer;
 366 
 367 /*
 368  * mb1_transfer - state needed for mailbox 1 communication.
 369  * @lock:       The transaction lock.
 370  * @work:       The transaction completion structure.
 371  * @ape_opp:    The current APE OPP.
 372  * @ack:        Reply ("acknowledge") data.
 373  */
 374 static struct {
 375         struct mutex lock;
 376         struct completion work;
 377         u8 ape_opp;
 378         struct {
 379                 u8 header;
 380                 u8 arm_opp;
 381                 u8 ape_opp;
 382                 u8 ape_voltage_status;
 383         } ack;
 384 } mb1_transfer;
 385 
 386 /*
 387  * mb2_transfer - state needed for mailbox 2 communication.
 388  * @lock:            The transaction lock.
 389  * @work:            The transaction completion structure.
 390  * @auto_pm_lock:    The autonomous power management configuration lock.
 391  * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled.
 392  * @req:             Request data that need to persist between requests.
 393  * @ack:             Reply ("acknowledge") data.
 394  */
 395 static struct {
 396         struct mutex lock;
 397         struct completion work;
 398         spinlock_t auto_pm_lock;
 399         bool auto_pm_enabled;
 400         struct {
 401                 u8 status;
 402         } ack;
 403 } mb2_transfer;
 404 
 405 /*
 406  * mb3_transfer - state needed for mailbox 3 communication.
 407  * @lock:               The request lock.
 408  * @sysclk_lock:        A lock used to handle concurrent sysclk requests.
 409  * @sysclk_work:        Work structure used for sysclk requests.
 410  */
 411 static struct {
 412         spinlock_t lock;
 413         struct mutex sysclk_lock;
 414         struct completion sysclk_work;
 415 } mb3_transfer;
 416 
 417 /*
 418  * mb4_transfer - state needed for mailbox 4 communication.
 419  * @lock:       The transaction lock.
 420  * @work:       The transaction completion structure.
 421  */
 422 static struct {
 423         struct mutex lock;
 424         struct completion work;
 425 } mb4_transfer;
 426 
 427 /*
 428  * mb5_transfer - state needed for mailbox 5 communication.
 429  * @lock:       The transaction lock.
 430  * @work:       The transaction completion structure.
 431  * @ack:        Reply ("acknowledge") data.
 432  */
 433 static struct {
 434         struct mutex lock;
 435         struct completion work;
 436         struct {
 437                 u8 status;
 438                 u8 value;
 439         } ack;
 440 } mb5_transfer;
 441 
 442 static atomic_t ac_wake_req_state = ATOMIC_INIT(0);
 443 
 444 /* Spinlocks */
 445 static DEFINE_SPINLOCK(prcmu_lock);
 446 static DEFINE_SPINLOCK(clkout_lock);
 447 
 448 /* Global var to runtime determine TCDM base for v2 or v1 */
 449 static __iomem void *tcdm_base;
 450 static __iomem void *prcmu_base;
 451 
 452 struct clk_mgt {
 453         u32 offset;
 454         u32 pllsw;
 455         int branch;
 456         bool clk38div;
 457 };
 458 
 459 enum {
 460         PLL_RAW,
 461         PLL_FIX,
 462         PLL_DIV
 463 };
 464 
 465 static DEFINE_SPINLOCK(clk_mgt_lock);
 466 
 467 #define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \
 468         { (PRCM_##_name##_MGT), 0 , _branch, _clk38div}
 469 static struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
 470         CLK_MGT_ENTRY(SGACLK, PLL_DIV, false),
 471         CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true),
 472         CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true),
 473         CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true),
 474         CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true),
 475         CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true),
 476         CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true),
 477         CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true),
 478         CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true),
 479         CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true),
 480         CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true),
 481         CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
 482         CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
 483         CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true),
 484         CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
 485         CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true),
 486         CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true),
 487         CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false),
 488         CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true),
 489         CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true),
 490         CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true),
 491         CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true),
 492         CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false),
 493         CLK_MGT_ENTRY(DMACLK, PLL_DIV, true),
 494         CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true),
 495         CLK_MGT_ENTRY(TVCLK, PLL_FIX, true),
 496         CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true),
 497         CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true),
 498         CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false),
 499 };
 500 
 501 struct dsiclk {
 502         u32 divsel_mask;
 503         u32 divsel_shift;
 504         u32 divsel;
 505 };
 506 
 507 static struct dsiclk dsiclk[2] = {
 508         {
 509                 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK,
 510                 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT,
 511                 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
 512         },
 513         {
 514                 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK,
 515                 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT,
 516                 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
 517         }
 518 };
 519 
 520 struct dsiescclk {
 521         u32 en;
 522         u32 div_mask;
 523         u32 div_shift;
 524 };
 525 
 526 static struct dsiescclk dsiescclk[3] = {
 527         {
 528                 .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN,
 529                 .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK,
 530                 .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT,
 531         },
 532         {
 533                 .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN,
 534                 .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK,
 535                 .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT,
 536         },
 537         {
 538                 .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN,
 539                 .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK,
 540                 .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT,
 541         }
 542 };
 543 
 544 
 545 /*
 546 * Used by MCDE to setup all necessary PRCMU registers
 547 */
 548 #define PRCMU_RESET_DSIPLL              0x00004000
 549 #define PRCMU_UNCLAMP_DSIPLL            0x00400800
 550 
 551 #define PRCMU_CLK_PLL_DIV_SHIFT         0
 552 #define PRCMU_CLK_PLL_SW_SHIFT          5
 553 #define PRCMU_CLK_38                    (1 << 9)
 554 #define PRCMU_CLK_38_SRC                (1 << 10)
 555 #define PRCMU_CLK_38_DIV                (1 << 11)
 556 
 557 /* PLLDIV=12, PLLSW=4 (PLLDDR) */
 558 #define PRCMU_DSI_CLOCK_SETTING         0x0000008C
 559 
 560 /* DPI 50000000 Hz */
 561 #define PRCMU_DPI_CLOCK_SETTING         ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \
 562                                           (16 << PRCMU_CLK_PLL_DIV_SHIFT))
 563 #define PRCMU_DSI_LP_CLOCK_SETTING      0x00000E00
 564 
 565 /* D=101, N=1, R=4, SELDIV2=0 */
 566 #define PRCMU_PLLDSI_FREQ_SETTING       0x00040165
 567 
 568 #define PRCMU_ENABLE_PLLDSI             0x00000001
 569 #define PRCMU_DISABLE_PLLDSI            0x00000000
 570 #define PRCMU_RELEASE_RESET_DSS         0x0000400C
 571 #define PRCMU_DSI_PLLOUT_SEL_SETTING    0x00000202
 572 /* ESC clk, div0=1, div1=1, div2=3 */
 573 #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV   0x07030101
 574 #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV  0x00030101
 575 #define PRCMU_DSI_RESET_SW              0x00000007
 576 
 577 #define PRCMU_PLLDSI_LOCKP_LOCKED       0x3
 578 
 579 int db8500_prcmu_enable_dsipll(void)
 580 {
 581         int i;
 582 
 583         /* Clear DSIPLL_RESETN */
 584         writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR);
 585         /* Unclamp DSIPLL in/out */
 586         writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR);
 587 
 588         /* Set DSI PLL FREQ */
 589         writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ);
 590         writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL);
 591         /* Enable Escape clocks */
 592         writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
 593 
 594         /* Start DSI PLL */
 595         writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
 596         /* Reset DSI PLL */
 597         writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET);
 598         for (i = 0; i < 10; i++) {
 599                 if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED)
 600                                         == PRCMU_PLLDSI_LOCKP_LOCKED)
 601                         break;
 602                 udelay(100);
 603         }
 604         /* Set DSIPLL_RESETN */
 605         writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET);
 606         return 0;
 607 }
 608 
 609 int db8500_prcmu_disable_dsipll(void)
 610 {
 611         /* Disable dsi pll */
 612         writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
 613         /* Disable  escapeclock */
 614         writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
 615         return 0;
 616 }
 617 
 618 int db8500_prcmu_set_display_clocks(void)
 619 {
 620         unsigned long flags;
 621 
 622         spin_lock_irqsave(&clk_mgt_lock, flags);
 623 
 624         /* Grab the HW semaphore. */
 625         while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
 626                 cpu_relax();
 627 
 628         writel(PRCMU_DSI_CLOCK_SETTING, prcmu_base + PRCM_HDMICLK_MGT);
 629         writel(PRCMU_DSI_LP_CLOCK_SETTING, prcmu_base + PRCM_TVCLK_MGT);
 630         writel(PRCMU_DPI_CLOCK_SETTING, prcmu_base + PRCM_LCDCLK_MGT);
 631 
 632         /* Release the HW semaphore. */
 633         writel(0, PRCM_SEM);
 634 
 635         spin_unlock_irqrestore(&clk_mgt_lock, flags);
 636 
 637         return 0;
 638 }
 639 
 640 u32 db8500_prcmu_read(unsigned int reg)
 641 {
 642         return readl(prcmu_base + reg);
 643 }
 644 
 645 void db8500_prcmu_write(unsigned int reg, u32 value)
 646 {
 647         unsigned long flags;
 648 
 649         spin_lock_irqsave(&prcmu_lock, flags);
 650         writel(value, (prcmu_base + reg));
 651         spin_unlock_irqrestore(&prcmu_lock, flags);
 652 }
 653 
 654 void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
 655 {
 656         u32 val;
 657         unsigned long flags;
 658 
 659         spin_lock_irqsave(&prcmu_lock, flags);
 660         val = readl(prcmu_base + reg);
 661         val = ((val & ~mask) | (value & mask));
 662         writel(val, (prcmu_base + reg));
 663         spin_unlock_irqrestore(&prcmu_lock, flags);
 664 }
 665 
 666 struct prcmu_fw_version *prcmu_get_fw_version(void)
 667 {
 668         return fw_info.valid ? &fw_info.version : NULL;
 669 }
 670 
 671 bool prcmu_has_arm_maxopp(void)
 672 {
 673         return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) &
 674                 PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK;
 675 }
 676 
 677 /**
 678  * prcmu_set_rc_a2p - This function is used to run few power state sequences
 679  * @val: Value to be set, i.e. transition requested
 680  * Returns: 0 on success, -EINVAL on invalid argument
 681  *
 682  * This function is used to run the following power state sequences -
 683  * any state to ApReset,  ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
 684  */
 685 int prcmu_set_rc_a2p(enum romcode_write val)
 686 {
 687         if (val < RDY_2_DS || val > RDY_2_XP70_RST)
 688                 return -EINVAL;
 689         writeb(val, (tcdm_base + PRCM_ROMCODE_A2P));
 690         return 0;
 691 }
 692 
 693 /**
 694  * prcmu_get_rc_p2a - This function is used to get power state sequences
 695  * Returns: the power transition that has last happened
 696  *
 697  * This function can return the following transitions-
 698  * any state to ApReset,  ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
 699  */
 700 enum romcode_read prcmu_get_rc_p2a(void)
 701 {
 702         return readb(tcdm_base + PRCM_ROMCODE_P2A);
 703 }
 704 
 705 /**
 706  * prcmu_get_current_mode - Return the current XP70 power mode
 707  * Returns: Returns the current AP(ARM) power mode: init,
 708  * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset
 709  */
 710 enum ap_pwrst prcmu_get_xp70_current_state(void)
 711 {
 712         return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE);
 713 }
 714 
 715 /**
 716  * prcmu_config_clkout - Configure one of the programmable clock outputs.
 717  * @clkout:     The CLKOUT number (0 or 1).
 718  * @source:     The clock to be used (one of the PRCMU_CLKSRC_*).
 719  * @div:        The divider to be applied.
 720  *
 721  * Configures one of the programmable clock outputs (CLKOUTs).
 722  * @div should be in the range [1,63] to request a configuration, or 0 to
 723  * inform that the configuration is no longer requested.
 724  */
 725 int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
 726 {
 727         static int requests[2];
 728         int r = 0;
 729         unsigned long flags;
 730         u32 val;
 731         u32 bits;
 732         u32 mask;
 733         u32 div_mask;
 734 
 735         BUG_ON(clkout > 1);
 736         BUG_ON(div > 63);
 737         BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009));
 738 
 739         if (!div && !requests[clkout])
 740                 return -EINVAL;
 741 
 742         if (clkout == 0) {
 743                 div_mask = PRCM_CLKOCR_CLKODIV0_MASK;
 744                 mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK);
 745                 bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) |
 746                         (div << PRCM_CLKOCR_CLKODIV0_SHIFT));
 747         } else {
 748                 div_mask = PRCM_CLKOCR_CLKODIV1_MASK;
 749                 mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK |
 750                         PRCM_CLKOCR_CLK1TYPE);
 751                 bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) |
 752                         (div << PRCM_CLKOCR_CLKODIV1_SHIFT));
 753         }
 754         bits &= mask;
 755 
 756         spin_lock_irqsave(&clkout_lock, flags);
 757 
 758         val = readl(PRCM_CLKOCR);
 759         if (val & div_mask) {
 760                 if (div) {
 761                         if ((val & mask) != bits) {
 762                                 r = -EBUSY;
 763                                 goto unlock_and_return;
 764                         }
 765                 } else {
 766                         if ((val & mask & ~div_mask) != bits) {
 767                                 r = -EINVAL;
 768                                 goto unlock_and_return;
 769                         }
 770                 }
 771         }
 772         writel((bits | (val & ~mask)), PRCM_CLKOCR);
 773         requests[clkout] += (div ? 1 : -1);
 774 
 775 unlock_and_return:
 776         spin_unlock_irqrestore(&clkout_lock, flags);
 777 
 778         return r;
 779 }
 780 
 781 int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll)
 782 {
 783         unsigned long flags;
 784 
 785         BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state));
 786 
 787         spin_lock_irqsave(&mb0_transfer.lock, flags);
 788 
 789         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
 790                 cpu_relax();
 791 
 792         writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
 793         writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE));
 794         writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE));
 795         writeb((keep_ulp_clk ? 1 : 0),
 796                 (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE));
 797         writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI));
 798         writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
 799 
 800         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
 801 
 802         return 0;
 803 }
 804 
 805 u8 db8500_prcmu_get_power_state_result(void)
 806 {
 807         return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS);
 808 }
 809 
 810 /* This function should only be called while mb0_transfer.lock is held. */
 811 static void config_wakeups(void)
 812 {
 813         const u8 header[2] = {
 814                 MB0H_CONFIG_WAKEUPS_EXE,
 815                 MB0H_CONFIG_WAKEUPS_SLEEP
 816         };
 817         static u32 last_dbb_events;
 818         static u32 last_abb_events;
 819         u32 dbb_events;
 820         u32 abb_events;
 821         unsigned int i;
 822 
 823         dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups;
 824         dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK);
 825 
 826         abb_events = mb0_transfer.req.abb_events;
 827 
 828         if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events))
 829                 return;
 830 
 831         for (i = 0; i < 2; i++) {
 832                 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
 833                         cpu_relax();
 834                 writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500));
 835                 writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500));
 836                 writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
 837                 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
 838         }
 839         last_dbb_events = dbb_events;
 840         last_abb_events = abb_events;
 841 }
 842 
 843 void db8500_prcmu_enable_wakeups(u32 wakeups)
 844 {
 845         unsigned long flags;
 846         u32 bits;
 847         int i;
 848 
 849         BUG_ON(wakeups != (wakeups & VALID_WAKEUPS));
 850 
 851         for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) {
 852                 if (wakeups & BIT(i))
 853                         bits |= prcmu_wakeup_bit[i];
 854         }
 855 
 856         spin_lock_irqsave(&mb0_transfer.lock, flags);
 857 
 858         mb0_transfer.req.dbb_wakeups = bits;
 859         config_wakeups();
 860 
 861         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
 862 }
 863 
 864 void db8500_prcmu_config_abb_event_readout(u32 abb_events)
 865 {
 866         unsigned long flags;
 867 
 868         spin_lock_irqsave(&mb0_transfer.lock, flags);
 869 
 870         mb0_transfer.req.abb_events = abb_events;
 871         config_wakeups();
 872 
 873         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
 874 }
 875 
 876 void db8500_prcmu_get_abb_event_buffer(void __iomem **buf)
 877 {
 878         if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
 879                 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500);
 880         else
 881                 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500);
 882 }
 883 
 884 /**
 885  * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP
 886  * @opp: The new ARM operating point to which transition is to be made
 887  * Returns: 0 on success, non-zero on failure
 888  *
 889  * This function sets the the operating point of the ARM.
 890  */
 891 int db8500_prcmu_set_arm_opp(u8 opp)
 892 {
 893         int r;
 894 
 895         if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK)
 896                 return -EINVAL;
 897 
 898         r = 0;
 899 
 900         mutex_lock(&mb1_transfer.lock);
 901 
 902         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
 903                 cpu_relax();
 904 
 905         writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
 906         writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
 907         writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP));
 908 
 909         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
 910         wait_for_completion(&mb1_transfer.work);
 911 
 912         if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
 913                 (mb1_transfer.ack.arm_opp != opp))
 914                 r = -EIO;
 915 
 916         mutex_unlock(&mb1_transfer.lock);
 917 
 918         return r;
 919 }
 920 
 921 /**
 922  * db8500_prcmu_get_arm_opp - get the current ARM OPP
 923  *
 924  * Returns: the current ARM OPP
 925  */
 926 int db8500_prcmu_get_arm_opp(void)
 927 {
 928         return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP);
 929 }
 930 
 931 /**
 932  * db8500_prcmu_get_ddr_opp - get the current DDR OPP
 933  *
 934  * Returns: the current DDR OPP
 935  */
 936 int db8500_prcmu_get_ddr_opp(void)
 937 {
 938         return readb(PRCM_DDR_SUBSYS_APE_MINBW);
 939 }
 940 
 941 /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */
 942 static void request_even_slower_clocks(bool enable)
 943 {
 944         u32 clock_reg[] = {
 945                 PRCM_ACLK_MGT,
 946                 PRCM_DMACLK_MGT
 947         };
 948         unsigned long flags;
 949         unsigned int i;
 950 
 951         spin_lock_irqsave(&clk_mgt_lock, flags);
 952 
 953         /* Grab the HW semaphore. */
 954         while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
 955                 cpu_relax();
 956 
 957         for (i = 0; i < ARRAY_SIZE(clock_reg); i++) {
 958                 u32 val;
 959                 u32 div;
 960 
 961                 val = readl(prcmu_base + clock_reg[i]);
 962                 div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK);
 963                 if (enable) {
 964                         if ((div <= 1) || (div > 15)) {
 965                                 pr_err("prcmu: Bad clock divider %d in %s\n",
 966                                         div, __func__);
 967                                 goto unlock_and_return;
 968                         }
 969                         div <<= 1;
 970                 } else {
 971                         if (div <= 2)
 972                                 goto unlock_and_return;
 973                         div >>= 1;
 974                 }
 975                 val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) |
 976                         (div & PRCM_CLK_MGT_CLKPLLDIV_MASK));
 977                 writel(val, prcmu_base + clock_reg[i]);
 978         }
 979 
 980 unlock_and_return:
 981         /* Release the HW semaphore. */
 982         writel(0, PRCM_SEM);
 983 
 984         spin_unlock_irqrestore(&clk_mgt_lock, flags);
 985 }
 986 
 987 /**
 988  * db8500_set_ape_opp - set the appropriate APE OPP
 989  * @opp: The new APE operating point to which transition is to be made
 990  * Returns: 0 on success, non-zero on failure
 991  *
 992  * This function sets the operating point of the APE.
 993  */
 994 int db8500_prcmu_set_ape_opp(u8 opp)
 995 {
 996         int r = 0;
 997 
 998         if (opp == mb1_transfer.ape_opp)
 999                 return 0;
1000 
1001         mutex_lock(&mb1_transfer.lock);
1002 
1003         if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)
1004                 request_even_slower_clocks(false);
1005 
1006         if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP))
1007                 goto skip_message;
1008 
1009         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1010                 cpu_relax();
1011 
1012         writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1013         writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
1014         writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp),
1015                 (tcdm_base + PRCM_REQ_MB1_APE_OPP));
1016 
1017         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1018         wait_for_completion(&mb1_transfer.work);
1019 
1020         if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
1021                 (mb1_transfer.ack.ape_opp != opp))
1022                 r = -EIO;
1023 
1024 skip_message:
1025         if ((!r && (opp == APE_50_PARTLY_25_OPP)) ||
1026                 (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)))
1027                 request_even_slower_clocks(true);
1028         if (!r)
1029                 mb1_transfer.ape_opp = opp;
1030 
1031         mutex_unlock(&mb1_transfer.lock);
1032 
1033         return r;
1034 }
1035 
1036 /**
1037  * db8500_prcmu_get_ape_opp - get the current APE OPP
1038  *
1039  * Returns: the current APE OPP
1040  */
1041 int db8500_prcmu_get_ape_opp(void)
1042 {
1043         return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP);
1044 }
1045 
1046 /**
1047  * db8500_prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage
1048  * @enable: true to request the higher voltage, false to drop a request.
1049  *
1050  * Calls to this function to enable and disable requests must be balanced.
1051  */
1052 int db8500_prcmu_request_ape_opp_100_voltage(bool enable)
1053 {
1054         int r = 0;
1055         u8 header;
1056         static unsigned int requests;
1057 
1058         mutex_lock(&mb1_transfer.lock);
1059 
1060         if (enable) {
1061                 if (0 != requests++)
1062                         goto unlock_and_return;
1063                 header = MB1H_REQUEST_APE_OPP_100_VOLT;
1064         } else {
1065                 if (requests == 0) {
1066                         r = -EIO;
1067                         goto unlock_and_return;
1068                 } else if (1 != requests--) {
1069                         goto unlock_and_return;
1070                 }
1071                 header = MB1H_RELEASE_APE_OPP_100_VOLT;
1072         }
1073 
1074         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1075                 cpu_relax();
1076 
1077         writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1078 
1079         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1080         wait_for_completion(&mb1_transfer.work);
1081 
1082         if ((mb1_transfer.ack.header != header) ||
1083                 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1084                 r = -EIO;
1085 
1086 unlock_and_return:
1087         mutex_unlock(&mb1_transfer.lock);
1088 
1089         return r;
1090 }
1091 
1092 /**
1093  * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup
1094  *
1095  * This function releases the power state requirements of a USB wakeup.
1096  */
1097 int prcmu_release_usb_wakeup_state(void)
1098 {
1099         int r = 0;
1100 
1101         mutex_lock(&mb1_transfer.lock);
1102 
1103         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1104                 cpu_relax();
1105 
1106         writeb(MB1H_RELEASE_USB_WAKEUP,
1107                 (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1108 
1109         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1110         wait_for_completion(&mb1_transfer.work);
1111 
1112         if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) ||
1113                 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1114                 r = -EIO;
1115 
1116         mutex_unlock(&mb1_transfer.lock);
1117 
1118         return r;
1119 }
1120 
1121 static int request_pll(u8 clock, bool enable)
1122 {
1123         int r = 0;
1124 
1125         if (clock == PRCMU_PLLSOC0)
1126                 clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF);
1127         else if (clock == PRCMU_PLLSOC1)
1128                 clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF);
1129         else
1130                 return -EINVAL;
1131 
1132         mutex_lock(&mb1_transfer.lock);
1133 
1134         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1135                 cpu_relax();
1136 
1137         writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1138         writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF));
1139 
1140         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1141         wait_for_completion(&mb1_transfer.work);
1142 
1143         if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF)
1144                 r = -EIO;
1145 
1146         mutex_unlock(&mb1_transfer.lock);
1147 
1148         return r;
1149 }
1150 
1151 /**
1152  * db8500_prcmu_set_epod - set the state of a EPOD (power domain)
1153  * @epod_id: The EPOD to set
1154  * @epod_state: The new EPOD state
1155  *
1156  * This function sets the state of a EPOD (power domain). It may not be called
1157  * from interrupt context.
1158  */
1159 int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
1160 {
1161         int r = 0;
1162         bool ram_retention = false;
1163         int i;
1164 
1165         /* check argument */
1166         BUG_ON(epod_id >= NUM_EPOD_ID);
1167 
1168         /* set flag if retention is possible */
1169         switch (epod_id) {
1170         case EPOD_ID_SVAMMDSP:
1171         case EPOD_ID_SIAMMDSP:
1172         case EPOD_ID_ESRAM12:
1173         case EPOD_ID_ESRAM34:
1174                 ram_retention = true;
1175                 break;
1176         }
1177 
1178         /* check argument */
1179         BUG_ON(epod_state > EPOD_STATE_ON);
1180         BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention);
1181 
1182         /* get lock */
1183         mutex_lock(&mb2_transfer.lock);
1184 
1185         /* wait for mailbox */
1186         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2))
1187                 cpu_relax();
1188 
1189         /* fill in mailbox */
1190         for (i = 0; i < NUM_EPOD_ID; i++)
1191                 writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i));
1192         writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id));
1193 
1194         writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2));
1195 
1196         writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET);
1197 
1198         /*
1199          * The current firmware version does not handle errors correctly,
1200          * and we cannot recover if there is an error.
1201          * This is expected to change when the firmware is updated.
1202          */
1203         if (!wait_for_completion_timeout(&mb2_transfer.work,
1204                         msecs_to_jiffies(20000))) {
1205                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1206                         __func__);
1207                 r = -EIO;
1208                 goto unlock_and_return;
1209         }
1210 
1211         if (mb2_transfer.ack.status != HWACC_PWR_ST_OK)
1212                 r = -EIO;
1213 
1214 unlock_and_return:
1215         mutex_unlock(&mb2_transfer.lock);
1216         return r;
1217 }
1218 
1219 /**
1220  * prcmu_configure_auto_pm - Configure autonomous power management.
1221  * @sleep: Configuration for ApSleep.
1222  * @idle:  Configuration for ApIdle.
1223  */
1224 void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
1225         struct prcmu_auto_pm_config *idle)
1226 {
1227         u32 sleep_cfg;
1228         u32 idle_cfg;
1229         unsigned long flags;
1230 
1231         BUG_ON((sleep == NULL) || (idle == NULL));
1232 
1233         sleep_cfg = (sleep->sva_auto_pm_enable & 0xF);
1234         sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF));
1235         sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF));
1236         sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF));
1237         sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF));
1238         sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF));
1239 
1240         idle_cfg = (idle->sva_auto_pm_enable & 0xF);
1241         idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF));
1242         idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF));
1243         idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF));
1244         idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF));
1245         idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF));
1246 
1247         spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags);
1248 
1249         /*
1250          * The autonomous power management configuration is done through
1251          * fields in mailbox 2, but these fields are only used as shared
1252          * variables - i.e. there is no need to send a message.
1253          */
1254         writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP));
1255         writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE));
1256 
1257         mb2_transfer.auto_pm_enabled =
1258                 ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1259                  (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1260                  (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1261                  (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON));
1262 
1263         spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags);
1264 }
1265 EXPORT_SYMBOL(prcmu_configure_auto_pm);
1266 
1267 bool prcmu_is_auto_pm_enabled(void)
1268 {
1269         return mb2_transfer.auto_pm_enabled;
1270 }
1271 
1272 static int request_sysclk(bool enable)
1273 {
1274         int r;
1275         unsigned long flags;
1276 
1277         r = 0;
1278 
1279         mutex_lock(&mb3_transfer.sysclk_lock);
1280 
1281         spin_lock_irqsave(&mb3_transfer.lock, flags);
1282 
1283         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3))
1284                 cpu_relax();
1285 
1286         writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT));
1287 
1288         writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3));
1289         writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET);
1290 
1291         spin_unlock_irqrestore(&mb3_transfer.lock, flags);
1292 
1293         /*
1294          * The firmware only sends an ACK if we want to enable the
1295          * SysClk, and it succeeds.
1296          */
1297         if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work,
1298                         msecs_to_jiffies(20000))) {
1299                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1300                         __func__);
1301                 r = -EIO;
1302         }
1303 
1304         mutex_unlock(&mb3_transfer.sysclk_lock);
1305 
1306         return r;
1307 }
1308 
1309 static int request_timclk(bool enable)
1310 {
1311         u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK);
1312 
1313         if (!enable)
1314                 val |= PRCM_TCR_STOP_TIMERS;
1315         writel(val, PRCM_TCR);
1316 
1317         return 0;
1318 }
1319 
1320 static int request_clock(u8 clock, bool enable)
1321 {
1322         u32 val;
1323         unsigned long flags;
1324 
1325         spin_lock_irqsave(&clk_mgt_lock, flags);
1326 
1327         /* Grab the HW semaphore. */
1328         while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1329                 cpu_relax();
1330 
1331         val = readl(prcmu_base + clk_mgt[clock].offset);
1332         if (enable) {
1333                 val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
1334         } else {
1335                 clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1336                 val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK);
1337         }
1338         writel(val, prcmu_base + clk_mgt[clock].offset);
1339 
1340         /* Release the HW semaphore. */
1341         writel(0, PRCM_SEM);
1342 
1343         spin_unlock_irqrestore(&clk_mgt_lock, flags);
1344 
1345         return 0;
1346 }
1347 
1348 static int request_sga_clock(u8 clock, bool enable)
1349 {
1350         u32 val;
1351         int ret;
1352 
1353         if (enable) {
1354                 val = readl(PRCM_CGATING_BYPASS);
1355                 writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1356         }
1357 
1358         ret = request_clock(clock, enable);
1359 
1360         if (!ret && !enable) {
1361                 val = readl(PRCM_CGATING_BYPASS);
1362                 writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1363         }
1364 
1365         return ret;
1366 }
1367 
1368 static inline bool plldsi_locked(void)
1369 {
1370         return (readl(PRCM_PLLDSI_LOCKP) &
1371                 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1372                  PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) ==
1373                 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1374                  PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3);
1375 }
1376 
1377 static int request_plldsi(bool enable)
1378 {
1379         int r = 0;
1380         u32 val;
1381 
1382         writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1383                 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ?
1384                 PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET));
1385 
1386         val = readl(PRCM_PLLDSI_ENABLE);
1387         if (enable)
1388                 val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1389         else
1390                 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1391         writel(val, PRCM_PLLDSI_ENABLE);
1392 
1393         if (enable) {
1394                 unsigned int i;
1395                 bool locked = plldsi_locked();
1396 
1397                 for (i = 10; !locked && (i > 0); --i) {
1398                         udelay(100);
1399                         locked = plldsi_locked();
1400                 }
1401                 if (locked) {
1402                         writel(PRCM_APE_RESETN_DSIPLL_RESETN,
1403                                 PRCM_APE_RESETN_SET);
1404                 } else {
1405                         writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1406                                 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI),
1407                                 PRCM_MMIP_LS_CLAMP_SET);
1408                         val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1409                         writel(val, PRCM_PLLDSI_ENABLE);
1410                         r = -EAGAIN;
1411                 }
1412         } else {
1413                 writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR);
1414         }
1415         return r;
1416 }
1417 
1418 static int request_dsiclk(u8 n, bool enable)
1419 {
1420         u32 val;
1421 
1422         val = readl(PRCM_DSI_PLLOUT_SEL);
1423         val &= ~dsiclk[n].divsel_mask;
1424         val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) <<
1425                 dsiclk[n].divsel_shift);
1426         writel(val, PRCM_DSI_PLLOUT_SEL);
1427         return 0;
1428 }
1429 
1430 static int request_dsiescclk(u8 n, bool enable)
1431 {
1432         u32 val;
1433 
1434         val = readl(PRCM_DSITVCLK_DIV);
1435         enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en);
1436         writel(val, PRCM_DSITVCLK_DIV);
1437         return 0;
1438 }
1439 
1440 /**
1441  * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled.
1442  * @clock:      The clock for which the request is made.
1443  * @enable:     Whether the clock should be enabled (true) or disabled (false).
1444  *
1445  * This function should only be used by the clock implementation.
1446  * Do not use it from any other place!
1447  */
1448 int db8500_prcmu_request_clock(u8 clock, bool enable)
1449 {
1450         if (clock == PRCMU_SGACLK)
1451                 return request_sga_clock(clock, enable);
1452         else if (clock < PRCMU_NUM_REG_CLOCKS)
1453                 return request_clock(clock, enable);
1454         else if (clock == PRCMU_TIMCLK)
1455                 return request_timclk(enable);
1456         else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1457                 return request_dsiclk((clock - PRCMU_DSI0CLK), enable);
1458         else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1459                 return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable);
1460         else if (clock == PRCMU_PLLDSI)
1461                 return request_plldsi(enable);
1462         else if (clock == PRCMU_SYSCLK)
1463                 return request_sysclk(enable);
1464         else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1))
1465                 return request_pll(clock, enable);
1466         else
1467                 return -EINVAL;
1468 }
1469 
1470 static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate,
1471         int branch)
1472 {
1473         u64 rate;
1474         u32 val;
1475         u32 d;
1476         u32 div = 1;
1477 
1478         val = readl(reg);
1479 
1480         rate = src_rate;
1481         rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT);
1482 
1483         d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT);
1484         if (d > 1)
1485                 div *= d;
1486 
1487         d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT);
1488         if (d > 1)
1489                 div *= d;
1490 
1491         if (val & PRCM_PLL_FREQ_SELDIV2)
1492                 div *= 2;
1493 
1494         if ((branch == PLL_FIX) || ((branch == PLL_DIV) &&
1495                 (val & PRCM_PLL_FREQ_DIV2EN) &&
1496                 ((reg == PRCM_PLLSOC0_FREQ) ||
1497                  (reg == PRCM_PLLARM_FREQ) ||
1498                  (reg == PRCM_PLLDDR_FREQ))))
1499                 div *= 2;
1500 
1501         (void)do_div(rate, div);
1502 
1503         return (unsigned long)rate;
1504 }
1505 
1506 #define ROOT_CLOCK_RATE 38400000
1507 
1508 static unsigned long clock_rate(u8 clock)
1509 {
1510         u32 val;
1511         u32 pllsw;
1512         unsigned long rate = ROOT_CLOCK_RATE;
1513 
1514         val = readl(prcmu_base + clk_mgt[clock].offset);
1515 
1516         if (val & PRCM_CLK_MGT_CLK38) {
1517                 if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV))
1518                         rate /= 2;
1519                 return rate;
1520         }
1521 
1522         val |= clk_mgt[clock].pllsw;
1523         pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1524 
1525         if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1526                 rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch);
1527         else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1528                 rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch);
1529         else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR)
1530                 rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch);
1531         else
1532                 return 0;
1533 
1534         if ((clock == PRCMU_SGACLK) &&
1535                 (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) {
1536                 u64 r = (rate * 10);
1537 
1538                 (void)do_div(r, 25);
1539                 return (unsigned long)r;
1540         }
1541         val &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1542         if (val)
1543                 return rate / val;
1544         else
1545                 return 0;
1546 }
1547 
1548 static unsigned long armss_rate(void)
1549 {
1550         u32 r;
1551         unsigned long rate;
1552 
1553         r = readl(PRCM_ARM_CHGCLKREQ);
1554 
1555         if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) {
1556                 /* External ARMCLKFIX clock */
1557 
1558                 rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX);
1559 
1560                 /* Check PRCM_ARM_CHGCLKREQ divider */
1561                 if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL))
1562                         rate /= 2;
1563 
1564                 /* Check PRCM_ARMCLKFIX_MGT divider */
1565                 r = readl(PRCM_ARMCLKFIX_MGT);
1566                 r &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1567                 rate /= r;
1568 
1569         } else {/* ARM PLL */
1570                 rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV);
1571         }
1572 
1573         return rate;
1574 }
1575 
1576 static unsigned long dsiclk_rate(u8 n)
1577 {
1578         u32 divsel;
1579         u32 div = 1;
1580 
1581         divsel = readl(PRCM_DSI_PLLOUT_SEL);
1582         divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift);
1583 
1584         if (divsel == PRCM_DSI_PLLOUT_SEL_OFF)
1585                 divsel = dsiclk[n].divsel;
1586         else
1587                 dsiclk[n].divsel = divsel;
1588 
1589         switch (divsel) {
1590         case PRCM_DSI_PLLOUT_SEL_PHI_4:
1591                 div *= 2;
1592                 /* Fall through */
1593         case PRCM_DSI_PLLOUT_SEL_PHI_2:
1594                 div *= 2;
1595                 /* Fall through */
1596         case PRCM_DSI_PLLOUT_SEL_PHI:
1597                 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1598                         PLL_RAW) / div;
1599         default:
1600                 return 0;
1601         }
1602 }
1603 
1604 static unsigned long dsiescclk_rate(u8 n)
1605 {
1606         u32 div;
1607 
1608         div = readl(PRCM_DSITVCLK_DIV);
1609         div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift));
1610         return clock_rate(PRCMU_TVCLK) / max((u32)1, div);
1611 }
1612 
1613 unsigned long prcmu_clock_rate(u8 clock)
1614 {
1615         if (clock < PRCMU_NUM_REG_CLOCKS)
1616                 return clock_rate(clock);
1617         else if (clock == PRCMU_TIMCLK)
1618                 return ROOT_CLOCK_RATE / 16;
1619         else if (clock == PRCMU_SYSCLK)
1620                 return ROOT_CLOCK_RATE;
1621         else if (clock == PRCMU_PLLSOC0)
1622                 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1623         else if (clock == PRCMU_PLLSOC1)
1624                 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1625         else if (clock == PRCMU_ARMSS)
1626                 return armss_rate();
1627         else if (clock == PRCMU_PLLDDR)
1628                 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1629         else if (clock == PRCMU_PLLDSI)
1630                 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1631                         PLL_RAW);
1632         else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1633                 return dsiclk_rate(clock - PRCMU_DSI0CLK);
1634         else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1635                 return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK);
1636         else
1637                 return 0;
1638 }
1639 
1640 static unsigned long clock_source_rate(u32 clk_mgt_val, int branch)
1641 {
1642         if (clk_mgt_val & PRCM_CLK_MGT_CLK38)
1643                 return ROOT_CLOCK_RATE;
1644         clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK;
1645         if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1646                 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch);
1647         else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1648                 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch);
1649         else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR)
1650                 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch);
1651         else
1652                 return 0;
1653 }
1654 
1655 static u32 clock_divider(unsigned long src_rate, unsigned long rate)
1656 {
1657         u32 div;
1658 
1659         div = (src_rate / rate);
1660         if (div == 0)
1661                 return 1;
1662         if (rate < (src_rate / div))
1663                 div++;
1664         return div;
1665 }
1666 
1667 static long round_clock_rate(u8 clock, unsigned long rate)
1668 {
1669         u32 val;
1670         u32 div;
1671         unsigned long src_rate;
1672         long rounded_rate;
1673 
1674         val = readl(prcmu_base + clk_mgt[clock].offset);
1675         src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1676                 clk_mgt[clock].branch);
1677         div = clock_divider(src_rate, rate);
1678         if (val & PRCM_CLK_MGT_CLK38) {
1679                 if (clk_mgt[clock].clk38div) {
1680                         if (div > 2)
1681                                 div = 2;
1682                 } else {
1683                         div = 1;
1684                 }
1685         } else if ((clock == PRCMU_SGACLK) && (div == 3)) {
1686                 u64 r = (src_rate * 10);
1687 
1688                 (void)do_div(r, 25);
1689                 if (r <= rate)
1690                         return (unsigned long)r;
1691         }
1692         rounded_rate = (src_rate / min(div, (u32)31));
1693 
1694         return rounded_rate;
1695 }
1696 
1697 static const unsigned long db8500_armss_freqs[] = {
1698         200000000,
1699         400000000,
1700         800000000,
1701         998400000
1702 };
1703 
1704 /* The DB8520 has slightly higher ARMSS max frequency */
1705 static const unsigned long db8520_armss_freqs[] = {
1706         200000000,
1707         400000000,
1708         800000000,
1709         1152000000
1710 };
1711 
1712 
1713 
1714 static long round_armss_rate(unsigned long rate)
1715 {
1716         unsigned long freq = 0;
1717         const unsigned long *freqs;
1718         int nfreqs;
1719         int i;
1720 
1721         if (fw_info.version.project == PRCMU_FW_PROJECT_U8520) {
1722                 freqs = db8520_armss_freqs;
1723                 nfreqs = ARRAY_SIZE(db8520_armss_freqs);
1724         } else {
1725                 freqs = db8500_armss_freqs;
1726                 nfreqs = ARRAY_SIZE(db8500_armss_freqs);
1727         }
1728 
1729         /* Find the corresponding arm opp from the cpufreq table. */
1730         for (i = 0; i < nfreqs; i++) {
1731                 freq = freqs[i];
1732                 if (rate <= freq)
1733                         break;
1734         }
1735 
1736         /* Return the last valid value, even if a match was not found. */
1737         return freq;
1738 }
1739 
1740 #define MIN_PLL_VCO_RATE 600000000ULL
1741 #define MAX_PLL_VCO_RATE 1680640000ULL
1742 
1743 static long round_plldsi_rate(unsigned long rate)
1744 {
1745         long rounded_rate = 0;
1746         unsigned long src_rate;
1747         unsigned long rem;
1748         u32 r;
1749 
1750         src_rate = clock_rate(PRCMU_HDMICLK);
1751         rem = rate;
1752 
1753         for (r = 7; (rem > 0) && (r > 0); r--) {
1754                 u64 d;
1755 
1756                 d = (r * rate);
1757                 (void)do_div(d, src_rate);
1758                 if (d < 6)
1759                         d = 6;
1760                 else if (d > 255)
1761                         d = 255;
1762                 d *= src_rate;
1763                 if (((2 * d) < (r * MIN_PLL_VCO_RATE)) ||
1764                         ((r * MAX_PLL_VCO_RATE) < (2 * d)))
1765                         continue;
1766                 (void)do_div(d, r);
1767                 if (rate < d) {
1768                         if (rounded_rate == 0)
1769                                 rounded_rate = (long)d;
1770                         break;
1771                 }
1772                 if ((rate - d) < rem) {
1773                         rem = (rate - d);
1774                         rounded_rate = (long)d;
1775                 }
1776         }
1777         return rounded_rate;
1778 }
1779 
1780 static long round_dsiclk_rate(unsigned long rate)
1781 {
1782         u32 div;
1783         unsigned long src_rate;
1784         long rounded_rate;
1785 
1786         src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1787                 PLL_RAW);
1788         div = clock_divider(src_rate, rate);
1789         rounded_rate = (src_rate / ((div > 2) ? 4 : div));
1790 
1791         return rounded_rate;
1792 }
1793 
1794 static long round_dsiescclk_rate(unsigned long rate)
1795 {
1796         u32 div;
1797         unsigned long src_rate;
1798         long rounded_rate;
1799 
1800         src_rate = clock_rate(PRCMU_TVCLK);
1801         div = clock_divider(src_rate, rate);
1802         rounded_rate = (src_rate / min(div, (u32)255));
1803 
1804         return rounded_rate;
1805 }
1806 
1807 long prcmu_round_clock_rate(u8 clock, unsigned long rate)
1808 {
1809         if (clock < PRCMU_NUM_REG_CLOCKS)
1810                 return round_clock_rate(clock, rate);
1811         else if (clock == PRCMU_ARMSS)
1812                 return round_armss_rate(rate);
1813         else if (clock == PRCMU_PLLDSI)
1814                 return round_plldsi_rate(rate);
1815         else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1816                 return round_dsiclk_rate(rate);
1817         else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1818                 return round_dsiescclk_rate(rate);
1819         else
1820                 return (long)prcmu_clock_rate(clock);
1821 }
1822 
1823 static void set_clock_rate(u8 clock, unsigned long rate)
1824 {
1825         u32 val;
1826         u32 div;
1827         unsigned long src_rate;
1828         unsigned long flags;
1829 
1830         spin_lock_irqsave(&clk_mgt_lock, flags);
1831 
1832         /* Grab the HW semaphore. */
1833         while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1834                 cpu_relax();
1835 
1836         val = readl(prcmu_base + clk_mgt[clock].offset);
1837         src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1838                 clk_mgt[clock].branch);
1839         div = clock_divider(src_rate, rate);
1840         if (val & PRCM_CLK_MGT_CLK38) {
1841                 if (clk_mgt[clock].clk38div) {
1842                         if (div > 1)
1843                                 val |= PRCM_CLK_MGT_CLK38DIV;
1844                         else
1845                                 val &= ~PRCM_CLK_MGT_CLK38DIV;
1846                 }
1847         } else if (clock == PRCMU_SGACLK) {
1848                 val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK |
1849                         PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN);
1850                 if (div == 3) {
1851                         u64 r = (src_rate * 10);
1852 
1853                         (void)do_div(r, 25);
1854                         if (r <= rate) {
1855                                 val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN;
1856                                 div = 0;
1857                         }
1858                 }
1859                 val |= min(div, (u32)31);
1860         } else {
1861                 val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK;
1862                 val |= min(div, (u32)31);
1863         }
1864         writel(val, prcmu_base + clk_mgt[clock].offset);
1865 
1866         /* Release the HW semaphore. */
1867         writel(0, PRCM_SEM);
1868 
1869         spin_unlock_irqrestore(&clk_mgt_lock, flags);
1870 }
1871 
1872 static int set_armss_rate(unsigned long rate)
1873 {
1874         unsigned long freq;
1875         u8 opps[] = { ARM_EXTCLK, ARM_50_OPP, ARM_100_OPP, ARM_MAX_OPP };
1876         const unsigned long *freqs;
1877         int nfreqs;
1878         int i;
1879 
1880         if (fw_info.version.project == PRCMU_FW_PROJECT_U8520) {
1881                 freqs = db8520_armss_freqs;
1882                 nfreqs = ARRAY_SIZE(db8520_armss_freqs);
1883         } else {
1884                 freqs = db8500_armss_freqs;
1885                 nfreqs = ARRAY_SIZE(db8500_armss_freqs);
1886         }
1887 
1888         /* Find the corresponding arm opp from the cpufreq table. */
1889         for (i = 0; i < nfreqs; i++) {
1890                 freq = freqs[i];
1891                 if (rate == freq)
1892                         break;
1893         }
1894 
1895         if (rate != freq)
1896                 return -EINVAL;
1897 
1898         /* Set the new arm opp. */
1899         pr_debug("SET ARM OPP 0x%02x\n", opps[i]);
1900         return db8500_prcmu_set_arm_opp(opps[i]);
1901 }
1902 
1903 static int set_plldsi_rate(unsigned long rate)
1904 {
1905         unsigned long src_rate;
1906         unsigned long rem;
1907         u32 pll_freq = 0;
1908         u32 r;
1909 
1910         src_rate = clock_rate(PRCMU_HDMICLK);
1911         rem = rate;
1912 
1913         for (r = 7; (rem > 0) && (r > 0); r--) {
1914                 u64 d;
1915                 u64 hwrate;
1916 
1917                 d = (r * rate);
1918                 (void)do_div(d, src_rate);
1919                 if (d < 6)
1920                         d = 6;
1921                 else if (d > 255)
1922                         d = 255;
1923                 hwrate = (d * src_rate);
1924                 if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) ||
1925                         ((r * MAX_PLL_VCO_RATE) < (2 * hwrate)))
1926                         continue;
1927                 (void)do_div(hwrate, r);
1928                 if (rate < hwrate) {
1929                         if (pll_freq == 0)
1930                                 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
1931                                         (r << PRCM_PLL_FREQ_R_SHIFT));
1932                         break;
1933                 }
1934                 if ((rate - hwrate) < rem) {
1935                         rem = (rate - hwrate);
1936                         pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
1937                                 (r << PRCM_PLL_FREQ_R_SHIFT));
1938                 }
1939         }
1940         if (pll_freq == 0)
1941                 return -EINVAL;
1942 
1943         pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT);
1944         writel(pll_freq, PRCM_PLLDSI_FREQ);
1945 
1946         return 0;
1947 }
1948 
1949 static void set_dsiclk_rate(u8 n, unsigned long rate)
1950 {
1951         u32 val;
1952         u32 div;
1953 
1954         div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ,
1955                         clock_rate(PRCMU_HDMICLK), PLL_RAW), rate);
1956 
1957         dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI :
1958                            (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 :
1959                            /* else */   PRCM_DSI_PLLOUT_SEL_PHI_4;
1960 
1961         val = readl(PRCM_DSI_PLLOUT_SEL);
1962         val &= ~dsiclk[n].divsel_mask;
1963         val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift);
1964         writel(val, PRCM_DSI_PLLOUT_SEL);
1965 }
1966 
1967 static void set_dsiescclk_rate(u8 n, unsigned long rate)
1968 {
1969         u32 val;
1970         u32 div;
1971 
1972         div = clock_divider(clock_rate(PRCMU_TVCLK), rate);
1973         val = readl(PRCM_DSITVCLK_DIV);
1974         val &= ~dsiescclk[n].div_mask;
1975         val |= (min(div, (u32)255) << dsiescclk[n].div_shift);
1976         writel(val, PRCM_DSITVCLK_DIV);
1977 }
1978 
1979 int prcmu_set_clock_rate(u8 clock, unsigned long rate)
1980 {
1981         if (clock < PRCMU_NUM_REG_CLOCKS)
1982                 set_clock_rate(clock, rate);
1983         else if (clock == PRCMU_ARMSS)
1984                 return set_armss_rate(rate);
1985         else if (clock == PRCMU_PLLDSI)
1986                 return set_plldsi_rate(rate);
1987         else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1988                 set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate);
1989         else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1990                 set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate);
1991         return 0;
1992 }
1993 
1994 int db8500_prcmu_config_esram0_deep_sleep(u8 state)
1995 {
1996         if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) ||
1997             (state < ESRAM0_DEEP_SLEEP_STATE_OFF))
1998                 return -EINVAL;
1999 
2000         mutex_lock(&mb4_transfer.lock);
2001 
2002         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2003                 cpu_relax();
2004 
2005         writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2006         writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON),
2007                (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE));
2008         writeb(DDR_PWR_STATE_ON,
2009                (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE));
2010         writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST));
2011 
2012         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2013         wait_for_completion(&mb4_transfer.work);
2014 
2015         mutex_unlock(&mb4_transfer.lock);
2016 
2017         return 0;
2018 }
2019 
2020 int db8500_prcmu_config_hotdog(u8 threshold)
2021 {
2022         mutex_lock(&mb4_transfer.lock);
2023 
2024         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2025                 cpu_relax();
2026 
2027         writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD));
2028         writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2029 
2030         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2031         wait_for_completion(&mb4_transfer.work);
2032 
2033         mutex_unlock(&mb4_transfer.lock);
2034 
2035         return 0;
2036 }
2037 
2038 int db8500_prcmu_config_hotmon(u8 low, u8 high)
2039 {
2040         mutex_lock(&mb4_transfer.lock);
2041 
2042         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2043                 cpu_relax();
2044 
2045         writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW));
2046         writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH));
2047         writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH),
2048                 (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG));
2049         writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2050 
2051         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2052         wait_for_completion(&mb4_transfer.work);
2053 
2054         mutex_unlock(&mb4_transfer.lock);
2055 
2056         return 0;
2057 }
2058 EXPORT_SYMBOL_GPL(db8500_prcmu_config_hotmon);
2059 
2060 static int config_hot_period(u16 val)
2061 {
2062         mutex_lock(&mb4_transfer.lock);
2063 
2064         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2065                 cpu_relax();
2066 
2067         writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD));
2068         writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2069 
2070         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2071         wait_for_completion(&mb4_transfer.work);
2072 
2073         mutex_unlock(&mb4_transfer.lock);
2074 
2075         return 0;
2076 }
2077 
2078 int db8500_prcmu_start_temp_sense(u16 cycles32k)
2079 {
2080         if (cycles32k == 0xFFFF)
2081                 return -EINVAL;
2082 
2083         return config_hot_period(cycles32k);
2084 }
2085 EXPORT_SYMBOL_GPL(db8500_prcmu_start_temp_sense);
2086 
2087 int db8500_prcmu_stop_temp_sense(void)
2088 {
2089         return config_hot_period(0xFFFF);
2090 }
2091 EXPORT_SYMBOL_GPL(db8500_prcmu_stop_temp_sense);
2092 
2093 static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3)
2094 {
2095 
2096         mutex_lock(&mb4_transfer.lock);
2097 
2098         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2099                 cpu_relax();
2100 
2101         writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0));
2102         writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1));
2103         writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2));
2104         writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3));
2105 
2106         writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2107 
2108         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2109         wait_for_completion(&mb4_transfer.work);
2110 
2111         mutex_unlock(&mb4_transfer.lock);
2112 
2113         return 0;
2114 
2115 }
2116 
2117 int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
2118 {
2119         BUG_ON(num == 0 || num > 0xf);
2120         return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0,
2121                             sleep_auto_off ? A9WDOG_AUTO_OFF_EN :
2122                             A9WDOG_AUTO_OFF_DIS);
2123 }
2124 EXPORT_SYMBOL(db8500_prcmu_config_a9wdog);
2125 
2126 int db8500_prcmu_enable_a9wdog(u8 id)
2127 {
2128         return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0);
2129 }
2130 EXPORT_SYMBOL(db8500_prcmu_enable_a9wdog);
2131 
2132 int db8500_prcmu_disable_a9wdog(u8 id)
2133 {
2134         return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0);
2135 }
2136 EXPORT_SYMBOL(db8500_prcmu_disable_a9wdog);
2137 
2138 int db8500_prcmu_kick_a9wdog(u8 id)
2139 {
2140         return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0);
2141 }
2142 EXPORT_SYMBOL(db8500_prcmu_kick_a9wdog);
2143 
2144 /*
2145  * timeout is 28 bit, in ms.
2146  */
2147 int db8500_prcmu_load_a9wdog(u8 id, u32 timeout)
2148 {
2149         return prcmu_a9wdog(MB4H_A9WDOG_LOAD,
2150                             (id & A9WDOG_ID_MASK) |
2151                             /*
2152                              * Put the lowest 28 bits of timeout at
2153                              * offset 4. Four first bits are used for id.
2154                              */
2155                             (u8)((timeout << 4) & 0xf0),
2156                             (u8)((timeout >> 4) & 0xff),
2157                             (u8)((timeout >> 12) & 0xff),
2158                             (u8)((timeout >> 20) & 0xff));
2159 }
2160 EXPORT_SYMBOL(db8500_prcmu_load_a9wdog);
2161 
2162 /**
2163  * prcmu_abb_read() - Read register value(s) from the ABB.
2164  * @slave:      The I2C slave address.
2165  * @reg:        The (start) register address.
2166  * @value:      The read out value(s).
2167  * @size:       The number of registers to read.
2168  *
2169  * Reads register value(s) from the ABB.
2170  * @size has to be 1 for the current firmware version.
2171  */
2172 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
2173 {
2174         int r;
2175 
2176         if (size != 1)
2177                 return -EINVAL;
2178 
2179         mutex_lock(&mb5_transfer.lock);
2180 
2181         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2182                 cpu_relax();
2183 
2184         writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2185         writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2186         writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2187         writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2188         writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2189 
2190         writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2191 
2192         if (!wait_for_completion_timeout(&mb5_transfer.work,
2193                                 msecs_to_jiffies(20000))) {
2194                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2195                         __func__);
2196                 r = -EIO;
2197         } else {
2198                 r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
2199         }
2200 
2201         if (!r)
2202                 *value = mb5_transfer.ack.value;
2203 
2204         mutex_unlock(&mb5_transfer.lock);
2205 
2206         return r;
2207 }
2208 
2209 /**
2210  * prcmu_abb_write_masked() - Write masked register value(s) to the ABB.
2211  * @slave:      The I2C slave address.
2212  * @reg:        The (start) register address.
2213  * @value:      The value(s) to write.
2214  * @mask:       The mask(s) to use.
2215  * @size:       The number of registers to write.
2216  *
2217  * Writes masked register value(s) to the ABB.
2218  * For each @value, only the bits set to 1 in the corresponding @mask
2219  * will be written. The other bits are not changed.
2220  * @size has to be 1 for the current firmware version.
2221  */
2222 int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size)
2223 {
2224         int r;
2225 
2226         if (size != 1)
2227                 return -EINVAL;
2228 
2229         mutex_lock(&mb5_transfer.lock);
2230 
2231         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2232                 cpu_relax();
2233 
2234         writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2235         writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2236         writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2237         writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2238         writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2239 
2240         writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2241 
2242         if (!wait_for_completion_timeout(&mb5_transfer.work,
2243                                 msecs_to_jiffies(20000))) {
2244                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2245                         __func__);
2246                 r = -EIO;
2247         } else {
2248                 r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
2249         }
2250 
2251         mutex_unlock(&mb5_transfer.lock);
2252 
2253         return r;
2254 }
2255 
2256 /**
2257  * prcmu_abb_write() - Write register value(s) to the ABB.
2258  * @slave:      The I2C slave address.
2259  * @reg:        The (start) register address.
2260  * @value:      The value(s) to write.
2261  * @size:       The number of registers to write.
2262  *
2263  * Writes register value(s) to the ABB.
2264  * @size has to be 1 for the current firmware version.
2265  */
2266 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
2267 {
2268         u8 mask = ~0;
2269 
2270         return prcmu_abb_write_masked(slave, reg, value, &mask, size);
2271 }
2272 
2273 /**
2274  * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem
2275  */
2276 int prcmu_ac_wake_req(void)
2277 {
2278         u32 val;
2279         int ret = 0;
2280 
2281         mutex_lock(&mb0_transfer.ac_wake_lock);
2282 
2283         val = readl(PRCM_HOSTACCESS_REQ);
2284         if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)
2285                 goto unlock_and_return;
2286 
2287         atomic_set(&ac_wake_req_state, 1);
2288 
2289         /*
2290          * Force Modem Wake-up before hostaccess_req ping-pong.
2291          * It prevents Modem to enter in Sleep while acking the hostaccess
2292          * request. The 31us delay has been calculated by HWI.
2293          */
2294         val |= PRCM_HOSTACCESS_REQ_WAKE_REQ;
2295         writel(val, PRCM_HOSTACCESS_REQ);
2296 
2297         udelay(31);
2298 
2299         val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ;
2300         writel(val, PRCM_HOSTACCESS_REQ);
2301 
2302         if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2303                         msecs_to_jiffies(5000))) {
2304                 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2305                         __func__);
2306                 ret = -EFAULT;
2307         }
2308 
2309 unlock_and_return:
2310         mutex_unlock(&mb0_transfer.ac_wake_lock);
2311         return ret;
2312 }
2313 
2314 /**
2315  * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem
2316  */
2317 void prcmu_ac_sleep_req(void)
2318 {
2319         u32 val;
2320 
2321         mutex_lock(&mb0_transfer.ac_wake_lock);
2322 
2323         val = readl(PRCM_HOSTACCESS_REQ);
2324         if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ))
2325                 goto unlock_and_return;
2326 
2327         writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ),
2328                 PRCM_HOSTACCESS_REQ);
2329 
2330         if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2331                         msecs_to_jiffies(5000))) {
2332                 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2333                         __func__);
2334         }
2335 
2336         atomic_set(&ac_wake_req_state, 0);
2337 
2338 unlock_and_return:
2339         mutex_unlock(&mb0_transfer.ac_wake_lock);
2340 }
2341 
2342 bool db8500_prcmu_is_ac_wake_requested(void)
2343 {
2344         return (atomic_read(&ac_wake_req_state) != 0);
2345 }
2346 
2347 /**
2348  * db8500_prcmu_system_reset - System reset
2349  *
2350  * Saves the reset reason code and then sets the APE_SOFTRST register which
2351  * fires interrupt to fw
2352  */
2353 void db8500_prcmu_system_reset(u16 reset_code)
2354 {
2355         writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON));
2356         writel(1, PRCM_APE_SOFTRST);
2357 }
2358 
2359 /**
2360  * db8500_prcmu_get_reset_code - Retrieve SW reset reason code
2361  *
2362  * Retrieves the reset reason code stored by prcmu_system_reset() before
2363  * last restart.
2364  */
2365 u16 db8500_prcmu_get_reset_code(void)
2366 {
2367         return readw(tcdm_base + PRCM_SW_RST_REASON);
2368 }
2369 
2370 /**
2371  * db8500_prcmu_reset_modem - ask the PRCMU to reset modem
2372  */
2373 void db8500_prcmu_modem_reset(void)
2374 {
2375         mutex_lock(&mb1_transfer.lock);
2376 
2377         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
2378                 cpu_relax();
2379 
2380         writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
2381         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
2382         wait_for_completion(&mb1_transfer.work);
2383 
2384         /*
2385          * No need to check return from PRCMU as modem should go in reset state
2386          * This state is already managed by upper layer
2387          */
2388 
2389         mutex_unlock(&mb1_transfer.lock);
2390 }
2391 
2392 static void ack_dbb_wakeup(void)
2393 {
2394         unsigned long flags;
2395 
2396         spin_lock_irqsave(&mb0_transfer.lock, flags);
2397 
2398         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
2399                 cpu_relax();
2400 
2401         writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
2402         writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
2403 
2404         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2405 }
2406 
2407 static inline void print_unknown_header_warning(u8 n, u8 header)
2408 {
2409         pr_warn("prcmu: Unknown message header (%d) in mailbox %d\n",
2410                 header, n);
2411 }
2412 
2413 static bool read_mailbox_0(void)
2414 {
2415         bool r;
2416         u32 ev;
2417         unsigned int n;
2418         u8 header;
2419 
2420         header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0);
2421         switch (header) {
2422         case MB0H_WAKEUP_EXE:
2423         case MB0H_WAKEUP_SLEEP:
2424                 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
2425                         ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500);
2426                 else
2427                         ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500);
2428 
2429                 if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK))
2430                         complete(&mb0_transfer.ac_wake_work);
2431                 if (ev & WAKEUP_BIT_SYSCLK_OK)
2432                         complete(&mb3_transfer.sysclk_work);
2433 
2434                 ev &= mb0_transfer.req.dbb_irqs;
2435 
2436                 for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) {
2437                         if (ev & prcmu_irq_bit[n])
2438                                 generic_handle_irq(irq_find_mapping(db8500_irq_domain, n));
2439                 }
2440                 r = true;
2441                 break;
2442         default:
2443                 print_unknown_header_warning(0, header);
2444                 r = false;
2445                 break;
2446         }
2447         writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);
2448         return r;
2449 }
2450 
2451 static bool read_mailbox_1(void)
2452 {
2453         mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1);
2454         mb1_transfer.ack.arm_opp = readb(tcdm_base +
2455                 PRCM_ACK_MB1_CURRENT_ARM_OPP);
2456         mb1_transfer.ack.ape_opp = readb(tcdm_base +
2457                 PRCM_ACK_MB1_CURRENT_APE_OPP);
2458         mb1_transfer.ack.ape_voltage_status = readb(tcdm_base +
2459                 PRCM_ACK_MB1_APE_VOLTAGE_STATUS);
2460         writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);
2461         complete(&mb1_transfer.work);
2462         return false;
2463 }
2464 
2465 static bool read_mailbox_2(void)
2466 {
2467         mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS);
2468         writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);
2469         complete(&mb2_transfer.work);
2470         return false;
2471 }
2472 
2473 static bool read_mailbox_3(void)
2474 {
2475         writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);
2476         return false;
2477 }
2478 
2479 static bool read_mailbox_4(void)
2480 {
2481         u8 header;
2482         bool do_complete = true;
2483 
2484         header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4);
2485         switch (header) {
2486         case MB4H_MEM_ST:
2487         case MB4H_HOTDOG:
2488         case MB4H_HOTMON:
2489         case MB4H_HOT_PERIOD:
2490         case MB4H_A9WDOG_CONF:
2491         case MB4H_A9WDOG_EN:
2492         case MB4H_A9WDOG_DIS:
2493         case MB4H_A9WDOG_LOAD:
2494         case MB4H_A9WDOG_KICK:
2495                 break;
2496         default:
2497                 print_unknown_header_warning(4, header);
2498                 do_complete = false;
2499                 break;
2500         }
2501 
2502         writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);
2503 
2504         if (do_complete)
2505                 complete(&mb4_transfer.work);
2506 
2507         return false;
2508 }
2509 
2510 static bool read_mailbox_5(void)
2511 {
2512         mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS);
2513         mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL);
2514         writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);
2515         complete(&mb5_transfer.work);
2516         return false;
2517 }
2518 
2519 static bool read_mailbox_6(void)
2520 {
2521         writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);
2522         return false;
2523 }
2524 
2525 static bool read_mailbox_7(void)
2526 {
2527         writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);
2528         return false;
2529 }
2530 
2531 static bool (* const read_mailbox[NUM_MB])(void) = {
2532         read_mailbox_0,
2533         read_mailbox_1,
2534         read_mailbox_2,
2535         read_mailbox_3,
2536         read_mailbox_4,
2537         read_mailbox_5,
2538         read_mailbox_6,
2539         read_mailbox_7
2540 };
2541 
2542 static irqreturn_t prcmu_irq_handler(int irq, void *data)
2543 {
2544         u32 bits;
2545         u8 n;
2546         irqreturn_t r;
2547 
2548         bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);
2549         if (unlikely(!bits))
2550                 return IRQ_NONE;
2551 
2552         r = IRQ_HANDLED;
2553         for (n = 0; bits; n++) {
2554                 if (bits & MBOX_BIT(n)) {
2555                         bits -= MBOX_BIT(n);
2556                         if (read_mailbox[n]())
2557                                 r = IRQ_WAKE_THREAD;
2558                 }
2559         }
2560         return r;
2561 }
2562 
2563 static irqreturn_t prcmu_irq_thread_fn(int irq, void *data)
2564 {
2565         ack_dbb_wakeup();
2566         return IRQ_HANDLED;
2567 }
2568 
2569 static void prcmu_mask_work(struct work_struct *work)
2570 {
2571         unsigned long flags;
2572 
2573         spin_lock_irqsave(&mb0_transfer.lock, flags);
2574 
2575         config_wakeups();
2576 
2577         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2578 }
2579 
2580 static void prcmu_irq_mask(struct irq_data *d)
2581 {
2582         unsigned long flags;
2583 
2584         spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2585 
2586         mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->hwirq];
2587 
2588         spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2589 
2590         if (d->irq != IRQ_PRCMU_CA_SLEEP)
2591                 schedule_work(&mb0_transfer.mask_work);
2592 }
2593 
2594 static void prcmu_irq_unmask(struct irq_data *d)
2595 {
2596         unsigned long flags;
2597 
2598         spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2599 
2600         mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->hwirq];
2601 
2602         spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2603 
2604         if (d->irq != IRQ_PRCMU_CA_SLEEP)
2605                 schedule_work(&mb0_transfer.mask_work);
2606 }
2607 
2608 static void noop(struct irq_data *d)
2609 {
2610 }
2611 
2612 static struct irq_chip prcmu_irq_chip = {
2613         .name           = "prcmu",
2614         .irq_disable    = prcmu_irq_mask,
2615         .irq_ack        = noop,
2616         .irq_mask       = prcmu_irq_mask,
2617         .irq_unmask     = prcmu_irq_unmask,
2618 };
2619 
2620 static char *fw_project_name(u32 project)
2621 {
2622         switch (project) {
2623         case PRCMU_FW_PROJECT_U8500:
2624                 return "U8500";
2625         case PRCMU_FW_PROJECT_U8400:
2626                 return "U8400";
2627         case PRCMU_FW_PROJECT_U9500:
2628                 return "U9500";
2629         case PRCMU_FW_PROJECT_U8500_MBB:
2630                 return "U8500 MBB";
2631         case PRCMU_FW_PROJECT_U8500_C1:
2632                 return "U8500 C1";
2633         case PRCMU_FW_PROJECT_U8500_C2:
2634                 return "U8500 C2";
2635         case PRCMU_FW_PROJECT_U8500_C3:
2636                 return "U8500 C3";
2637         case PRCMU_FW_PROJECT_U8500_C4:
2638                 return "U8500 C4";
2639         case PRCMU_FW_PROJECT_U9500_MBL:
2640                 return "U9500 MBL";
2641         case PRCMU_FW_PROJECT_U8500_MBL:
2642                 return "U8500 MBL";
2643         case PRCMU_FW_PROJECT_U8500_MBL2:
2644                 return "U8500 MBL2";
2645         case PRCMU_FW_PROJECT_U8520:
2646                 return "U8520 MBL";
2647         case PRCMU_FW_PROJECT_U8420:
2648                 return "U8420";
2649         case PRCMU_FW_PROJECT_U9540:
2650                 return "U9540";
2651         case PRCMU_FW_PROJECT_A9420:
2652                 return "A9420";
2653         case PRCMU_FW_PROJECT_L8540:
2654                 return "L8540";
2655         case PRCMU_FW_PROJECT_L8580:
2656                 return "L8580";
2657         default:
2658                 return "Unknown";
2659         }
2660 }
2661 
2662 static int db8500_irq_map(struct irq_domain *d, unsigned int virq,
2663                                 irq_hw_number_t hwirq)
2664 {
2665         irq_set_chip_and_handler(virq, &prcmu_irq_chip,
2666                                 handle_simple_irq);
2667 
2668         return 0;
2669 }
2670 
2671 static const struct irq_domain_ops db8500_irq_ops = {
2672         .map    = db8500_irq_map,
2673         .xlate  = irq_domain_xlate_twocell,
2674 };
2675 
2676 static int db8500_irq_init(struct device_node *np)
2677 {
2678         int i;
2679 
2680         db8500_irq_domain = irq_domain_add_simple(
2681                 np, NUM_PRCMU_WAKEUPS, 0,
2682                 &db8500_irq_ops, NULL);
2683 
2684         if (!db8500_irq_domain) {
2685                 pr_err("Failed to create irqdomain\n");
2686                 return -ENOSYS;
2687         }
2688 
2689         /* All wakeups will be used, so create mappings for all */
2690         for (i = 0; i < NUM_PRCMU_WAKEUPS; i++)
2691                 irq_create_mapping(db8500_irq_domain, i);
2692 
2693         return 0;
2694 }
2695 
2696 static void dbx500_fw_version_init(struct platform_device *pdev,
2697                             u32 version_offset)
2698 {
2699         struct resource *res;
2700         void __iomem *tcpm_base;
2701         u32 version;
2702 
2703         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2704                                            "prcmu-tcpm");
2705         if (!res) {
2706                 dev_err(&pdev->dev,
2707                         "Error: no prcmu tcpm memory region provided\n");
2708                 return;
2709         }
2710         tcpm_base = ioremap(res->start, resource_size(res));
2711         if (!tcpm_base) {
2712                 dev_err(&pdev->dev, "no prcmu tcpm mem region provided\n");
2713                 return;
2714         }
2715 
2716         version = readl(tcpm_base + version_offset);
2717         fw_info.version.project = (version & 0xFF);
2718         fw_info.version.api_version = (version >> 8) & 0xFF;
2719         fw_info.version.func_version = (version >> 16) & 0xFF;
2720         fw_info.version.errata = (version >> 24) & 0xFF;
2721         strncpy(fw_info.version.project_name,
2722                 fw_project_name(fw_info.version.project),
2723                 PRCMU_FW_PROJECT_NAME_LEN);
2724         fw_info.valid = true;
2725         pr_info("PRCMU firmware: %s(%d), version %d.%d.%d\n",
2726                 fw_info.version.project_name,
2727                 fw_info.version.project,
2728                 fw_info.version.api_version,
2729                 fw_info.version.func_version,
2730                 fw_info.version.errata);
2731         iounmap(tcpm_base);
2732 }
2733 
2734 void __init db8500_prcmu_early_init(u32 phy_base, u32 size)
2735 {
2736         /*
2737          * This is a temporary remap to bring up the clocks. It is
2738          * subsequently replaces with a real remap. After the merge of
2739          * the mailbox subsystem all of this early code goes away, and the
2740          * clock driver can probe independently. An early initcall will
2741          * still be needed, but it can be diverted into drivers/clk/ux500.
2742          */
2743         prcmu_base = ioremap(phy_base, size);
2744         if (!prcmu_base)
2745                 pr_err("%s: ioremap() of prcmu registers failed!\n", __func__);
2746 
2747         spin_lock_init(&mb0_transfer.lock);
2748         spin_lock_init(&mb0_transfer.dbb_irqs_lock);
2749         mutex_init(&mb0_transfer.ac_wake_lock);
2750         init_completion(&mb0_transfer.ac_wake_work);
2751         mutex_init(&mb1_transfer.lock);
2752         init_completion(&mb1_transfer.work);
2753         mb1_transfer.ape_opp = APE_NO_CHANGE;
2754         mutex_init(&mb2_transfer.lock);
2755         init_completion(&mb2_transfer.work);
2756         spin_lock_init(&mb2_transfer.auto_pm_lock);
2757         spin_lock_init(&mb3_transfer.lock);
2758         mutex_init(&mb3_transfer.sysclk_lock);
2759         init_completion(&mb3_transfer.sysclk_work);
2760         mutex_init(&mb4_transfer.lock);
2761         init_completion(&mb4_transfer.work);
2762         mutex_init(&mb5_transfer.lock);
2763         init_completion(&mb5_transfer.work);
2764 
2765         INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work);
2766 }
2767 
2768 static void init_prcm_registers(void)
2769 {
2770         u32 val;
2771 
2772         val = readl(PRCM_A9PL_FORCE_CLKEN);
2773         val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN |
2774                 PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN);
2775         writel(val, (PRCM_A9PL_FORCE_CLKEN));
2776 }
2777 
2778 /*
2779  * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC
2780  */
2781 static struct regulator_consumer_supply db8500_vape_consumers[] = {
2782         REGULATOR_SUPPLY("v-ape", NULL),
2783         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"),
2784         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"),
2785         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"),
2786         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"),
2787         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"),
2788         /* "v-mmc" changed to "vcore" in the mainline kernel */
2789         REGULATOR_SUPPLY("vcore", "sdi0"),
2790         REGULATOR_SUPPLY("vcore", "sdi1"),
2791         REGULATOR_SUPPLY("vcore", "sdi2"),
2792         REGULATOR_SUPPLY("vcore", "sdi3"),
2793         REGULATOR_SUPPLY("vcore", "sdi4"),
2794         REGULATOR_SUPPLY("v-dma", "dma40.0"),
2795         REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"),
2796         /* "v-uart" changed to "vcore" in the mainline kernel */
2797         REGULATOR_SUPPLY("vcore", "uart0"),
2798         REGULATOR_SUPPLY("vcore", "uart1"),
2799         REGULATOR_SUPPLY("vcore", "uart2"),
2800         REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"),
2801         REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"),
2802         REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
2803 };
2804 
2805 static struct regulator_consumer_supply db8500_vsmps2_consumers[] = {
2806         REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"),
2807         /* AV8100 regulator */
2808         REGULATOR_SUPPLY("hdmi_1v8", "0-0070"),
2809 };
2810 
2811 static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = {
2812         REGULATOR_SUPPLY("vsupply", "b2r2_bus"),
2813         REGULATOR_SUPPLY("vsupply", "mcde"),
2814 };
2815 
2816 /* SVA MMDSP regulator switch */
2817 static struct regulator_consumer_supply db8500_svammdsp_consumers[] = {
2818         REGULATOR_SUPPLY("sva-mmdsp", "cm_control"),
2819 };
2820 
2821 /* SVA pipe regulator switch */
2822 static struct regulator_consumer_supply db8500_svapipe_consumers[] = {
2823         REGULATOR_SUPPLY("sva-pipe", "cm_control"),
2824 };
2825 
2826 /* SIA MMDSP regulator switch */
2827 static struct regulator_consumer_supply db8500_siammdsp_consumers[] = {
2828         REGULATOR_SUPPLY("sia-mmdsp", "cm_control"),
2829 };
2830 
2831 /* SIA pipe regulator switch */
2832 static struct regulator_consumer_supply db8500_siapipe_consumers[] = {
2833         REGULATOR_SUPPLY("sia-pipe", "cm_control"),
2834 };
2835 
2836 static struct regulator_consumer_supply db8500_sga_consumers[] = {
2837         REGULATOR_SUPPLY("v-mali", NULL),
2838 };
2839 
2840 /* ESRAM1 and 2 regulator switch */
2841 static struct regulator_consumer_supply db8500_esram12_consumers[] = {
2842         REGULATOR_SUPPLY("esram12", "cm_control"),
2843 };
2844 
2845 /* ESRAM3 and 4 regulator switch */
2846 static struct regulator_consumer_supply db8500_esram34_consumers[] = {
2847         REGULATOR_SUPPLY("v-esram34", "mcde"),
2848         REGULATOR_SUPPLY("esram34", "cm_control"),
2849         REGULATOR_SUPPLY("lcla_esram", "dma40.0"),
2850 };
2851 
2852 static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = {
2853         [DB8500_REGULATOR_VAPE] = {
2854                 .constraints = {
2855                         .name = "db8500-vape",
2856                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2857                         .always_on = true,
2858                 },
2859                 .consumer_supplies = db8500_vape_consumers,
2860                 .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers),
2861         },
2862         [DB8500_REGULATOR_VARM] = {
2863                 .constraints = {
2864                         .name = "db8500-varm",
2865                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2866                 },
2867         },
2868         [DB8500_REGULATOR_VMODEM] = {
2869                 .constraints = {
2870                         .name = "db8500-vmodem",
2871                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2872                 },
2873         },
2874         [DB8500_REGULATOR_VPLL] = {
2875                 .constraints = {
2876                         .name = "db8500-vpll",
2877                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2878                 },
2879         },
2880         [DB8500_REGULATOR_VSMPS1] = {
2881                 .constraints = {
2882                         .name = "db8500-vsmps1",
2883                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2884                 },
2885         },
2886         [DB8500_REGULATOR_VSMPS2] = {
2887                 .constraints = {
2888                         .name = "db8500-vsmps2",
2889                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2890                 },
2891                 .consumer_supplies = db8500_vsmps2_consumers,
2892                 .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers),
2893         },
2894         [DB8500_REGULATOR_VSMPS3] = {
2895                 .constraints = {
2896                         .name = "db8500-vsmps3",
2897                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2898                 },
2899         },
2900         [DB8500_REGULATOR_VRF1] = {
2901                 .constraints = {
2902                         .name = "db8500-vrf1",
2903                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2904                 },
2905         },
2906         [DB8500_REGULATOR_SWITCH_SVAMMDSP] = {
2907                 /* dependency to u8500-vape is handled outside regulator framework */
2908                 .constraints = {
2909                         .name = "db8500-sva-mmdsp",
2910                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2911                 },
2912                 .consumer_supplies = db8500_svammdsp_consumers,
2913                 .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers),
2914         },
2915         [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = {
2916                 .constraints = {
2917                         /* "ret" means "retention" */
2918                         .name = "db8500-sva-mmdsp-ret",
2919                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2920                 },
2921         },
2922         [DB8500_REGULATOR_SWITCH_SVAPIPE] = {
2923                 /* dependency to u8500-vape is handled outside regulator framework */
2924                 .constraints = {
2925                         .name = "db8500-sva-pipe",
2926                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2927                 },
2928                 .consumer_supplies = db8500_svapipe_consumers,
2929                 .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers),
2930         },
2931         [DB8500_REGULATOR_SWITCH_SIAMMDSP] = {
2932                 /* dependency to u8500-vape is handled outside regulator framework */
2933                 .constraints = {
2934                         .name = "db8500-sia-mmdsp",
2935                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2936                 },
2937                 .consumer_supplies = db8500_siammdsp_consumers,
2938                 .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers),
2939         },
2940         [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = {
2941                 .constraints = {
2942                         .name = "db8500-sia-mmdsp-ret",
2943                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2944                 },
2945         },
2946         [DB8500_REGULATOR_SWITCH_SIAPIPE] = {
2947                 /* dependency to u8500-vape is handled outside regulator framework */
2948                 .constraints = {
2949                         .name = "db8500-sia-pipe",
2950                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2951                 },
2952                 .consumer_supplies = db8500_siapipe_consumers,
2953                 .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers),
2954         },
2955         [DB8500_REGULATOR_SWITCH_SGA] = {
2956                 .supply_regulator = "db8500-vape",
2957                 .constraints = {
2958                         .name = "db8500-sga",
2959                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2960                 },
2961                 .consumer_supplies = db8500_sga_consumers,
2962                 .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers),
2963 
2964         },
2965         [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = {
2966                 .supply_regulator = "db8500-vape",
2967                 .constraints = {
2968                         .name = "db8500-b2r2-mcde",
2969                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2970                 },
2971                 .consumer_supplies = db8500_b2r2_mcde_consumers,
2972                 .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers),
2973         },
2974         [DB8500_REGULATOR_SWITCH_ESRAM12] = {
2975                 /*
2976                  * esram12 is set in retention and supplied by Vsafe when Vape is off,
2977                  * no need to hold Vape
2978                  */
2979                 .constraints = {
2980                         .name = "db8500-esram12",
2981                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2982                 },
2983                 .consumer_supplies = db8500_esram12_consumers,
2984                 .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers),
2985         },
2986         [DB8500_REGULATOR_SWITCH_ESRAM12RET] = {
2987                 .constraints = {
2988                         .name = "db8500-esram12-ret",
2989                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2990                 },
2991         },
2992         [DB8500_REGULATOR_SWITCH_ESRAM34] = {
2993                 /*
2994                  * esram34 is set in retention and supplied by Vsafe when Vape is off,
2995                  * no need to hold Vape
2996                  */
2997                 .constraints = {
2998                         .name = "db8500-esram34",
2999                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3000                 },
3001                 .consumer_supplies = db8500_esram34_consumers,
3002                 .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers),
3003         },
3004         [DB8500_REGULATOR_SWITCH_ESRAM34RET] = {
3005                 .constraints = {
3006                         .name = "db8500-esram34-ret",
3007                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3008                 },
3009         },
3010 };
3011 
3012 static struct ux500_wdt_data db8500_wdt_pdata = {
3013         .timeout = 600, /* 10 minutes */
3014         .has_28_bits_resolution = true,
3015 };
3016 
3017 static const struct mfd_cell common_prcmu_devs[] = {
3018         {
3019                 .name = "ux500_wdt",
3020                 .platform_data = &db8500_wdt_pdata,
3021                 .pdata_size = sizeof(db8500_wdt_pdata),
3022                 .id = -1,
3023         },
3024 };
3025 
3026 static const struct mfd_cell db8500_prcmu_devs[] = {
3027         {
3028                 .name = "db8500-prcmu-regulators",
3029                 .of_compatible = "stericsson,db8500-prcmu-regulator",
3030                 .platform_data = &db8500_regulators,
3031                 .pdata_size = sizeof(db8500_regulators),
3032         },
3033         {
3034                 .name = "cpuidle-dbx500",
3035                 .of_compatible = "stericsson,cpuidle-dbx500",
3036         },
3037         {
3038                 .name = "db8500-thermal",
3039                 .of_compatible = "stericsson,db8500-thermal",
3040         },
3041 };
3042 
3043 static int db8500_prcmu_register_ab8500(struct device *parent)
3044 {
3045         struct device_node *np;
3046         struct resource ab8500_resource;
3047         const struct mfd_cell ab8500_cell = {
3048                 .name = "ab8500-core",
3049                 .of_compatible = "stericsson,ab8500",
3050                 .id = AB8500_VERSION_AB8500,
3051                 .resources = &ab8500_resource,
3052                 .num_resources = 1,
3053         };
3054 
3055         if (!parent->of_node)
3056                 return -ENODEV;
3057 
3058         /* Look up the device node, sneak the IRQ out of it */
3059         for_each_child_of_node(parent->of_node, np) {
3060                 if (of_device_is_compatible(np, ab8500_cell.of_compatible))
3061                         break;
3062         }
3063         if (!np) {
3064                 dev_info(parent, "could not find AB8500 node in the device tree\n");
3065                 return -ENODEV;
3066         }
3067         of_irq_to_resource_table(np, &ab8500_resource, 1);
3068 
3069         return mfd_add_devices(parent, 0, &ab8500_cell, 1, NULL, 0, NULL);
3070 }
3071 
3072 /**
3073  * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
3074  *
3075  */
3076 static int db8500_prcmu_probe(struct platform_device *pdev)
3077 {
3078         struct device_node *np = pdev->dev.of_node;
3079         int irq = 0, err = 0;
3080         struct resource *res;
3081 
3082         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu");
3083         if (!res) {
3084                 dev_err(&pdev->dev, "no prcmu memory region provided\n");
3085                 return -EINVAL;
3086         }
3087         prcmu_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
3088         if (!prcmu_base) {
3089                 dev_err(&pdev->dev,
3090                         "failed to ioremap prcmu register memory\n");
3091                 return -ENOMEM;
3092         }
3093         init_prcm_registers();
3094         dbx500_fw_version_init(pdev, DB8500_PRCMU_FW_VERSION_OFFSET);
3095         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu-tcdm");
3096         if (!res) {
3097                 dev_err(&pdev->dev, "no prcmu tcdm region provided\n");
3098                 return -EINVAL;
3099         }
3100         tcdm_base = devm_ioremap(&pdev->dev, res->start,
3101                         resource_size(res));
3102         if (!tcdm_base) {
3103                 dev_err(&pdev->dev,
3104                         "failed to ioremap prcmu-tcdm register memory\n");
3105                 return -ENOMEM;
3106         }
3107 
3108         /* Clean up the mailbox interrupts after pre-kernel code. */
3109         writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);
3110 
3111         irq = platform_get_irq(pdev, 0);
3112         if (irq <= 0)
3113                 return irq;
3114 
3115         err = request_threaded_irq(irq, prcmu_irq_handler,
3116                 prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL);
3117         if (err < 0) {
3118                 pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n");
3119                 return err;
3120         }
3121 
3122         db8500_irq_init(np);
3123 
3124         prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
3125 
3126         err = mfd_add_devices(&pdev->dev, 0, common_prcmu_devs,
3127                               ARRAY_SIZE(common_prcmu_devs), NULL, 0, db8500_irq_domain);
3128         if (err) {
3129                 pr_err("prcmu: Failed to add subdevices\n");
3130                 return err;
3131         }
3132 
3133         /* TODO: Remove restriction when clk definitions are available. */
3134         if (!of_machine_is_compatible("st-ericsson,u8540")) {
3135                 err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs,
3136                                       ARRAY_SIZE(db8500_prcmu_devs), NULL, 0,
3137                                       db8500_irq_domain);
3138                 if (err) {
3139                         mfd_remove_devices(&pdev->dev);
3140                         pr_err("prcmu: Failed to add subdevices\n");
3141                         return err;
3142                 }
3143         }
3144 
3145         err = db8500_prcmu_register_ab8500(&pdev->dev);
3146         if (err) {
3147                 mfd_remove_devices(&pdev->dev);
3148                 pr_err("prcmu: Failed to add ab8500 subdevice\n");
3149                 return err;
3150         }
3151 
3152         pr_info("DB8500 PRCMU initialized\n");
3153         return err;
3154 }
3155 static const struct of_device_id db8500_prcmu_match[] = {
3156         { .compatible = "stericsson,db8500-prcmu"},
3157         { },
3158 };
3159 
3160 static struct platform_driver db8500_prcmu_driver = {
3161         .driver = {
3162                 .name = "db8500-prcmu",
3163                 .of_match_table = db8500_prcmu_match,
3164         },
3165         .probe = db8500_prcmu_probe,
3166 };
3167 
3168 static int __init db8500_prcmu_init(void)
3169 {
3170         return platform_driver_register(&db8500_prcmu_driver);
3171 }
3172 core_initcall(db8500_prcmu_init);
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/mfd/db8500-prcmu.c

DEFINITIONS
