1
2
3 #ifndef HISI_ACC_QM_H
4 #define HISI_ACC_QM_H
5
6 #include <linux/bitfield.h>
7 #include <linux/iopoll.h>
8 #include <linux/module.h>
9 #include <linux/pci.h>
10
11
12 #define QM_ARUSER_M_CFG_1 0x100088
13 #define AXUSER_SNOOP_ENABLE BIT(30)
14 #define AXUSER_CMD_TYPE GENMASK(14, 12)
15 #define AXUSER_CMD_SMMU_NORMAL 1
16 #define AXUSER_NS BIT(6)
17 #define AXUSER_NO BIT(5)
18 #define AXUSER_FP BIT(4)
19 #define AXUSER_SSV BIT(0)
20 #define AXUSER_BASE (AXUSER_SNOOP_ENABLE | \
21 FIELD_PREP(AXUSER_CMD_TYPE, \
22 AXUSER_CMD_SMMU_NORMAL) | \
23 AXUSER_NS | AXUSER_NO | AXUSER_FP)
24 #define QM_ARUSER_M_CFG_ENABLE 0x100090
25 #define ARUSER_M_CFG_ENABLE 0xfffffffe
26 #define QM_AWUSER_M_CFG_1 0x100098
27 #define QM_AWUSER_M_CFG_ENABLE 0x1000a0
28 #define AWUSER_M_CFG_ENABLE 0xfffffffe
29 #define QM_WUSER_M_CFG_ENABLE 0x1000a8
30 #define WUSER_M_CFG_ENABLE 0xffffffff
31
32
33 #define QM_CACHE_CTL 0x100050
34 #define SQC_CACHE_ENABLE BIT(0)
35 #define CQC_CACHE_ENABLE BIT(1)
36 #define SQC_CACHE_WB_ENABLE BIT(4)
37 #define SQC_CACHE_WB_THRD GENMASK(10, 5)
38 #define CQC_CACHE_WB_ENABLE BIT(11)
39 #define CQC_CACHE_WB_THRD GENMASK(17, 12)
40 #define QM_AXI_M_CFG 0x1000ac
41 #define AXI_M_CFG 0xffff
42 #define QM_AXI_M_CFG_ENABLE 0x1000b0
43 #define AXI_M_CFG_ENABLE 0xffffffff
44 #define QM_PEH_AXUSER_CFG 0x1000cc
45 #define QM_PEH_AXUSER_CFG_ENABLE 0x1000d0
46 #define PEH_AXUSER_CFG 0x401001
47 #define PEH_AXUSER_CFG_ENABLE 0xffffffff
48
49 #define QM_DFX_MB_CNT_VF 0x104010
50 #define QM_DFX_DB_CNT_VF 0x104020
51 #define QM_DFX_SQE_CNT_VF_SQN 0x104030
52 #define QM_DFX_CQE_CNT_VF_CQN 0x104040
53 #define QM_DFX_QN_SHIFT 16
54 #define CURRENT_FUN_MASK GENMASK(5, 0)
55 #define CURRENT_Q_MASK GENMASK(31, 16)
56
57 #define QM_AXI_RRESP BIT(0)
58 #define QM_AXI_BRESP BIT(1)
59 #define QM_ECC_MBIT BIT(2)
60 #define QM_ECC_1BIT BIT(3)
61 #define QM_ACC_GET_TASK_TIMEOUT BIT(4)
62 #define QM_ACC_DO_TASK_TIMEOUT BIT(5)
63 #define QM_ACC_WB_NOT_READY_TIMEOUT BIT(6)
64 #define QM_SQ_CQ_VF_INVALID BIT(7)
65 #define QM_CQ_VF_INVALID BIT(8)
66 #define QM_SQ_VF_INVALID BIT(9)
67 #define QM_DB_TIMEOUT BIT(10)
68 #define QM_OF_FIFO_OF BIT(11)
69 #define QM_DB_RANDOM_INVALID BIT(12)
70
71 #define QM_BASE_NFE (QM_AXI_RRESP | QM_AXI_BRESP | QM_ECC_MBIT | \
72 QM_ACC_GET_TASK_TIMEOUT | QM_DB_TIMEOUT | \
73 QM_OF_FIFO_OF)
74 #define QM_BASE_CE QM_ECC_1BIT
75
76 #define QM_Q_DEPTH 1024
77
78 enum qp_state {
79 QP_STOP,
80 };
81
82 enum qm_hw_ver {
83 QM_HW_UNKNOWN = -1,
84 QM_HW_V1 = 0x20,
85 QM_HW_V2 = 0x21,
86 };
87
88 enum qm_fun_type {
89 QM_HW_PF,
90 QM_HW_VF,
91 };
92
93 enum qm_debug_file {
94 CURRENT_Q,
95 CLEAR_ENABLE,
96 DEBUG_FILE_NUM,
97 };
98
99 struct debugfs_file {
100 enum qm_debug_file index;
101 struct mutex lock;
102 struct qm_debug *debug;
103 };
104
105 struct qm_debug {
106 u32 curr_qm_qp_num;
107 struct dentry *debug_root;
108 struct dentry *qm_d;
109 struct debugfs_file files[DEBUG_FILE_NUM];
110 };
111
112 struct qm_dma {
113 void *va;
114 dma_addr_t dma;
115 size_t size;
116 };
117
118 struct hisi_qm_status {
119 u32 eq_head;
120 bool eqc_phase;
121 u32 aeq_head;
122 bool aeqc_phase;
123 unsigned long flags;
124 };
125
126 struct hisi_qm {
127 enum qm_hw_ver ver;
128 enum qm_fun_type fun_type;
129 const char *dev_name;
130 struct pci_dev *pdev;
131 void __iomem *io_base;
132 u32 sqe_size;
133 u32 qp_base;
134 u32 qp_num;
135 u32 ctrl_qp_num;
136
137 struct qm_dma qdma;
138 struct qm_sqc *sqc;
139 struct qm_cqc *cqc;
140 struct qm_eqe *eqe;
141 struct qm_aeqe *aeqe;
142 dma_addr_t sqc_dma;
143 dma_addr_t cqc_dma;
144 dma_addr_t eqe_dma;
145 dma_addr_t aeqe_dma;
146
147 struct hisi_qm_status status;
148
149 rwlock_t qps_lock;
150 unsigned long *qp_bitmap;
151 struct hisi_qp **qp_array;
152
153 struct mutex mailbox_lock;
154
155 const struct hisi_qm_hw_ops *ops;
156
157 struct qm_debug debug;
158
159 u32 error_mask;
160 u32 msi_mask;
161
162 bool use_dma_api;
163 };
164
165 struct hisi_qp_status {
166 atomic_t used;
167 u16 sq_tail;
168 u16 cq_head;
169 bool cqc_phase;
170 unsigned long flags;
171 };
172
173 struct hisi_qp_ops {
174 int (*fill_sqe)(void *sqe, void *q_parm, void *d_parm);
175 };
176
177 struct hisi_qp {
178 u32 qp_id;
179 u8 alg_type;
180 u8 req_type;
181
182 struct qm_dma qdma;
183 void *sqe;
184 struct qm_cqe *cqe;
185 dma_addr_t sqe_dma;
186 dma_addr_t cqe_dma;
187
188 struct hisi_qp_status qp_status;
189 struct hisi_qp_ops *hw_ops;
190 void *qp_ctx;
191 void (*req_cb)(struct hisi_qp *qp, void *data);
192 struct work_struct work;
193 struct workqueue_struct *wq;
194
195 struct hisi_qm *qm;
196 };
197
198 int hisi_qm_init(struct hisi_qm *qm);
199 void hisi_qm_uninit(struct hisi_qm *qm);
200 int hisi_qm_start(struct hisi_qm *qm);
201 int hisi_qm_stop(struct hisi_qm *qm);
202 struct hisi_qp *hisi_qm_create_qp(struct hisi_qm *qm, u8 alg_type);
203 int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg);
204 int hisi_qm_stop_qp(struct hisi_qp *qp);
205 void hisi_qm_release_qp(struct hisi_qp *qp);
206 int hisi_qp_send(struct hisi_qp *qp, const void *msg);
207 int hisi_qm_get_vft(struct hisi_qm *qm, u32 *base, u32 *number);
208 int hisi_qm_set_vft(struct hisi_qm *qm, u32 fun_num, u32 base, u32 number);
209 int hisi_qm_debug_init(struct hisi_qm *qm);
210 void hisi_qm_hw_error_init(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe,
211 u32 msi);
212 int hisi_qm_hw_error_handle(struct hisi_qm *qm);
213 enum qm_hw_ver hisi_qm_get_hw_version(struct pci_dev *pdev);
214 void hisi_qm_debug_regs_clear(struct hisi_qm *qm);
215 #endif