root/drivers/crypto/marvell/cesa.h

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INCLUDED FROM

DEFINITIONS

This source file includes following definitions.
  1. mv_cesa_engine_enqueue_complete_request
  2. mv_cesa_engine_dequeue_complete_request
  3. mv_cesa_req_get_type
  4. mv_cesa_update_op_cfg
  5. mv_cesa_get_op_cfg
  6. mv_cesa_set_op_cfg
  7. mv_cesa_adjust_op
  8. mv_cesa_set_crypt_op_len
  9. mv_cesa_set_mac_op_total_len
  10. mv_cesa_set_mac_op_frag_len
  11. mv_cesa_set_int_mask
  12. mv_cesa_get_int_mask
  13. mv_cesa_mac_op_is_first_frag
  14. mv_cesa_select_engine
  15. mv_cesa_req_needs_cleanup
  16. mv_cesa_req_dma_iter_init
  17. mv_cesa_sg_dma_iter_init
  18. mv_cesa_req_dma_iter_transfer_len
  19. mv_cesa_req_dma_iter_next_op
  20. mv_cesa_dma_process
  21. mv_cesa_tdma_desc_iter_init
   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __MARVELL_CESA_H__
   3 #define __MARVELL_CESA_H__
   4 
   5 #include <crypto/algapi.h>
   6 #include <crypto/hash.h>
   7 #include <crypto/internal/hash.h>
   8 #include <crypto/internal/skcipher.h>
   9 
  10 #include <linux/crypto.h>
  11 #include <linux/dmapool.h>
  12 
  13 #define CESA_ENGINE_OFF(i)                      (((i) * 0x2000))
  14 
  15 #define CESA_TDMA_BYTE_CNT                      0x800
  16 #define CESA_TDMA_SRC_ADDR                      0x810
  17 #define CESA_TDMA_DST_ADDR                      0x820
  18 #define CESA_TDMA_NEXT_ADDR                     0x830
  19 
  20 #define CESA_TDMA_CONTROL                       0x840
  21 #define CESA_TDMA_DST_BURST                     GENMASK(2, 0)
  22 #define CESA_TDMA_DST_BURST_32B                 3
  23 #define CESA_TDMA_DST_BURST_128B                4
  24 #define CESA_TDMA_OUT_RD_EN                     BIT(4)
  25 #define CESA_TDMA_SRC_BURST                     GENMASK(8, 6)
  26 #define CESA_TDMA_SRC_BURST_32B                 (3 << 6)
  27 #define CESA_TDMA_SRC_BURST_128B                (4 << 6)
  28 #define CESA_TDMA_CHAIN                         BIT(9)
  29 #define CESA_TDMA_BYTE_SWAP                     BIT(11)
  30 #define CESA_TDMA_NO_BYTE_SWAP                  BIT(11)
  31 #define CESA_TDMA_EN                            BIT(12)
  32 #define CESA_TDMA_FETCH_ND                      BIT(13)
  33 #define CESA_TDMA_ACT                           BIT(14)
  34 
  35 #define CESA_TDMA_CUR                           0x870
  36 #define CESA_TDMA_ERROR_CAUSE                   0x8c8
  37 #define CESA_TDMA_ERROR_MSK                     0x8cc
  38 
  39 #define CESA_TDMA_WINDOW_BASE(x)                (((x) * 0x8) + 0xa00)
  40 #define CESA_TDMA_WINDOW_CTRL(x)                (((x) * 0x8) + 0xa04)
  41 
  42 #define CESA_IVDIG(x)                           (0xdd00 + ((x) * 4) +   \
  43                                                  (((x) < 5) ? 0 : 0x14))
  44 
  45 #define CESA_SA_CMD                             0xde00
  46 #define CESA_SA_CMD_EN_CESA_SA_ACCL0            BIT(0)
  47 #define CESA_SA_CMD_EN_CESA_SA_ACCL1            BIT(1)
  48 #define CESA_SA_CMD_DISABLE_SEC                 BIT(2)
  49 
  50 #define CESA_SA_DESC_P0                         0xde04
  51 
  52 #define CESA_SA_DESC_P1                         0xde14
  53 
  54 #define CESA_SA_CFG                             0xde08
  55 #define CESA_SA_CFG_STOP_DIG_ERR                GENMASK(1, 0)
  56 #define CESA_SA_CFG_DIG_ERR_CONT                0
  57 #define CESA_SA_CFG_DIG_ERR_SKIP                1
  58 #define CESA_SA_CFG_DIG_ERR_STOP                3
  59 #define CESA_SA_CFG_CH0_W_IDMA                  BIT(7)
  60 #define CESA_SA_CFG_CH1_W_IDMA                  BIT(8)
  61 #define CESA_SA_CFG_ACT_CH0_IDMA                BIT(9)
  62 #define CESA_SA_CFG_ACT_CH1_IDMA                BIT(10)
  63 #define CESA_SA_CFG_MULTI_PKT                   BIT(11)
  64 #define CESA_SA_CFG_PARA_DIS                    BIT(13)
  65 
  66 #define CESA_SA_ACCEL_STATUS                    0xde0c
  67 #define CESA_SA_ST_ACT_0                        BIT(0)
  68 #define CESA_SA_ST_ACT_1                        BIT(1)
  69 
  70 /*
  71  * CESA_SA_FPGA_INT_STATUS looks like a FPGA leftover and is documented only
  72  * in Errata 4.12. It looks like that it was part of an IRQ-controller in FPGA
  73  * and someone forgot to remove  it while switching to the core and moving to
  74  * CESA_SA_INT_STATUS.
  75  */
  76 #define CESA_SA_FPGA_INT_STATUS                 0xdd68
  77 #define CESA_SA_INT_STATUS                      0xde20
  78 #define CESA_SA_INT_AUTH_DONE                   BIT(0)
  79 #define CESA_SA_INT_DES_E_DONE                  BIT(1)
  80 #define CESA_SA_INT_AES_E_DONE                  BIT(2)
  81 #define CESA_SA_INT_AES_D_DONE                  BIT(3)
  82 #define CESA_SA_INT_ENC_DONE                    BIT(4)
  83 #define CESA_SA_INT_ACCEL0_DONE                 BIT(5)
  84 #define CESA_SA_INT_ACCEL1_DONE                 BIT(6)
  85 #define CESA_SA_INT_ACC0_IDMA_DONE              BIT(7)
  86 #define CESA_SA_INT_ACC1_IDMA_DONE              BIT(8)
  87 #define CESA_SA_INT_IDMA_DONE                   BIT(9)
  88 #define CESA_SA_INT_IDMA_OWN_ERR                BIT(10)
  89 
  90 #define CESA_SA_INT_MSK                         0xde24
  91 
  92 #define CESA_SA_DESC_CFG_OP_MAC_ONLY            0
  93 #define CESA_SA_DESC_CFG_OP_CRYPT_ONLY          1
  94 #define CESA_SA_DESC_CFG_OP_MAC_CRYPT           2
  95 #define CESA_SA_DESC_CFG_OP_CRYPT_MAC           3
  96 #define CESA_SA_DESC_CFG_OP_MSK                 GENMASK(1, 0)
  97 #define CESA_SA_DESC_CFG_MACM_SHA256            (1 << 4)
  98 #define CESA_SA_DESC_CFG_MACM_HMAC_SHA256       (3 << 4)
  99 #define CESA_SA_DESC_CFG_MACM_MD5               (4 << 4)
 100 #define CESA_SA_DESC_CFG_MACM_SHA1              (5 << 4)
 101 #define CESA_SA_DESC_CFG_MACM_HMAC_MD5          (6 << 4)
 102 #define CESA_SA_DESC_CFG_MACM_HMAC_SHA1         (7 << 4)
 103 #define CESA_SA_DESC_CFG_MACM_MSK               GENMASK(6, 4)
 104 #define CESA_SA_DESC_CFG_CRYPTM_DES             (1 << 8)
 105 #define CESA_SA_DESC_CFG_CRYPTM_3DES            (2 << 8)
 106 #define CESA_SA_DESC_CFG_CRYPTM_AES             (3 << 8)
 107 #define CESA_SA_DESC_CFG_CRYPTM_MSK             GENMASK(9, 8)
 108 #define CESA_SA_DESC_CFG_DIR_ENC                (0 << 12)
 109 #define CESA_SA_DESC_CFG_DIR_DEC                (1 << 12)
 110 #define CESA_SA_DESC_CFG_CRYPTCM_ECB            (0 << 16)
 111 #define CESA_SA_DESC_CFG_CRYPTCM_CBC            (1 << 16)
 112 #define CESA_SA_DESC_CFG_CRYPTCM_MSK            BIT(16)
 113 #define CESA_SA_DESC_CFG_3DES_EEE               (0 << 20)
 114 #define CESA_SA_DESC_CFG_3DES_EDE               (1 << 20)
 115 #define CESA_SA_DESC_CFG_AES_LEN_128            (0 << 24)
 116 #define CESA_SA_DESC_CFG_AES_LEN_192            (1 << 24)
 117 #define CESA_SA_DESC_CFG_AES_LEN_256            (2 << 24)
 118 #define CESA_SA_DESC_CFG_AES_LEN_MSK            GENMASK(25, 24)
 119 #define CESA_SA_DESC_CFG_NOT_FRAG               (0 << 30)
 120 #define CESA_SA_DESC_CFG_FIRST_FRAG             (1 << 30)
 121 #define CESA_SA_DESC_CFG_LAST_FRAG              (2 << 30)
 122 #define CESA_SA_DESC_CFG_MID_FRAG               (3 << 30)
 123 #define CESA_SA_DESC_CFG_FRAG_MSK               GENMASK(31, 30)
 124 
 125 /*
 126  * /-----------\ 0
 127  * | ACCEL CFG |        4 * 8
 128  * |-----------| 0x20
 129  * | CRYPT KEY |        8 * 4
 130  * |-----------| 0x40
 131  * |  IV   IN  |        4 * 4
 132  * |-----------| 0x40 (inplace)
 133  * |  IV BUF   |        4 * 4
 134  * |-----------| 0x80
 135  * |  DATA IN  |        16 * x (max ->max_req_size)
 136  * |-----------| 0x80 (inplace operation)
 137  * |  DATA OUT |        16 * x (max ->max_req_size)
 138  * \-----------/ SRAM size
 139  */
 140 
 141 /*
 142  * Hashing memory map:
 143  * /-----------\ 0
 144  * | ACCEL CFG |        4 * 8
 145  * |-----------| 0x20
 146  * | Inner IV  |        8 * 4
 147  * |-----------| 0x40
 148  * | Outer IV  |        8 * 4
 149  * |-----------| 0x60
 150  * | Output BUF|        8 * 4
 151  * |-----------| 0x80
 152  * |  DATA IN  |        64 * x (max ->max_req_size)
 153  * \-----------/ SRAM size
 154  */
 155 
 156 #define CESA_SA_CFG_SRAM_OFFSET                 0x00
 157 #define CESA_SA_DATA_SRAM_OFFSET                0x80
 158 
 159 #define CESA_SA_CRYPT_KEY_SRAM_OFFSET           0x20
 160 #define CESA_SA_CRYPT_IV_SRAM_OFFSET            0x40
 161 
 162 #define CESA_SA_MAC_IIV_SRAM_OFFSET             0x20
 163 #define CESA_SA_MAC_OIV_SRAM_OFFSET             0x40
 164 #define CESA_SA_MAC_DIG_SRAM_OFFSET             0x60
 165 
 166 #define CESA_SA_DESC_CRYPT_DATA(offset)                                 \
 167         cpu_to_le32((CESA_SA_DATA_SRAM_OFFSET + (offset)) |             \
 168                     ((CESA_SA_DATA_SRAM_OFFSET + (offset)) << 16))
 169 
 170 #define CESA_SA_DESC_CRYPT_IV(offset)                                   \
 171         cpu_to_le32((CESA_SA_CRYPT_IV_SRAM_OFFSET + (offset)) | \
 172                     ((CESA_SA_CRYPT_IV_SRAM_OFFSET + (offset)) << 16))
 173 
 174 #define CESA_SA_DESC_CRYPT_KEY(offset)                                  \
 175         cpu_to_le32(CESA_SA_CRYPT_KEY_SRAM_OFFSET + (offset))
 176 
 177 #define CESA_SA_DESC_MAC_DATA(offset)                                   \
 178         cpu_to_le32(CESA_SA_DATA_SRAM_OFFSET + (offset))
 179 #define CESA_SA_DESC_MAC_DATA_MSK               cpu_to_le32(GENMASK(15, 0))
 180 
 181 #define CESA_SA_DESC_MAC_TOTAL_LEN(total_len)   cpu_to_le32((total_len) << 16)
 182 #define CESA_SA_DESC_MAC_TOTAL_LEN_MSK          cpu_to_le32(GENMASK(31, 16))
 183 
 184 #define CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX      0xffff
 185 
 186 #define CESA_SA_DESC_MAC_DIGEST(offset)                                 \
 187         cpu_to_le32(CESA_SA_MAC_DIG_SRAM_OFFSET + (offset))
 188 #define CESA_SA_DESC_MAC_DIGEST_MSK             cpu_to_le32(GENMASK(15, 0))
 189 
 190 #define CESA_SA_DESC_MAC_FRAG_LEN(frag_len)     cpu_to_le32((frag_len) << 16)
 191 #define CESA_SA_DESC_MAC_FRAG_LEN_MSK           cpu_to_le32(GENMASK(31, 16))
 192 
 193 #define CESA_SA_DESC_MAC_IV(offset)                                     \
 194         cpu_to_le32((CESA_SA_MAC_IIV_SRAM_OFFSET + (offset)) |          \
 195                     ((CESA_SA_MAC_OIV_SRAM_OFFSET + (offset)) << 16))
 196 
 197 #define CESA_SA_SRAM_SIZE                       2048
 198 #define CESA_SA_SRAM_PAYLOAD_SIZE               (cesa_dev->sram_size - \
 199                                                  CESA_SA_DATA_SRAM_OFFSET)
 200 
 201 #define CESA_SA_DEFAULT_SRAM_SIZE               2048
 202 #define CESA_SA_MIN_SRAM_SIZE                   1024
 203 
 204 #define CESA_SA_SRAM_MSK                        (2048 - 1)
 205 
 206 #define CESA_MAX_HASH_BLOCK_SIZE                64
 207 #define CESA_HASH_BLOCK_SIZE_MSK                (CESA_MAX_HASH_BLOCK_SIZE - 1)
 208 
 209 /**
 210  * struct mv_cesa_sec_accel_desc - security accelerator descriptor
 211  * @config:     engine config
 212  * @enc_p:      input and output data pointers for a cipher operation
 213  * @enc_len:    cipher operation length
 214  * @enc_key_p:  cipher key pointer
 215  * @enc_iv:     cipher IV pointers
 216  * @mac_src_p:  input pointer and total hash length
 217  * @mac_digest: digest pointer and hash operation length
 218  * @mac_iv:     hmac IV pointers
 219  *
 220  * Structure passed to the CESA engine to describe the crypto operation
 221  * to be executed.
 222  */
 223 struct mv_cesa_sec_accel_desc {
 224         __le32 config;
 225         __le32 enc_p;
 226         __le32 enc_len;
 227         __le32 enc_key_p;
 228         __le32 enc_iv;
 229         __le32 mac_src_p;
 230         __le32 mac_digest;
 231         __le32 mac_iv;
 232 };
 233 
 234 /**
 235  * struct mv_cesa_blkcipher_op_ctx - cipher operation context
 236  * @key:        cipher key
 237  * @iv:         cipher IV
 238  *
 239  * Context associated to a cipher operation.
 240  */
 241 struct mv_cesa_blkcipher_op_ctx {
 242         u32 key[8];
 243         u32 iv[4];
 244 };
 245 
 246 /**
 247  * struct mv_cesa_hash_op_ctx - hash or hmac operation context
 248  * @key:        cipher key
 249  * @iv:         cipher IV
 250  *
 251  * Context associated to an hash or hmac operation.
 252  */
 253 struct mv_cesa_hash_op_ctx {
 254         u32 iv[16];
 255         u32 hash[8];
 256 };
 257 
 258 /**
 259  * struct mv_cesa_op_ctx - crypto operation context
 260  * @desc:       CESA descriptor
 261  * @ctx:        context associated to the crypto operation
 262  *
 263  * Context associated to a crypto operation.
 264  */
 265 struct mv_cesa_op_ctx {
 266         struct mv_cesa_sec_accel_desc desc;
 267         union {
 268                 struct mv_cesa_blkcipher_op_ctx blkcipher;
 269                 struct mv_cesa_hash_op_ctx hash;
 270         } ctx;
 271 };
 272 
 273 /* TDMA descriptor flags */
 274 #define CESA_TDMA_DST_IN_SRAM                   BIT(31)
 275 #define CESA_TDMA_SRC_IN_SRAM                   BIT(30)
 276 #define CESA_TDMA_END_OF_REQ                    BIT(29)
 277 #define CESA_TDMA_BREAK_CHAIN                   BIT(28)
 278 #define CESA_TDMA_SET_STATE                     BIT(27)
 279 #define CESA_TDMA_TYPE_MSK                      GENMASK(26, 0)
 280 #define CESA_TDMA_DUMMY                         0
 281 #define CESA_TDMA_DATA                          1
 282 #define CESA_TDMA_OP                            2
 283 #define CESA_TDMA_RESULT                        3
 284 
 285 /**
 286  * struct mv_cesa_tdma_desc - TDMA descriptor
 287  * @byte_cnt:   number of bytes to transfer
 288  * @src:        DMA address of the source
 289  * @dst:        DMA address of the destination
 290  * @next_dma:   DMA address of the next TDMA descriptor
 291  * @cur_dma:    DMA address of this TDMA descriptor
 292  * @next:       pointer to the next TDMA descriptor
 293  * @op:         CESA operation attached to this TDMA descriptor
 294  * @data:       raw data attached to this TDMA descriptor
 295  * @flags:      flags describing the TDMA transfer. See the
 296  *              "TDMA descriptor flags" section above
 297  *
 298  * TDMA descriptor used to create a transfer chain describing a crypto
 299  * operation.
 300  */
 301 struct mv_cesa_tdma_desc {
 302         __le32 byte_cnt;
 303         __le32 src;
 304         __le32 dst;
 305         __le32 next_dma;
 306 
 307         /* Software state */
 308         dma_addr_t cur_dma;
 309         struct mv_cesa_tdma_desc *next;
 310         union {
 311                 struct mv_cesa_op_ctx *op;
 312                 void *data;
 313         };
 314         u32 flags;
 315 };
 316 
 317 /**
 318  * struct mv_cesa_sg_dma_iter - scatter-gather iterator
 319  * @dir:        transfer direction
 320  * @sg:         scatter list
 321  * @offset:     current position in the scatter list
 322  * @op_offset:  current position in the crypto operation
 323  *
 324  * Iterator used to iterate over a scatterlist while creating a TDMA chain for
 325  * a crypto operation.
 326  */
 327 struct mv_cesa_sg_dma_iter {
 328         enum dma_data_direction dir;
 329         struct scatterlist *sg;
 330         unsigned int offset;
 331         unsigned int op_offset;
 332 };
 333 
 334 /**
 335  * struct mv_cesa_dma_iter - crypto operation iterator
 336  * @len:        the crypto operation length
 337  * @offset:     current position in the crypto operation
 338  * @op_len:     sub-operation length (the crypto engine can only act on 2kb
 339  *              chunks)
 340  *
 341  * Iterator used to create a TDMA chain for a given crypto operation.
 342  */
 343 struct mv_cesa_dma_iter {
 344         unsigned int len;
 345         unsigned int offset;
 346         unsigned int op_len;
 347 };
 348 
 349 /**
 350  * struct mv_cesa_tdma_chain - TDMA chain
 351  * @first:      first entry in the TDMA chain
 352  * @last:       last entry in the TDMA chain
 353  *
 354  * Stores a TDMA chain for a specific crypto operation.
 355  */
 356 struct mv_cesa_tdma_chain {
 357         struct mv_cesa_tdma_desc *first;
 358         struct mv_cesa_tdma_desc *last;
 359 };
 360 
 361 struct mv_cesa_engine;
 362 
 363 /**
 364  * struct mv_cesa_caps - CESA device capabilities
 365  * @engines:            number of engines
 366  * @has_tdma:           whether this device has a TDMA block
 367  * @cipher_algs:        supported cipher algorithms
 368  * @ncipher_algs:       number of supported cipher algorithms
 369  * @ahash_algs:         supported hash algorithms
 370  * @nahash_algs:        number of supported hash algorithms
 371  *
 372  * Structure used to describe CESA device capabilities.
 373  */
 374 struct mv_cesa_caps {
 375         int nengines;
 376         bool has_tdma;
 377         struct skcipher_alg **cipher_algs;
 378         int ncipher_algs;
 379         struct ahash_alg **ahash_algs;
 380         int nahash_algs;
 381 };
 382 
 383 /**
 384  * struct mv_cesa_dev_dma - DMA pools
 385  * @tdma_desc_pool:     TDMA desc pool
 386  * @op_pool:            crypto operation pool
 387  * @cache_pool:         data cache pool (used by hash implementation when the
 388  *                      hash request is smaller than the hash block size)
 389  * @padding_pool:       padding pool (used by hash implementation when hardware
 390  *                      padding cannot be used)
 391  *
 392  * Structure containing the different DMA pools used by this driver.
 393  */
 394 struct mv_cesa_dev_dma {
 395         struct dma_pool *tdma_desc_pool;
 396         struct dma_pool *op_pool;
 397         struct dma_pool *cache_pool;
 398         struct dma_pool *padding_pool;
 399 };
 400 
 401 /**
 402  * struct mv_cesa_dev - CESA device
 403  * @caps:       device capabilities
 404  * @regs:       device registers
 405  * @sram_size:  usable SRAM size
 406  * @lock:       device lock
 407  * @engines:    array of engines
 408  * @dma:        dma pools
 409  *
 410  * Structure storing CESA device information.
 411  */
 412 struct mv_cesa_dev {
 413         const struct mv_cesa_caps *caps;
 414         void __iomem *regs;
 415         struct device *dev;
 416         unsigned int sram_size;
 417         spinlock_t lock;
 418         struct mv_cesa_engine *engines;
 419         struct mv_cesa_dev_dma *dma;
 420 };
 421 
 422 /**
 423  * struct mv_cesa_engine - CESA engine
 424  * @id:                 engine id
 425  * @regs:               engine registers
 426  * @sram:               SRAM memory region
 427  * @sram_dma:           DMA address of the SRAM memory region
 428  * @lock:               engine lock
 429  * @req:                current crypto request
 430  * @clk:                engine clk
 431  * @zclk:               engine zclk
 432  * @max_req_len:        maximum chunk length (useful to create the TDMA chain)
 433  * @int_mask:           interrupt mask cache
 434  * @pool:               memory pool pointing to the memory region reserved in
 435  *                      SRAM
 436  * @queue:              fifo of the pending crypto requests
 437  * @load:               engine load counter, useful for load balancing
 438  * @chain:              list of the current tdma descriptors being processed
 439  *                      by this engine.
 440  * @complete_queue:     fifo of the processed requests by the engine
 441  *
 442  * Structure storing CESA engine information.
 443  */
 444 struct mv_cesa_engine {
 445         int id;
 446         void __iomem *regs;
 447         void __iomem *sram;
 448         dma_addr_t sram_dma;
 449         spinlock_t lock;
 450         struct crypto_async_request *req;
 451         struct clk *clk;
 452         struct clk *zclk;
 453         size_t max_req_len;
 454         u32 int_mask;
 455         struct gen_pool *pool;
 456         struct crypto_queue queue;
 457         atomic_t load;
 458         struct mv_cesa_tdma_chain chain;
 459         struct list_head complete_queue;
 460 };
 461 
 462 /**
 463  * struct mv_cesa_req_ops - CESA request operations
 464  * @process:    process a request chunk result (should return 0 if the
 465  *              operation, -EINPROGRESS if it needs more steps or an error
 466  *              code)
 467  * @step:       launch the crypto operation on the next chunk
 468  * @cleanup:    cleanup the crypto request (release associated data)
 469  * @complete:   complete the request, i.e copy result or context from sram when
 470  *              needed.
 471  */
 472 struct mv_cesa_req_ops {
 473         int (*process)(struct crypto_async_request *req, u32 status);
 474         void (*step)(struct crypto_async_request *req);
 475         void (*cleanup)(struct crypto_async_request *req);
 476         void (*complete)(struct crypto_async_request *req);
 477 };
 478 
 479 /**
 480  * struct mv_cesa_ctx - CESA operation context
 481  * @ops:        crypto operations
 482  *
 483  * Base context structure inherited by operation specific ones.
 484  */
 485 struct mv_cesa_ctx {
 486         const struct mv_cesa_req_ops *ops;
 487 };
 488 
 489 /**
 490  * struct mv_cesa_hash_ctx - CESA hash operation context
 491  * @base:       base context structure
 492  *
 493  * Hash context structure.
 494  */
 495 struct mv_cesa_hash_ctx {
 496         struct mv_cesa_ctx base;
 497 };
 498 
 499 /**
 500  * struct mv_cesa_hash_ctx - CESA hmac operation context
 501  * @base:       base context structure
 502  * @iv:         initialization vectors
 503  *
 504  * HMAC context structure.
 505  */
 506 struct mv_cesa_hmac_ctx {
 507         struct mv_cesa_ctx base;
 508         u32 iv[16];
 509 };
 510 
 511 /**
 512  * enum mv_cesa_req_type - request type definitions
 513  * @CESA_STD_REQ:       standard request
 514  * @CESA_DMA_REQ:       DMA request
 515  */
 516 enum mv_cesa_req_type {
 517         CESA_STD_REQ,
 518         CESA_DMA_REQ,
 519 };
 520 
 521 /**
 522  * struct mv_cesa_req - CESA request
 523  * @engine:     engine associated with this request
 524  * @chain:      list of tdma descriptors associated  with this request
 525  */
 526 struct mv_cesa_req {
 527         struct mv_cesa_engine *engine;
 528         struct mv_cesa_tdma_chain chain;
 529 };
 530 
 531 /**
 532  * struct mv_cesa_sg_std_iter - CESA scatter-gather iterator for standard
 533  *                              requests
 534  * @iter:       sg mapping iterator
 535  * @offset:     current offset in the SG entry mapped in memory
 536  */
 537 struct mv_cesa_sg_std_iter {
 538         struct sg_mapping_iter iter;
 539         unsigned int offset;
 540 };
 541 
 542 /**
 543  * struct mv_cesa_skcipher_std_req - cipher standard request
 544  * @op:         operation context
 545  * @offset:     current operation offset
 546  * @size:       size of the crypto operation
 547  */
 548 struct mv_cesa_skcipher_std_req {
 549         struct mv_cesa_op_ctx op;
 550         unsigned int offset;
 551         unsigned int size;
 552         bool skip_ctx;
 553 };
 554 
 555 /**
 556  * struct mv_cesa_skcipher_req - cipher request
 557  * @req:        type specific request information
 558  * @src_nents:  number of entries in the src sg list
 559  * @dst_nents:  number of entries in the dest sg list
 560  */
 561 struct mv_cesa_skcipher_req {
 562         struct mv_cesa_req base;
 563         struct mv_cesa_skcipher_std_req std;
 564         int src_nents;
 565         int dst_nents;
 566 };
 567 
 568 /**
 569  * struct mv_cesa_ahash_std_req - standard hash request
 570  * @offset:     current operation offset
 571  */
 572 struct mv_cesa_ahash_std_req {
 573         unsigned int offset;
 574 };
 575 
 576 /**
 577  * struct mv_cesa_ahash_dma_req - DMA hash request
 578  * @padding:            padding buffer
 579  * @padding_dma:        DMA address of the padding buffer
 580  * @cache_dma:          DMA address of the cache buffer
 581  */
 582 struct mv_cesa_ahash_dma_req {
 583         u8 *padding;
 584         dma_addr_t padding_dma;
 585         u8 *cache;
 586         dma_addr_t cache_dma;
 587 };
 588 
 589 /**
 590  * struct mv_cesa_ahash_req - hash request
 591  * @req:                type specific request information
 592  * @cache:              cache buffer
 593  * @cache_ptr:          write pointer in the cache buffer
 594  * @len:                hash total length
 595  * @src_nents:          number of entries in the scatterlist
 596  * @last_req:           define whether the current operation is the last one
 597  *                      or not
 598  * @state:              hash state
 599  */
 600 struct mv_cesa_ahash_req {
 601         struct mv_cesa_req base;
 602         union {
 603                 struct mv_cesa_ahash_dma_req dma;
 604                 struct mv_cesa_ahash_std_req std;
 605         } req;
 606         struct mv_cesa_op_ctx op_tmpl;
 607         u8 cache[CESA_MAX_HASH_BLOCK_SIZE];
 608         unsigned int cache_ptr;
 609         u64 len;
 610         int src_nents;
 611         bool last_req;
 612         bool algo_le;
 613         u32 state[8];
 614 };
 615 
 616 /* CESA functions */
 617 
 618 extern struct mv_cesa_dev *cesa_dev;
 619 
 620 
 621 static inline void
 622 mv_cesa_engine_enqueue_complete_request(struct mv_cesa_engine *engine,
 623                                         struct crypto_async_request *req)
 624 {
 625         list_add_tail(&req->list, &engine->complete_queue);
 626 }
 627 
 628 static inline struct crypto_async_request *
 629 mv_cesa_engine_dequeue_complete_request(struct mv_cesa_engine *engine)
 630 {
 631         struct crypto_async_request *req;
 632 
 633         req = list_first_entry_or_null(&engine->complete_queue,
 634                                        struct crypto_async_request,
 635                                        list);
 636         if (req)
 637                 list_del(&req->list);
 638 
 639         return req;
 640 }
 641 
 642 
 643 static inline enum mv_cesa_req_type
 644 mv_cesa_req_get_type(struct mv_cesa_req *req)
 645 {
 646         return req->chain.first ? CESA_DMA_REQ : CESA_STD_REQ;
 647 }
 648 
 649 static inline void mv_cesa_update_op_cfg(struct mv_cesa_op_ctx *op,
 650                                          u32 cfg, u32 mask)
 651 {
 652         op->desc.config &= cpu_to_le32(~mask);
 653         op->desc.config |= cpu_to_le32(cfg);
 654 }
 655 
 656 static inline u32 mv_cesa_get_op_cfg(const struct mv_cesa_op_ctx *op)
 657 {
 658         return le32_to_cpu(op->desc.config);
 659 }
 660 
 661 static inline void mv_cesa_set_op_cfg(struct mv_cesa_op_ctx *op, u32 cfg)
 662 {
 663         op->desc.config = cpu_to_le32(cfg);
 664 }
 665 
 666 static inline void mv_cesa_adjust_op(struct mv_cesa_engine *engine,
 667                                      struct mv_cesa_op_ctx *op)
 668 {
 669         u32 offset = engine->sram_dma & CESA_SA_SRAM_MSK;
 670 
 671         op->desc.enc_p = CESA_SA_DESC_CRYPT_DATA(offset);
 672         op->desc.enc_key_p = CESA_SA_DESC_CRYPT_KEY(offset);
 673         op->desc.enc_iv = CESA_SA_DESC_CRYPT_IV(offset);
 674         op->desc.mac_src_p &= ~CESA_SA_DESC_MAC_DATA_MSK;
 675         op->desc.mac_src_p |= CESA_SA_DESC_MAC_DATA(offset);
 676         op->desc.mac_digest &= ~CESA_SA_DESC_MAC_DIGEST_MSK;
 677         op->desc.mac_digest |= CESA_SA_DESC_MAC_DIGEST(offset);
 678         op->desc.mac_iv = CESA_SA_DESC_MAC_IV(offset);
 679 }
 680 
 681 static inline void mv_cesa_set_crypt_op_len(struct mv_cesa_op_ctx *op, int len)
 682 {
 683         op->desc.enc_len = cpu_to_le32(len);
 684 }
 685 
 686 static inline void mv_cesa_set_mac_op_total_len(struct mv_cesa_op_ctx *op,
 687                                                 int len)
 688 {
 689         op->desc.mac_src_p &= ~CESA_SA_DESC_MAC_TOTAL_LEN_MSK;
 690         op->desc.mac_src_p |= CESA_SA_DESC_MAC_TOTAL_LEN(len);
 691 }
 692 
 693 static inline void mv_cesa_set_mac_op_frag_len(struct mv_cesa_op_ctx *op,
 694                                                int len)
 695 {
 696         op->desc.mac_digest &= ~CESA_SA_DESC_MAC_FRAG_LEN_MSK;
 697         op->desc.mac_digest |= CESA_SA_DESC_MAC_FRAG_LEN(len);
 698 }
 699 
 700 static inline void mv_cesa_set_int_mask(struct mv_cesa_engine *engine,
 701                                         u32 int_mask)
 702 {
 703         if (int_mask == engine->int_mask)
 704                 return;
 705 
 706         writel_relaxed(int_mask, engine->regs + CESA_SA_INT_MSK);
 707         engine->int_mask = int_mask;
 708 }
 709 
 710 static inline u32 mv_cesa_get_int_mask(struct mv_cesa_engine *engine)
 711 {
 712         return engine->int_mask;
 713 }
 714 
 715 static inline bool mv_cesa_mac_op_is_first_frag(const struct mv_cesa_op_ctx *op)
 716 {
 717         return (mv_cesa_get_op_cfg(op) & CESA_SA_DESC_CFG_FRAG_MSK) ==
 718                 CESA_SA_DESC_CFG_FIRST_FRAG;
 719 }
 720 
 721 int mv_cesa_queue_req(struct crypto_async_request *req,
 722                       struct mv_cesa_req *creq);
 723 
 724 struct crypto_async_request *
 725 mv_cesa_dequeue_req_locked(struct mv_cesa_engine *engine,
 726                            struct crypto_async_request **backlog);
 727 
 728 static inline struct mv_cesa_engine *mv_cesa_select_engine(int weight)
 729 {
 730         int i;
 731         u32 min_load = U32_MAX;
 732         struct mv_cesa_engine *selected = NULL;
 733 
 734         for (i = 0; i < cesa_dev->caps->nengines; i++) {
 735                 struct mv_cesa_engine *engine = cesa_dev->engines + i;
 736                 u32 load = atomic_read(&engine->load);
 737                 if (load < min_load) {
 738                         min_load = load;
 739                         selected = engine;
 740                 }
 741         }
 742 
 743         atomic_add(weight, &selected->load);
 744 
 745         return selected;
 746 }
 747 
 748 /*
 749  * Helper function that indicates whether a crypto request needs to be
 750  * cleaned up or not after being enqueued using mv_cesa_queue_req().
 751  */
 752 static inline int mv_cesa_req_needs_cleanup(struct crypto_async_request *req,
 753                                             int ret)
 754 {
 755         /*
 756          * The queue still had some space, the request was queued
 757          * normally, so there's no need to clean it up.
 758          */
 759         if (ret == -EINPROGRESS)
 760                 return false;
 761 
 762         /*
 763          * The queue had not space left, but since the request is
 764          * flagged with CRYPTO_TFM_REQ_MAY_BACKLOG, it was added to
 765          * the backlog and will be processed later. There's no need to
 766          * clean it up.
 767          */
 768         if (ret == -EBUSY)
 769                 return false;
 770 
 771         /* Request wasn't queued, we need to clean it up */
 772         return true;
 773 }
 774 
 775 /* TDMA functions */
 776 
 777 static inline void mv_cesa_req_dma_iter_init(struct mv_cesa_dma_iter *iter,
 778                                              unsigned int len)
 779 {
 780         iter->len = len;
 781         iter->op_len = min(len, CESA_SA_SRAM_PAYLOAD_SIZE);
 782         iter->offset = 0;
 783 }
 784 
 785 static inline void mv_cesa_sg_dma_iter_init(struct mv_cesa_sg_dma_iter *iter,
 786                                             struct scatterlist *sg,
 787                                             enum dma_data_direction dir)
 788 {
 789         iter->op_offset = 0;
 790         iter->offset = 0;
 791         iter->sg = sg;
 792         iter->dir = dir;
 793 }
 794 
 795 static inline unsigned int
 796 mv_cesa_req_dma_iter_transfer_len(struct mv_cesa_dma_iter *iter,
 797                                   struct mv_cesa_sg_dma_iter *sgiter)
 798 {
 799         return min(iter->op_len - sgiter->op_offset,
 800                    sg_dma_len(sgiter->sg) - sgiter->offset);
 801 }
 802 
 803 bool mv_cesa_req_dma_iter_next_transfer(struct mv_cesa_dma_iter *chain,
 804                                         struct mv_cesa_sg_dma_iter *sgiter,
 805                                         unsigned int len);
 806 
 807 static inline bool mv_cesa_req_dma_iter_next_op(struct mv_cesa_dma_iter *iter)
 808 {
 809         iter->offset += iter->op_len;
 810         iter->op_len = min(iter->len - iter->offset,
 811                            CESA_SA_SRAM_PAYLOAD_SIZE);
 812 
 813         return iter->op_len;
 814 }
 815 
 816 void mv_cesa_dma_step(struct mv_cesa_req *dreq);
 817 
 818 static inline int mv_cesa_dma_process(struct mv_cesa_req *dreq,
 819                                       u32 status)
 820 {
 821         if (!(status & CESA_SA_INT_ACC0_IDMA_DONE))
 822                 return -EINPROGRESS;
 823 
 824         if (status & CESA_SA_INT_IDMA_OWN_ERR)
 825                 return -EINVAL;
 826 
 827         return 0;
 828 }
 829 
 830 void mv_cesa_dma_prepare(struct mv_cesa_req *dreq,
 831                          struct mv_cesa_engine *engine);
 832 void mv_cesa_dma_cleanup(struct mv_cesa_req *dreq);
 833 void mv_cesa_tdma_chain(struct mv_cesa_engine *engine,
 834                         struct mv_cesa_req *dreq);
 835 int mv_cesa_tdma_process(struct mv_cesa_engine *engine, u32 status);
 836 
 837 
 838 static inline void
 839 mv_cesa_tdma_desc_iter_init(struct mv_cesa_tdma_chain *chain)
 840 {
 841         memset(chain, 0, sizeof(*chain));
 842 }
 843 
 844 int mv_cesa_dma_add_result_op(struct mv_cesa_tdma_chain *chain, dma_addr_t src,
 845                           u32 size, u32 flags, gfp_t gfp_flags);
 846 
 847 struct mv_cesa_op_ctx *mv_cesa_dma_add_op(struct mv_cesa_tdma_chain *chain,
 848                                         const struct mv_cesa_op_ctx *op_templ,
 849                                         bool skip_ctx,
 850                                         gfp_t flags);
 851 
 852 int mv_cesa_dma_add_data_transfer(struct mv_cesa_tdma_chain *chain,
 853                                   dma_addr_t dst, dma_addr_t src, u32 size,
 854                                   u32 flags, gfp_t gfp_flags);
 855 
 856 int mv_cesa_dma_add_dummy_launch(struct mv_cesa_tdma_chain *chain, gfp_t flags);
 857 int mv_cesa_dma_add_dummy_end(struct mv_cesa_tdma_chain *chain, gfp_t flags);
 858 
 859 int mv_cesa_dma_add_op_transfers(struct mv_cesa_tdma_chain *chain,
 860                                  struct mv_cesa_dma_iter *dma_iter,
 861                                  struct mv_cesa_sg_dma_iter *sgiter,
 862                                  gfp_t gfp_flags);
 863 
 864 /* Algorithm definitions */
 865 
 866 extern struct ahash_alg mv_md5_alg;
 867 extern struct ahash_alg mv_sha1_alg;
 868 extern struct ahash_alg mv_sha256_alg;
 869 extern struct ahash_alg mv_ahmac_md5_alg;
 870 extern struct ahash_alg mv_ahmac_sha1_alg;
 871 extern struct ahash_alg mv_ahmac_sha256_alg;
 872 
 873 extern struct skcipher_alg mv_cesa_ecb_des_alg;
 874 extern struct skcipher_alg mv_cesa_cbc_des_alg;
 875 extern struct skcipher_alg mv_cesa_ecb_des3_ede_alg;
 876 extern struct skcipher_alg mv_cesa_cbc_des3_ede_alg;
 877 extern struct skcipher_alg mv_cesa_ecb_aes_alg;
 878 extern struct skcipher_alg mv_cesa_cbc_aes_alg;
 879 
 880 #endif /* __MARVELL_CESA_H__ */
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