drivers/crypto/cavium/zip/zip

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This source file includes following definitions.
ZIP_COREX_BIST_STATUS
ZIP_DBG_COREX_INST
ZIP_DBG_COREX_STA
ZIP_DBG_QUEX_STA
ZIP_MSIX_PBAX
ZIP_MSIX_VECX_ADDR
ZIP_MSIX_VECX_CTL
ZIP_QUEX_DONE
ZIP_QUEX_DONE_ACK
ZIP_QUEX_DONE_ENA_W1C
ZIP_QUEX_DONE_ENA_W1S
ZIP_QUEX_DONE_WAIT
ZIP_QUEX_DOORBELL
ZIP_QUEX_ERR_ENA_W1C
ZIP_QUEX_ERR_ENA_W1S
ZIP_QUEX_ERR_INT
ZIP_QUEX_ERR_INT_W1S
ZIP_QUEX_GCFG
ZIP_QUEX_MAP
ZIP_QUEX_SBUF_ADDR
ZIP_QUEX_SBUF_CTL
   1 /***********************license start************************************
   2  * Copyright (c) 2003-2017 Cavium, Inc.
   3  * All rights reserved.
   4  *
   5  * License: one of 'Cavium License' or 'GNU General Public License Version 2'
   6  *
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   9  * published by the Free Software Foundation. When using or redistributing
  10  * this file, you may do so under either license.
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  13  * or without modification, are permitted provided that the following
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  43  * WITH YOU.
  44  ***********************license end**************************************/
  45 
  46 #ifndef __ZIP_REGS_H__
  47 #define __ZIP_REGS_H__
  48 
  49 /*
  50  * Configuration and status register (CSR) address and type definitions for
  51  * Cavium ZIP.
  52  */
  53 
  54 #include <linux/kern_levels.h>
  55 
  56 /* ZIP invocation result completion status codes */
  57 #define ZIP_CMD_NOTDONE        0x0
  58 
  59 /* Successful completion. */
  60 #define ZIP_CMD_SUCCESS        0x1
  61 
  62 /* Output truncated */
  63 #define ZIP_CMD_DTRUNC         0x2
  64 
  65 /* Dynamic Stop */
  66 #define ZIP_CMD_DYNAMIC_STOP   0x3
  67 
  68 /* Uncompress ran out of input data when IWORD0[EF] was set */
  69 #define ZIP_CMD_ITRUNC         0x4
  70 
  71 /* Uncompress found the reserved block type 3 */
  72 #define ZIP_CMD_RBLOCK         0x5
  73 
  74 /*
  75  * Uncompress found LEN != ZIP_CMD_NLEN in an uncompressed block in the input.
  76  */
  77 #define ZIP_CMD_NLEN           0x6
  78 
  79 /* Uncompress found a bad code in the main Huffman codes. */
  80 #define ZIP_CMD_BADCODE        0x7
  81 
  82 /* Uncompress found a bad code in the 19 Huffman codes encoding lengths. */
  83 #define ZIP_CMD_BADCODE2       0x8
  84 
  85 /* Compress found a zero-length input. */
  86 #define ZIP_CMD_ZERO_LEN       0x9
  87 
  88 /* The compress or decompress encountered an internal parity error. */
  89 #define ZIP_CMD_PARITY         0xA
  90 
  91 /*
  92  * Uncompress found a string identifier that precedes the uncompressed data and
  93  * decompression history.
  94  */
  95 #define ZIP_CMD_FATAL          0xB
  96 
  97 /**
  98  * enum zip_int_vec_e - ZIP MSI-X Vector Enumeration, enumerates the MSI-X
  99  * interrupt vectors.
 100  */
 101 enum zip_int_vec_e {
 102         ZIP_INT_VEC_E_ECCE = 0x10,
 103         ZIP_INT_VEC_E_FIFE = 0x11,
 104         ZIP_INT_VEC_E_QUE0_DONE = 0x0,
 105         ZIP_INT_VEC_E_QUE0_ERR = 0x8,
 106         ZIP_INT_VEC_E_QUE1_DONE = 0x1,
 107         ZIP_INT_VEC_E_QUE1_ERR = 0x9,
 108         ZIP_INT_VEC_E_QUE2_DONE = 0x2,
 109         ZIP_INT_VEC_E_QUE2_ERR = 0xa,
 110         ZIP_INT_VEC_E_QUE3_DONE = 0x3,
 111         ZIP_INT_VEC_E_QUE3_ERR = 0xb,
 112         ZIP_INT_VEC_E_QUE4_DONE = 0x4,
 113         ZIP_INT_VEC_E_QUE4_ERR = 0xc,
 114         ZIP_INT_VEC_E_QUE5_DONE = 0x5,
 115         ZIP_INT_VEC_E_QUE5_ERR = 0xd,
 116         ZIP_INT_VEC_E_QUE6_DONE = 0x6,
 117         ZIP_INT_VEC_E_QUE6_ERR = 0xe,
 118         ZIP_INT_VEC_E_QUE7_DONE = 0x7,
 119         ZIP_INT_VEC_E_QUE7_ERR = 0xf,
 120         ZIP_INT_VEC_E_ENUM_LAST = 0x12,
 121 };
 122 
 123 /**
 124  * union zip_zptr_addr_s - ZIP Generic Pointer Structure for ADDR.
 125  *
 126  * It is the generic format of pointers in ZIP_INST_S.
 127  */
 128 union zip_zptr_addr_s {
 129         u64 u_reg64;
 130         struct {
 131 #if defined(__BIG_ENDIAN_BITFIELD)
 132                 u64 reserved_49_63              : 15;
 133                 u64 addr                        : 49;
 134 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 135                 u64 addr                        : 49;
 136                 u64 reserved_49_63              : 15;
 137 #endif
 138         } s;
 139 
 140 };
 141 
 142 /**
 143  * union zip_zptr_ctl_s - ZIP Generic Pointer Structure for CTL.
 144  *
 145  * It is the generic format of pointers in ZIP_INST_S.
 146  */
 147 union zip_zptr_ctl_s {
 148         u64 u_reg64;
 149         struct {
 150 #if defined(__BIG_ENDIAN_BITFIELD)
 151                 u64 reserved_112_127            : 16;
 152                 u64 length                      : 16;
 153                 u64 reserved_67_95              : 29;
 154                 u64 fw                          : 1;
 155                 u64 nc                          : 1;
 156                 u64 data_be                     : 1;
 157 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 158                 u64 data_be                     : 1;
 159                 u64 nc                          : 1;
 160                 u64 fw                          : 1;
 161                 u64 reserved_67_95              : 29;
 162                 u64 length                      : 16;
 163                 u64 reserved_112_127            : 16;
 164 #endif
 165         } s;
 166 };
 167 
 168 /**
 169  * union zip_inst_s - ZIP Instruction Structure.
 170  * Each ZIP instruction has 16 words (they are called IWORD0 to IWORD15 within
 171  * the structure).
 172  */
 173 union zip_inst_s {
 174         u64 u_reg64[16];
 175         struct {
 176 #if defined(__BIG_ENDIAN_BITFIELD)
 177                 u64 doneint                     : 1;
 178                 u64 reserved_56_62              : 7;
 179                 u64 totaloutputlength           : 24;
 180                 u64 reserved_27_31              : 5;
 181                 u64 exn                         : 3;
 182                 u64 reserved_23_23              : 1;
 183                 u64 exbits                      : 7;
 184                 u64 reserved_12_15              : 4;
 185                 u64 sf                          : 1;
 186                 u64 ss                          : 2;
 187                 u64 cc                          : 2;
 188                 u64 ef                          : 1;
 189                 u64 bf                          : 1;
 190                 u64 ce                          : 1;
 191                 u64 reserved_3_3                : 1;
 192                 u64 ds                          : 1;
 193                 u64 dg                          : 1;
 194                 u64 hg                          : 1;
 195 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 196                 u64 hg                          : 1;
 197                 u64 dg                          : 1;
 198                 u64 ds                          : 1;
 199                 u64 reserved_3_3                : 1;
 200                 u64 ce                          : 1;
 201                 u64 bf                          : 1;
 202                 u64 ef                          : 1;
 203                 u64 cc                          : 2;
 204                 u64 ss                          : 2;
 205                 u64 sf                          : 1;
 206                 u64 reserved_12_15              : 4;
 207                 u64 exbits                      : 7;
 208                 u64 reserved_23_23              : 1;
 209                 u64 exn                         : 3;
 210                 u64 reserved_27_31              : 5;
 211                 u64 totaloutputlength           : 24;
 212                 u64 reserved_56_62              : 7;
 213                 u64 doneint                     : 1;
 214 #endif
 215 #if defined(__BIG_ENDIAN_BITFIELD)
 216                 u64 historylength               : 16;
 217                 u64 reserved_96_111             : 16;
 218                 u64 adlercrc32                  : 32;
 219 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 220                 u64 adlercrc32                  : 32;
 221                 u64 reserved_96_111             : 16;
 222                 u64 historylength               : 16;
 223 #endif
 224                 union zip_zptr_addr_s ctx_ptr_addr;
 225                 union zip_zptr_ctl_s ctx_ptr_ctl;
 226                 union zip_zptr_addr_s his_ptr_addr;
 227                 union zip_zptr_ctl_s his_ptr_ctl;
 228                 union zip_zptr_addr_s inp_ptr_addr;
 229                 union zip_zptr_ctl_s inp_ptr_ctl;
 230                 union zip_zptr_addr_s out_ptr_addr;
 231                 union zip_zptr_ctl_s out_ptr_ctl;
 232                 union zip_zptr_addr_s res_ptr_addr;
 233                 union zip_zptr_ctl_s res_ptr_ctl;
 234 #if defined(__BIG_ENDIAN_BITFIELD)
 235                 u64 reserved_817_831            : 15;
 236                 u64 wq_ptr                      : 49;
 237 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 238                 u64 wq_ptr                      : 49;
 239                 u64 reserved_817_831            : 15;
 240 #endif
 241 #if defined(__BIG_ENDIAN_BITFIELD)
 242                 u64 reserved_882_895            : 14;
 243                 u64 tt                          : 2;
 244                 u64 reserved_874_879            : 6;
 245                 u64 grp                         : 10;
 246                 u64 tag                         : 32;
 247 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 248                 u64 tag                         : 32;
 249                 u64 grp                         : 10;
 250                 u64 reserved_874_879            : 6;
 251                 u64 tt                          : 2;
 252                 u64 reserved_882_895            : 14;
 253 #endif
 254 #if defined(__BIG_ENDIAN_BITFIELD)
 255                 u64 reserved_896_959            : 64;
 256 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 257                 u64 reserved_896_959            : 64;
 258 #endif
 259 #if defined(__BIG_ENDIAN_BITFIELD)
 260                 u64 reserved_960_1023           : 64;
 261 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 262                 u64 reserved_960_1023           : 64;
 263 #endif
 264         } s;
 265 };
 266 
 267 /**
 268  * union zip_nptr_s - ZIP Instruction Next-Chunk-Buffer Pointer (NPTR)
 269  * Structure
 270  *
 271  * ZIP_NPTR structure is used to chain all the zip instruction buffers
 272  * together. ZIP instruction buffers are managed (allocated and released) by
 273  * the software.
 274  */
 275 union zip_nptr_s {
 276         u64 u_reg64;
 277         struct {
 278 #if defined(__BIG_ENDIAN_BITFIELD)
 279                 u64 reserved_49_63              : 15;
 280                 u64 addr                        : 49;
 281 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 282                 u64 addr                        : 49;
 283                 u64 reserved_49_63              : 15;
 284 #endif
 285         } s;
 286 };
 287 
 288 /**
 289  * union zip_zptr_s - ZIP Generic Pointer Structure.
 290  *
 291  * It is the generic format of pointers in ZIP_INST_S.
 292  */
 293 union zip_zptr_s {
 294         u64 u_reg64[2];
 295         struct {
 296 #if defined(__BIG_ENDIAN_BITFIELD)
 297                 u64 reserved_49_63              : 15;
 298                 u64 addr                        : 49;
 299 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 300                 u64 addr                        : 49;
 301                 u64 reserved_49_63              : 15;
 302 #endif
 303 #if defined(__BIG_ENDIAN_BITFIELD)
 304                 u64 reserved_112_127            : 16;
 305                 u64 length                      : 16;
 306                 u64 reserved_67_95              : 29;
 307                 u64 fw                          : 1;
 308                 u64 nc                          : 1;
 309                 u64 data_be                     : 1;
 310 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 311                 u64 data_be                     : 1;
 312                 u64 nc                          : 1;
 313                 u64 fw                          : 1;
 314                 u64 reserved_67_95              : 29;
 315                 u64 length                      : 16;
 316                 u64 reserved_112_127            : 16;
 317 #endif
 318         } s;
 319 };
 320 
 321 /**
 322  * union zip_zres_s - ZIP Result Structure
 323  *
 324  * The ZIP coprocessor writes the result structure after it completes the
 325  * invocation. The result structure is exactly 24 bytes, and each invocation of
 326  * the ZIP coprocessor produces exactly one result structure.
 327  */
 328 union zip_zres_s {
 329         u64 u_reg64[3];
 330         struct {
 331 #if defined(__BIG_ENDIAN_BITFIELD)
 332                 u64 crc32                       : 32;
 333                 u64 adler32                     : 32;
 334 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 335                 u64 adler32                     : 32;
 336                 u64 crc32                       : 32;
 337 #endif
 338 #if defined(__BIG_ENDIAN_BITFIELD)
 339                 u64 totalbyteswritten           : 32;
 340                 u64 totalbytesread              : 32;
 341 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 342                 u64 totalbytesread              : 32;
 343                 u64 totalbyteswritten           : 32;
 344 #endif
 345 #if defined(__BIG_ENDIAN_BITFIELD)
 346                 u64 totalbitsprocessed          : 32;
 347                 u64 doneint                     : 1;
 348                 u64 reserved_155_158            : 4;
 349                 u64 exn                         : 3;
 350                 u64 reserved_151_151            : 1;
 351                 u64 exbits                      : 7;
 352                 u64 reserved_137_143            : 7;
 353                 u64 ef                          : 1;
 354 
 355                 volatile u64 compcode           : 8;
 356 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 357 
 358                 volatile u64 compcode           : 8;
 359                 u64 ef                          : 1;
 360                 u64 reserved_137_143            : 7;
 361                 u64 exbits                      : 7;
 362                 u64 reserved_151_151            : 1;
 363                 u64 exn                         : 3;
 364                 u64 reserved_155_158            : 4;
 365                 u64 doneint                     : 1;
 366                 u64 totalbitsprocessed          : 32;
 367 #endif
 368         } s;
 369 };
 370 
 371 /**
 372  * union zip_cmd_ctl - Structure representing the register that controls
 373  * clock and reset.
 374  */
 375 union zip_cmd_ctl {
 376         u64 u_reg64;
 377         struct zip_cmd_ctl_s {
 378 #if defined(__BIG_ENDIAN_BITFIELD)
 379                 u64 reserved_2_63               : 62;
 380                 u64 forceclk                    : 1;
 381                 u64 reset                       : 1;
 382 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 383                 u64 reset                       : 1;
 384                 u64 forceclk                    : 1;
 385                 u64 reserved_2_63               : 62;
 386 #endif
 387         } s;
 388 };
 389 
 390 #define ZIP_CMD_CTL 0x0ull
 391 
 392 /**
 393  * union zip_constants - Data structure representing the register that contains
 394  * all of the current implementation-related parameters of the zip core in this
 395  * chip.
 396  */
 397 union zip_constants {
 398         u64 u_reg64;
 399         struct zip_constants_s {
 400 #if defined(__BIG_ENDIAN_BITFIELD)
 401                 u64 nexec                       : 8;
 402                 u64 reserved_49_55              : 7;
 403                 u64 syncflush_capable           : 1;
 404                 u64 depth                       : 16;
 405                 u64 onfsize                     : 12;
 406                 u64 ctxsize                     : 12;
 407                 u64 reserved_1_7                : 7;
 408                 u64 disabled                    : 1;
 409 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 410                 u64 disabled                    : 1;
 411                 u64 reserved_1_7                : 7;
 412                 u64 ctxsize                     : 12;
 413                 u64 onfsize                     : 12;
 414                 u64 depth                       : 16;
 415                 u64 syncflush_capable           : 1;
 416                 u64 reserved_49_55              : 7;
 417                 u64 nexec                       : 8;
 418 #endif
 419         } s;
 420 };
 421 
 422 #define ZIP_CONSTANTS 0x00A0ull
 423 
 424 /**
 425  * union zip_corex_bist_status - Represents registers which have the BIST
 426  * status of memories in zip cores.
 427  *
 428  * Each bit is the BIST result of an individual memory
 429  * (per bit, 0 = pass and 1 = fail).
 430  */
 431 union zip_corex_bist_status {
 432         u64 u_reg64;
 433         struct zip_corex_bist_status_s {
 434 #if defined(__BIG_ENDIAN_BITFIELD)
 435                 u64 reserved_53_63              : 11;
 436                 u64 bstatus                     : 53;
 437 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 438                 u64 bstatus                     : 53;
 439                 u64 reserved_53_63              : 11;
 440 #endif
 441         } s;
 442 };
 443 
 444 static inline u64 ZIP_COREX_BIST_STATUS(u64 param1)
 445 {
 446         if (param1 <= 1)
 447                 return 0x0520ull + (param1 & 1) * 0x8ull;
 448         pr_err("ZIP_COREX_BIST_STATUS: %llu\n", param1);
 449         return 0;
 450 }
 451 
 452 /**
 453  * union zip_ctl_bist_status - Represents register that has the BIST status of
 454  * memories in ZIP_CTL (instruction buffer, G/S pointer FIFO, input data
 455  * buffer, output data buffers).
 456  *
 457  * Each bit is the BIST result of an individual memory
 458  * (per bit, 0 = pass and 1 = fail).
 459  */
 460 union zip_ctl_bist_status {
 461         u64 u_reg64;
 462         struct zip_ctl_bist_status_s {
 463 #if defined(__BIG_ENDIAN_BITFIELD)
 464                 u64 reserved_9_63               : 55;
 465                 u64 bstatus                     : 9;
 466 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 467                 u64 bstatus                     : 9;
 468                 u64 reserved_9_63               : 55;
 469 #endif
 470         } s;
 471 };
 472 
 473 #define ZIP_CTL_BIST_STATUS 0x0510ull
 474 
 475 /**
 476  * union zip_ctl_cfg - Represents the register that controls the behavior of
 477  * the ZIP DMA engines.
 478  *
 479  * It is recommended to keep default values for normal operation. Changing the
 480  * values of the fields may be useful for diagnostics.
 481  */
 482 union zip_ctl_cfg {
 483         u64 u_reg64;
 484         struct zip_ctl_cfg_s {
 485 #if defined(__BIG_ENDIAN_BITFIELD)
 486                 u64 reserved_52_63              : 12;
 487                 u64 ildf                        : 4;
 488                 u64 reserved_36_47              : 12;
 489                 u64 drtf                        : 4;
 490                 u64 reserved_27_31              : 5;
 491                 u64 stcf                        : 3;
 492                 u64 reserved_19_23              : 5;
 493                 u64 ldf                         : 3;
 494                 u64 reserved_2_15               : 14;
 495                 u64 busy                        : 1;
 496                 u64 reserved_0_0                : 1;
 497 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 498                 u64 reserved_0_0                : 1;
 499                 u64 busy                        : 1;
 500                 u64 reserved_2_15               : 14;
 501                 u64 ldf                         : 3;
 502                 u64 reserved_19_23              : 5;
 503                 u64 stcf                        : 3;
 504                 u64 reserved_27_31              : 5;
 505                 u64 drtf                        : 4;
 506                 u64 reserved_36_47              : 12;
 507                 u64 ildf                        : 4;
 508                 u64 reserved_52_63              : 12;
 509 #endif
 510         } s;
 511 };
 512 
 513 #define ZIP_CTL_CFG 0x0560ull
 514 
 515 /**
 516  * union zip_dbg_corex_inst - Represents the registers that reflect the status
 517  * of the current instruction that the ZIP core is executing or has executed.
 518  *
 519  * These registers are only for debug use.
 520  */
 521 union zip_dbg_corex_inst {
 522         u64 u_reg64;
 523         struct zip_dbg_corex_inst_s {
 524 #if defined(__BIG_ENDIAN_BITFIELD)
 525                 u64 busy                        : 1;
 526                 u64 reserved_35_62              : 28;
 527                 u64 qid                         : 3;
 528                 u64 iid                         : 32;
 529 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 530                 u64 iid                         : 32;
 531                 u64 qid                         : 3;
 532                 u64 reserved_35_62              : 28;
 533                 u64 busy                        : 1;
 534 #endif
 535         } s;
 536 };
 537 
 538 static inline u64 ZIP_DBG_COREX_INST(u64 param1)
 539 {
 540         if (param1 <= 1)
 541                 return 0x0640ull + (param1 & 1) * 0x8ull;
 542         pr_err("ZIP_DBG_COREX_INST: %llu\n", param1);
 543         return 0;
 544 }
 545 
 546 /**
 547  * union zip_dbg_corex_sta - Represents registers that reflect the status of
 548  * the zip cores.
 549  *
 550  * They are for debug use only.
 551  */
 552 union zip_dbg_corex_sta {
 553         u64 u_reg64;
 554         struct zip_dbg_corex_sta_s {
 555 #if defined(__BIG_ENDIAN_BITFIELD)
 556                 u64 busy                        : 1;
 557                 u64 reserved_37_62              : 26;
 558                 u64 ist                         : 5;
 559                 u64 nie                         : 32;
 560 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 561                 u64 nie                         : 32;
 562                 u64 ist                         : 5;
 563                 u64 reserved_37_62              : 26;
 564                 u64 busy                        : 1;
 565 #endif
 566         } s;
 567 };
 568 
 569 static inline u64 ZIP_DBG_COREX_STA(u64 param1)
 570 {
 571         if (param1 <= 1)
 572                 return 0x0680ull + (param1 & 1) * 0x8ull;
 573         pr_err("ZIP_DBG_COREX_STA: %llu\n", param1);
 574         return 0;
 575 }
 576 
 577 /**
 578  * union zip_dbg_quex_sta - Represets registers that reflect status of the zip
 579  * instruction queues.
 580  *
 581  * They are for debug use only.
 582  */
 583 union zip_dbg_quex_sta {
 584         u64 u_reg64;
 585         struct zip_dbg_quex_sta_s {
 586 #if defined(__BIG_ENDIAN_BITFIELD)
 587                 u64 busy                        : 1;
 588                 u64 reserved_56_62              : 7;
 589                 u64 rqwc                        : 24;
 590                 u64 nii                         : 32;
 591 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 592                 u64 nii                         : 32;
 593                 u64 rqwc                        : 24;
 594                 u64 reserved_56_62              : 7;
 595                 u64 busy                        : 1;
 596 #endif
 597         } s;
 598 };
 599 
 600 static inline u64 ZIP_DBG_QUEX_STA(u64 param1)
 601 {
 602         if (param1 <= 7)
 603                 return 0x1800ull + (param1 & 7) * 0x8ull;
 604         pr_err("ZIP_DBG_QUEX_STA: %llu\n", param1);
 605         return 0;
 606 }
 607 
 608 /**
 609  * union zip_ecc_ctl - Represents the register that enables ECC for each
 610  * individual internal memory that requires ECC.
 611  *
 612  * For debug purpose, it can also flip one or two bits in the ECC data.
 613  */
 614 union zip_ecc_ctl {
 615         u64 u_reg64;
 616         struct zip_ecc_ctl_s {
 617 #if defined(__BIG_ENDIAN_BITFIELD)
 618                 u64 reserved_19_63              : 45;
 619                 u64 vmem_cdis                   : 1;
 620                 u64 vmem_fs                     : 2;
 621                 u64 reserved_15_15              : 1;
 622                 u64 idf1_cdis                   : 1;
 623                 u64 idf1_fs                     : 2;
 624                 u64 reserved_11_11              : 1;
 625                 u64 idf0_cdis                   : 1;
 626                 u64 idf0_fs                     : 2;
 627                 u64 reserved_7_7                : 1;
 628                 u64 gspf_cdis                   : 1;
 629                 u64 gspf_fs                     : 2;
 630                 u64 reserved_3_3                : 1;
 631                 u64 iqf_cdis                    : 1;
 632                 u64 iqf_fs                      : 2;
 633 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 634                 u64 iqf_fs                      : 2;
 635                 u64 iqf_cdis                    : 1;
 636                 u64 reserved_3_3                : 1;
 637                 u64 gspf_fs                     : 2;
 638                 u64 gspf_cdis                   : 1;
 639                 u64 reserved_7_7                : 1;
 640                 u64 idf0_fs                     : 2;
 641                 u64 idf0_cdis                   : 1;
 642                 u64 reserved_11_11              : 1;
 643                 u64 idf1_fs                     : 2;
 644                 u64 idf1_cdis                   : 1;
 645                 u64 reserved_15_15              : 1;
 646                 u64 vmem_fs                     : 2;
 647                 u64 vmem_cdis                   : 1;
 648                 u64 reserved_19_63              : 45;
 649 #endif
 650         } s;
 651 };
 652 
 653 #define ZIP_ECC_CTL 0x0568ull
 654 
 655 /* NCB - zip_ecce_ena_w1c */
 656 union zip_ecce_ena_w1c {
 657         u64 u_reg64;
 658         struct zip_ecce_ena_w1c_s {
 659 #if defined(__BIG_ENDIAN_BITFIELD)
 660                 u64 reserved_37_63              : 27;
 661                 u64 dbe                         : 5;
 662                 u64 reserved_5_31               : 27;
 663                 u64 sbe                         : 5;
 664 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 665                 u64 sbe                         : 5;
 666                 u64 reserved_5_31               : 27;
 667                 u64 dbe                         : 5;
 668                 u64 reserved_37_63              : 27;
 669 #endif
 670         } s;
 671 };
 672 
 673 #define ZIP_ECCE_ENA_W1C 0x0598ull
 674 
 675 /* NCB - zip_ecce_ena_w1s */
 676 union zip_ecce_ena_w1s {
 677         u64 u_reg64;
 678         struct zip_ecce_ena_w1s_s {
 679 #if defined(__BIG_ENDIAN_BITFIELD)
 680                 u64 reserved_37_63              : 27;
 681                 u64 dbe                         : 5;
 682                 u64 reserved_5_31               : 27;
 683                 u64 sbe                         : 5;
 684 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 685                 u64 sbe                         : 5;
 686                 u64 reserved_5_31               : 27;
 687                 u64 dbe                         : 5;
 688                 u64 reserved_37_63              : 27;
 689 #endif
 690         } s;
 691 };
 692 
 693 #define ZIP_ECCE_ENA_W1S 0x0590ull
 694 
 695 /**
 696  * union zip_ecce_int - Represents the register that contains the status of the
 697  * ECC interrupt sources.
 698  */
 699 union zip_ecce_int {
 700         u64 u_reg64;
 701         struct zip_ecce_int_s {
 702 #if defined(__BIG_ENDIAN_BITFIELD)
 703                 u64 reserved_37_63              : 27;
 704                 u64 dbe                         : 5;
 705                 u64 reserved_5_31               : 27;
 706                 u64 sbe                         : 5;
 707 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 708                 u64 sbe                         : 5;
 709                 u64 reserved_5_31               : 27;
 710                 u64 dbe                         : 5;
 711                 u64 reserved_37_63              : 27;
 712 #endif
 713         } s;
 714 };
 715 
 716 #define ZIP_ECCE_INT 0x0580ull
 717 
 718 /* NCB - zip_ecce_int_w1s */
 719 union zip_ecce_int_w1s {
 720         u64 u_reg64;
 721         struct zip_ecce_int_w1s_s {
 722 #if defined(__BIG_ENDIAN_BITFIELD)
 723                 u64 reserved_37_63              : 27;
 724                 u64 dbe                         : 5;
 725                 u64 reserved_5_31               : 27;
 726                 u64 sbe                         : 5;
 727 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 728                 u64 sbe                         : 5;
 729                 u64 reserved_5_31               : 27;
 730                 u64 dbe                         : 5;
 731                 u64 reserved_37_63              : 27;
 732 #endif
 733         } s;
 734 };
 735 
 736 #define ZIP_ECCE_INT_W1S 0x0588ull
 737 
 738 /* NCB - zip_fife_ena_w1c */
 739 union zip_fife_ena_w1c {
 740         u64 u_reg64;
 741         struct zip_fife_ena_w1c_s {
 742 #if defined(__BIG_ENDIAN_BITFIELD)
 743                 u64 reserved_42_63              : 22;
 744                 u64 asserts                     : 42;
 745 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 746                 u64 asserts                     : 42;
 747                 u64 reserved_42_63              : 22;
 748 #endif
 749         } s;
 750 };
 751 
 752 #define ZIP_FIFE_ENA_W1C 0x0090ull
 753 
 754 /* NCB - zip_fife_ena_w1s */
 755 union zip_fife_ena_w1s {
 756         u64 u_reg64;
 757         struct zip_fife_ena_w1s_s {
 758 #if defined(__BIG_ENDIAN_BITFIELD)
 759                 u64 reserved_42_63              : 22;
 760                 u64 asserts                     : 42;
 761 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 762                 u64 asserts                     : 42;
 763                 u64 reserved_42_63              : 22;
 764 #endif
 765         } s;
 766 };
 767 
 768 #define ZIP_FIFE_ENA_W1S 0x0088ull
 769 
 770 /* NCB - zip_fife_int */
 771 union zip_fife_int {
 772         u64 u_reg64;
 773         struct zip_fife_int_s {
 774 #if defined(__BIG_ENDIAN_BITFIELD)
 775                 u64 reserved_42_63              : 22;
 776                 u64 asserts                     : 42;
 777 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 778                 u64 asserts                     : 42;
 779                 u64 reserved_42_63              : 22;
 780 #endif
 781         } s;
 782 };
 783 
 784 #define ZIP_FIFE_INT 0x0078ull
 785 
 786 /* NCB - zip_fife_int_w1s */
 787 union zip_fife_int_w1s {
 788         u64 u_reg64;
 789         struct zip_fife_int_w1s_s {
 790 #if defined(__BIG_ENDIAN_BITFIELD)
 791                 u64 reserved_42_63              : 22;
 792                 u64 asserts                     : 42;
 793 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 794                 u64 asserts                     : 42;
 795                 u64 reserved_42_63              : 22;
 796 #endif
 797         } s;
 798 };
 799 
 800 #define ZIP_FIFE_INT_W1S 0x0080ull
 801 
 802 /**
 803  * union zip_msix_pbax - Represents the register that is the MSI-X PBA table
 804  *
 805  * The bit number is indexed by the ZIP_INT_VEC_E enumeration.
 806  */
 807 union zip_msix_pbax {
 808         u64 u_reg64;
 809         struct zip_msix_pbax_s {
 810 #if defined(__BIG_ENDIAN_BITFIELD)
 811                 u64 pend                        : 64;
 812 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 813                 u64 pend                        : 64;
 814 #endif
 815         } s;
 816 };
 817 
 818 static inline u64 ZIP_MSIX_PBAX(u64 param1)
 819 {
 820         if (param1 == 0)
 821                 return 0x0000838000FF0000ull;
 822         pr_err("ZIP_MSIX_PBAX: %llu\n", param1);
 823         return 0;
 824 }
 825 
 826 /**
 827  * union zip_msix_vecx_addr - Represents the register that is the MSI-X vector
 828  * table, indexed by the ZIP_INT_VEC_E enumeration.
 829  */
 830 union zip_msix_vecx_addr {
 831         u64 u_reg64;
 832         struct zip_msix_vecx_addr_s {
 833 #if defined(__BIG_ENDIAN_BITFIELD)
 834                 u64 reserved_49_63              : 15;
 835                 u64 addr                        : 47;
 836                 u64 reserved_1_1                : 1;
 837                 u64 secvec                      : 1;
 838 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 839                 u64 secvec                      : 1;
 840                 u64 reserved_1_1                : 1;
 841                 u64 addr                        : 47;
 842                 u64 reserved_49_63              : 15;
 843 #endif
 844         } s;
 845 };
 846 
 847 static inline u64 ZIP_MSIX_VECX_ADDR(u64 param1)
 848 {
 849         if (param1 <= 17)
 850                 return 0x0000838000F00000ull + (param1 & 31) * 0x10ull;
 851         pr_err("ZIP_MSIX_VECX_ADDR: %llu\n", param1);
 852         return 0;
 853 }
 854 
 855 /**
 856  * union zip_msix_vecx_ctl - Represents the register that is the MSI-X vector
 857  * table, indexed by the ZIP_INT_VEC_E enumeration.
 858  */
 859 union zip_msix_vecx_ctl {
 860         u64 u_reg64;
 861         struct zip_msix_vecx_ctl_s {
 862 #if defined(__BIG_ENDIAN_BITFIELD)
 863                 u64 reserved_33_63              : 31;
 864                 u64 mask                        : 1;
 865                 u64 reserved_20_31              : 12;
 866                 u64 data                        : 20;
 867 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 868                 u64 data                        : 20;
 869                 u64 reserved_20_31              : 12;
 870                 u64 mask                        : 1;
 871                 u64 reserved_33_63              : 31;
 872 #endif
 873         } s;
 874 };
 875 
 876 static inline u64 ZIP_MSIX_VECX_CTL(u64 param1)
 877 {
 878         if (param1 <= 17)
 879                 return 0x0000838000F00008ull + (param1 & 31) * 0x10ull;
 880         pr_err("ZIP_MSIX_VECX_CTL: %llu\n", param1);
 881         return 0;
 882 }
 883 
 884 /**
 885  * union zip_quex_done - Represents the registers that contain the per-queue
 886  * instruction done count.
 887  */
 888 union zip_quex_done {
 889         u64 u_reg64;
 890         struct zip_quex_done_s {
 891 #if defined(__BIG_ENDIAN_BITFIELD)
 892                 u64 reserved_20_63              : 44;
 893                 u64 done                        : 20;
 894 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 895                 u64 done                        : 20;
 896                 u64 reserved_20_63              : 44;
 897 #endif
 898         } s;
 899 };
 900 
 901 static inline u64 ZIP_QUEX_DONE(u64 param1)
 902 {
 903         if (param1 <= 7)
 904                 return 0x2000ull + (param1 & 7) * 0x8ull;
 905         pr_err("ZIP_QUEX_DONE: %llu\n", param1);
 906         return 0;
 907 }
 908 
 909 /**
 910  * union zip_quex_done_ack - Represents the registers on write to which will
 911  * decrement the per-queue instructiona done count.
 912  */
 913 union zip_quex_done_ack {
 914         u64 u_reg64;
 915         struct zip_quex_done_ack_s {
 916 #if defined(__BIG_ENDIAN_BITFIELD)
 917                 u64 reserved_20_63              : 44;
 918                 u64 done_ack                    : 20;
 919 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 920                 u64 done_ack                    : 20;
 921                 u64 reserved_20_63              : 44;
 922 #endif
 923         } s;
 924 };
 925 
 926 static inline u64 ZIP_QUEX_DONE_ACK(u64 param1)
 927 {
 928         if (param1 <= 7)
 929                 return 0x2200ull + (param1 & 7) * 0x8ull;
 930         pr_err("ZIP_QUEX_DONE_ACK: %llu\n", param1);
 931         return 0;
 932 }
 933 
 934 /**
 935  * union zip_quex_done_ena_w1c - Represents the register which when written
 936  * 1 to will disable the DONEINT interrupt for the queue.
 937  */
 938 union zip_quex_done_ena_w1c {
 939         u64 u_reg64;
 940         struct zip_quex_done_ena_w1c_s {
 941 #if defined(__BIG_ENDIAN_BITFIELD)
 942                 u64 reserved_1_63               : 63;
 943                 u64 done_ena                    : 1;
 944 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 945                 u64 done_ena                    : 1;
 946                 u64 reserved_1_63               : 63;
 947 #endif
 948         } s;
 949 };
 950 
 951 static inline u64 ZIP_QUEX_DONE_ENA_W1C(u64 param1)
 952 {
 953         if (param1 <= 7)
 954                 return 0x2600ull + (param1 & 7) * 0x8ull;
 955         pr_err("ZIP_QUEX_DONE_ENA_W1C: %llu\n", param1);
 956         return 0;
 957 }
 958 
 959 /**
 960  * union zip_quex_done_ena_w1s - Represents the register that when written 1 to
 961  * will enable the DONEINT interrupt for the queue.
 962  */
 963 union zip_quex_done_ena_w1s {
 964         u64 u_reg64;
 965         struct zip_quex_done_ena_w1s_s {
 966 #if defined(__BIG_ENDIAN_BITFIELD)
 967                 u64 reserved_1_63               : 63;
 968                 u64 done_ena                    : 1;
 969 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 970                 u64 done_ena                    : 1;
 971                 u64 reserved_1_63               : 63;
 972 #endif
 973         } s;
 974 };
 975 
 976 static inline u64 ZIP_QUEX_DONE_ENA_W1S(u64 param1)
 977 {
 978         if (param1 <= 7)
 979                 return 0x2400ull + (param1 & 7) * 0x8ull;
 980         pr_err("ZIP_QUEX_DONE_ENA_W1S: %llu\n", param1);
 981         return 0;
 982 }
 983 
 984 /**
 985  * union zip_quex_done_wait - Represents the register that specifies the per
 986  * queue interrupt coalescing settings.
 987  */
 988 union zip_quex_done_wait {
 989         u64 u_reg64;
 990         struct zip_quex_done_wait_s {
 991 #if defined(__BIG_ENDIAN_BITFIELD)
 992                 u64 reserved_48_63              : 16;
 993                 u64 time_wait                   : 16;
 994                 u64 reserved_20_31              : 12;
 995                 u64 num_wait                    : 20;
 996 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 997                 u64 num_wait                    : 20;
 998                 u64 reserved_20_31              : 12;
 999                 u64 time_wait                   : 16;
1000                 u64 reserved_48_63              : 16;
1001 #endif
1002         } s;
1003 };
1004 
1005 static inline u64 ZIP_QUEX_DONE_WAIT(u64 param1)
1006 {
1007         if (param1 <= 7)
1008                 return 0x2800ull + (param1 & 7) * 0x8ull;
1009         pr_err("ZIP_QUEX_DONE_WAIT: %llu\n", param1);
1010         return 0;
1011 }
1012 
1013 /**
1014  * union zip_quex_doorbell - Represents doorbell registers for the ZIP
1015  * instruction queues.
1016  */
1017 union zip_quex_doorbell {
1018         u64 u_reg64;
1019         struct zip_quex_doorbell_s {
1020 #if defined(__BIG_ENDIAN_BITFIELD)
1021                 u64 reserved_20_63              : 44;
1022                 u64 dbell_cnt                   : 20;
1023 #elif defined(__LITTLE_ENDIAN_BITFIELD)
1024                 u64 dbell_cnt                   : 20;
1025                 u64 reserved_20_63              : 44;
1026 #endif
1027         } s;
1028 };
1029 
1030 static inline u64 ZIP_QUEX_DOORBELL(u64 param1)
1031 {
1032         if (param1 <= 7)
1033                 return 0x4000ull + (param1 & 7) * 0x8ull;
1034         pr_err("ZIP_QUEX_DOORBELL: %llu\n", param1);
1035         return 0;
1036 }
1037 
1038 union zip_quex_err_ena_w1c {
1039         u64 u_reg64;
1040         struct zip_quex_err_ena_w1c_s {
1041 #if defined(__BIG_ENDIAN_BITFIELD)
1042                 u64 reserved_5_63               : 59;
1043                 u64 mdbe                        : 1;
1044                 u64 nwrp                        : 1;
1045                 u64 nrrp                        : 1;
1046                 u64 irde                        : 1;
1047                 u64 dovf                        : 1;
1048 #elif defined(__LITTLE_ENDIAN_BITFIELD)
1049                 u64 dovf                        : 1;
1050                 u64 irde                        : 1;
1051                 u64 nrrp                        : 1;
1052                 u64 nwrp                        : 1;
1053                 u64 mdbe                        : 1;
1054                 u64 reserved_5_63               : 59;
1055 #endif
1056         } s;
1057 };
1058 
1059 static inline u64 ZIP_QUEX_ERR_ENA_W1C(u64 param1)
1060 {
1061         if (param1 <= 7)
1062                 return 0x3600ull + (param1 & 7) * 0x8ull;
1063         pr_err("ZIP_QUEX_ERR_ENA_W1C: %llu\n", param1);
1064         return 0;
1065 }
1066 
1067 union zip_quex_err_ena_w1s {
1068         u64 u_reg64;
1069         struct zip_quex_err_ena_w1s_s {
1070 #if defined(__BIG_ENDIAN_BITFIELD)
1071                 u64 reserved_5_63               : 59;
1072                 u64 mdbe                        : 1;
1073                 u64 nwrp                        : 1;
1074                 u64 nrrp                        : 1;
1075                 u64 irde                        : 1;
1076                 u64 dovf                        : 1;
1077 #elif defined(__LITTLE_ENDIAN_BITFIELD)
1078                 u64 dovf                        : 1;
1079                 u64 irde                        : 1;
1080                 u64 nrrp                        : 1;
1081                 u64 nwrp                        : 1;
1082                 u64 mdbe                        : 1;
1083                 u64 reserved_5_63               : 59;
1084 #endif
1085         } s;
1086 };
1087 
1088 static inline u64 ZIP_QUEX_ERR_ENA_W1S(u64 param1)
1089 {
1090         if (param1 <= 7)
1091                 return 0x3400ull + (param1 & 7) * 0x8ull;
1092         pr_err("ZIP_QUEX_ERR_ENA_W1S: %llu\n", param1);
1093         return 0;
1094 }
1095 
1096 /**
1097  * union zip_quex_err_int - Represents registers that contain the per-queue
1098  * error interrupts.
1099  */
1100 union zip_quex_err_int {
1101         u64 u_reg64;
1102         struct zip_quex_err_int_s {
1103 #if defined(__BIG_ENDIAN_BITFIELD)
1104                 u64 reserved_5_63               : 59;
1105                 u64 mdbe                        : 1;
1106                 u64 nwrp                        : 1;
1107                 u64 nrrp                        : 1;
1108                 u64 irde                        : 1;
1109                 u64 dovf                        : 1;
1110 #elif defined(__LITTLE_ENDIAN_BITFIELD)
1111                 u64 dovf                        : 1;
1112                 u64 irde                        : 1;
1113                 u64 nrrp                        : 1;
1114                 u64 nwrp                        : 1;
1115                 u64 mdbe                        : 1;
1116                 u64 reserved_5_63               : 59;
1117 #endif
1118         } s;
1119 };
1120 
1121 static inline u64 ZIP_QUEX_ERR_INT(u64 param1)
1122 {
1123         if (param1 <= 7)
1124                 return 0x3000ull + (param1 & 7) * 0x8ull;
1125         pr_err("ZIP_QUEX_ERR_INT: %llu\n", param1);
1126         return 0;
1127 }
1128 
1129 /* NCB - zip_que#_err_int_w1s */
1130 union zip_quex_err_int_w1s {
1131         u64 u_reg64;
1132         struct zip_quex_err_int_w1s_s {
1133 #if defined(__BIG_ENDIAN_BITFIELD)
1134                 u64 reserved_5_63               : 59;
1135                 u64 mdbe                        : 1;
1136                 u64 nwrp                        : 1;
1137                 u64 nrrp                        : 1;
1138                 u64 irde                        : 1;
1139                 u64 dovf                        : 1;
1140 #elif defined(__LITTLE_ENDIAN_BITFIELD)
1141                 u64 dovf                        : 1;
1142                 u64 irde                        : 1;
1143                 u64 nrrp                        : 1;
1144                 u64 nwrp                        : 1;
1145                 u64 mdbe                        : 1;
1146                 u64 reserved_5_63               : 59;
1147 #endif
1148         } s;
1149 };
1150 
1151 static inline u64 ZIP_QUEX_ERR_INT_W1S(u64 param1)
1152 {
1153         if (param1 <= 7)
1154                 return 0x3200ull + (param1 & 7) * 0x8ull;
1155         pr_err("ZIP_QUEX_ERR_INT_W1S: %llu\n", param1);
1156         return 0;
1157 }
1158 
1159 /**
1160  * union zip_quex_gcfg - Represents the registers that reflect status of the
1161  * zip instruction queues,debug use only.
1162  */
1163 union zip_quex_gcfg {
1164         u64 u_reg64;
1165         struct zip_quex_gcfg_s {
1166 #if defined(__BIG_ENDIAN_BITFIELD)
1167                 u64 reserved_4_63               : 60;
1168                 u64 iqb_ldwb                    : 1;
1169                 u64 cbw_sty                     : 1;
1170                 u64 l2ld_cmd                    : 2;
1171 #elif defined(__LITTLE_ENDIAN_BITFIELD)
1172                 u64 l2ld_cmd                    : 2;
1173                 u64 cbw_sty                     : 1;
1174                 u64 iqb_ldwb                    : 1;
1175                 u64 reserved_4_63               : 60;
1176 #endif
1177         } s;
1178 };
1179 
1180 static inline u64 ZIP_QUEX_GCFG(u64 param1)
1181 {
1182         if (param1 <= 7)
1183                 return 0x1A00ull + (param1 & 7) * 0x8ull;
1184         pr_err("ZIP_QUEX_GCFG: %llu\n", param1);
1185         return 0;
1186 }
1187 
1188 /**
1189  * union zip_quex_map - Represents the registers that control how each
1190  * instruction queue maps to zip cores.
1191  */
1192 union zip_quex_map {
1193         u64 u_reg64;
1194         struct zip_quex_map_s {
1195 #if defined(__BIG_ENDIAN_BITFIELD)
1196                 u64 reserved_2_63               : 62;
1197                 u64 zce                         : 2;
1198 #elif defined(__LITTLE_ENDIAN_BITFIELD)
1199                 u64 zce                         : 2;
1200                 u64 reserved_2_63               : 62;
1201 #endif
1202         } s;
1203 };
1204 
1205 static inline u64 ZIP_QUEX_MAP(u64 param1)
1206 {
1207         if (param1 <= 7)
1208                 return 0x1400ull + (param1 & 7) * 0x8ull;
1209         pr_err("ZIP_QUEX_MAP: %llu\n", param1);
1210         return 0;
1211 }
1212 
1213 /**
1214  * union zip_quex_sbuf_addr - Represents the registers that set the buffer
1215  * parameters for the instruction queues.
1216  *
1217  * When quiescent (i.e. outstanding doorbell count is 0), it is safe to rewrite
1218  * this register to effectively reset the command buffer state machine.
1219  * These registers must be programmed after SW programs the corresponding
1220  * ZIP_QUE(0..7)_SBUF_CTL.
1221  */
1222 union zip_quex_sbuf_addr {
1223         u64 u_reg64;
1224         struct zip_quex_sbuf_addr_s {
1225 #if defined(__BIG_ENDIAN_BITFIELD)
1226                 u64 reserved_49_63              : 15;
1227                 u64 ptr                         : 42;
1228                 u64 off                         : 7;
1229 #elif defined(__LITTLE_ENDIAN_BITFIELD)
1230                 u64 off                         : 7;
1231                 u64 ptr                         : 42;
1232                 u64 reserved_49_63              : 15;
1233 #endif
1234         } s;
1235 };
1236 
1237 static inline u64 ZIP_QUEX_SBUF_ADDR(u64 param1)
1238 {
1239         if (param1 <= 7)
1240                 return 0x1000ull + (param1 & 7) * 0x8ull;
1241         pr_err("ZIP_QUEX_SBUF_ADDR: %llu\n", param1);
1242         return 0;
1243 }
1244 
1245 /**
1246  * union zip_quex_sbuf_ctl - Represents the registers that set the buffer
1247  * parameters for the instruction queues.
1248  *
1249  * When quiescent (i.e. outstanding doorbell count is 0), it is safe to rewrite
1250  * this register to effectively reset the command buffer state machine.
1251  * These registers must be programmed before SW programs the corresponding
1252  * ZIP_QUE(0..7)_SBUF_ADDR.
1253  */
1254 union zip_quex_sbuf_ctl {
1255         u64 u_reg64;
1256         struct zip_quex_sbuf_ctl_s {
1257 #if defined(__BIG_ENDIAN_BITFIELD)
1258                 u64 reserved_45_63              : 19;
1259                 u64 size                        : 13;
1260                 u64 inst_be                     : 1;
1261                 u64 reserved_24_30              : 7;
1262                 u64 stream_id                   : 8;
1263                 u64 reserved_12_15              : 4;
1264                 u64 aura                        : 12;
1265 #elif defined(__LITTLE_ENDIAN_BITFIELD)
1266                 u64 aura                        : 12;
1267                 u64 reserved_12_15              : 4;
1268                 u64 stream_id                   : 8;
1269                 u64 reserved_24_30              : 7;
1270                 u64 inst_be                     : 1;
1271                 u64 size                        : 13;
1272                 u64 reserved_45_63              : 19;
1273 #endif
1274         } s;
1275 };
1276 
1277 static inline u64 ZIP_QUEX_SBUF_CTL(u64 param1)
1278 {
1279         if (param1 <= 7)
1280                 return 0x1200ull + (param1 & 7) * 0x8ull;
1281         pr_err("ZIP_QUEX_SBUF_CTL: %llu\n", param1);
1282         return 0;
1283 }
1284 
1285 /**
1286  * union zip_que_ena - Represents queue enable register
1287  *
1288  * If a queue is disabled, ZIP_CTL stops fetching instructions from the queue.
1289  */
1290 union zip_que_ena {
1291         u64 u_reg64;
1292         struct zip_que_ena_s {
1293 #if defined(__BIG_ENDIAN_BITFIELD)
1294                 u64 reserved_8_63               : 56;
1295                 u64 ena                         : 8;
1296 #elif defined(__LITTLE_ENDIAN_BITFIELD)
1297                 u64 ena                         : 8;
1298                 u64 reserved_8_63               : 56;
1299 #endif
1300         } s;
1301 };
1302 
1303 #define ZIP_QUE_ENA 0x0500ull
1304 
1305 /**
1306  * union zip_que_pri - Represents the register that defines the priority
1307  * between instruction queues.
1308  */
1309 union zip_que_pri {
1310         u64 u_reg64;
1311         struct zip_que_pri_s {
1312 #if defined(__BIG_ENDIAN_BITFIELD)
1313                 u64 reserved_8_63               : 56;
1314                 u64 pri                         : 8;
1315 #elif defined(__LITTLE_ENDIAN_BITFIELD)
1316                 u64 pri                         : 8;
1317                 u64 reserved_8_63               : 56;
1318 #endif
1319         } s;
1320 };
1321 
1322 #define ZIP_QUE_PRI 0x0508ull
1323 
1324 /**
1325  * union zip_throttle - Represents the register that controls the maximum
1326  * number of in-flight X2I data fetch transactions.
1327  *
1328  * Writing 0 to this register causes the ZIP module to temporarily suspend NCB
1329  * accesses; it is not recommended for normal operation, but may be useful for
1330  * diagnostics.
1331  */
1332 union zip_throttle {
1333         u64 u_reg64;
1334         struct zip_throttle_s {
1335 #if defined(__BIG_ENDIAN_BITFIELD)
1336                 u64 reserved_6_63               : 58;
1337                 u64 ld_infl                     : 6;
1338 #elif defined(__LITTLE_ENDIAN_BITFIELD)
1339                 u64 ld_infl                     : 6;
1340                 u64 reserved_6_63               : 58;
1341 #endif
1342         } s;
1343 };
1344 
1345 #define ZIP_THROTTLE 0x0010ull
1346 
1347 #endif /* _CSRS_ZIP__ */
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root/drivers/crypto/cavium/zip/zip_regs.h

INCLUDED FROM

DEFINITIONS
