arch/microblaze/kernel/hw_exception

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   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Exception handling for Microblaze
   4  *
   5  * Rewriten interrupt handling
   6  *
   7  * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
   8  * Copyright (C) 2008-2009 PetaLogix
   9  *
  10  * uClinux customisation (C) 2005 John Williams
  11  *
  12  * MMU code derived from arch/ppc/kernel/head_4xx.S:
  13  *      Copyright (C) 1995-1996 Gary Thomas <gdt@linuxppc.org>
  14  *              Initial PowerPC version.
  15  *      Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
  16  *              Rewritten for PReP
  17  *      Copyright (C) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
  18  *              Low-level exception handers, MMU support, and rewrite.
  19  *      Copyright (C) 1997 Dan Malek <dmalek@jlc.net>
  20  *              PowerPC 8xx modifications.
  21  *      Copyright (C) 1998-1999 TiVo, Inc.
  22  *              PowerPC 403GCX modifications.
  23  *      Copyright (C) 1999 Grant Erickson <grant@lcse.umn.edu>
  24  *              PowerPC 403GCX/405GP modifications.
  25  *      Copyright 2000 MontaVista Software Inc.
  26  *              PPC405 modifications
  27  *      PowerPC 403GCX/405GP modifications.
  28  *              Author: MontaVista Software, Inc.
  29  *              frank_rowand@mvista.com or source@mvista.com
  30  *              debbie_chu@mvista.com
  31  *
  32  * Original code
  33  * Copyright (C) 2004 Xilinx, Inc.
  34  */
  35 
  36 /*
  37  * Here are the handlers which don't require enabling translation
  38  * and calling other kernel code thus we can keep their design very simple
  39  * and do all processing in real mode. All what they need is a valid current
  40  * (that is an issue for the CONFIG_REGISTER_TASK_PTR case)
  41  * This handlers use r3,r4,r5,r6 and optionally r[current] to work therefore
  42  * these registers are saved/restored
  43  * The handlers which require translation are in entry.S --KAA
  44  *
  45  * Microblaze HW Exception Handler
  46  * - Non self-modifying exception handler for the following exception conditions
  47  *   - Unalignment
  48  *   - Instruction bus error
  49  *   - Data bus error
  50  *   - Illegal instruction opcode
  51  *   - Divide-by-zero
  52  *
  53  *   - Privileged instruction exception (MMU)
  54  *   - Data storage exception (MMU)
  55  *   - Instruction storage exception (MMU)
  56  *   - Data TLB miss exception (MMU)
  57  *   - Instruction TLB miss exception (MMU)
  58  *
  59  * Note we disable interrupts during exception handling, otherwise we will
  60  * possibly get multiple re-entrancy if interrupt handles themselves cause
  61  * exceptions. JW
  62  */
  63 
  64 #include <asm/exceptions.h>
  65 #include <asm/unistd.h>
  66 #include <asm/page.h>
  67 
  68 #include <asm/entry.h>
  69 #include <asm/current.h>
  70 #include <linux/linkage.h>
  71 
  72 #include <asm/mmu.h>
  73 #include <asm/pgtable.h>
  74 #include <asm/signal.h>
  75 #include <asm/registers.h>
  76 #include <asm/asm-offsets.h>
  77 
  78 #undef DEBUG
  79 
  80 /* Helpful Macros */
  81 #define NUM_TO_REG(num)         r ## num
  82 
  83 #ifdef CONFIG_MMU
  84         #define RESTORE_STATE                   \
  85                 lwi     r5, r1, 0;              \
  86                 mts     rmsr, r5;               \
  87                 nop;                            \
  88                 lwi     r3, r1, PT_R3;          \
  89                 lwi     r4, r1, PT_R4;          \
  90                 lwi     r5, r1, PT_R5;          \
  91                 lwi     r6, r1, PT_R6;          \
  92                 lwi     r11, r1, PT_R11;        \
  93                 lwi     r31, r1, PT_R31;        \
  94                 lwi     r1, r1, PT_R1;
  95 #endif /* CONFIG_MMU */
  96 
  97 #define LWREG_NOP                       \
  98         bri     ex_handler_unhandled;   \
  99         nop;
 100 
 101 #define SWREG_NOP                       \
 102         bri     ex_handler_unhandled;   \
 103         nop;
 104 
 105 /* FIXME this is weird - for noMMU kernel is not possible to use brid
 106  * instruction which can shorten executed time
 107  */
 108 
 109 /* r3 is the source */
 110 #define R3_TO_LWREG_V(regnum)                           \
 111         swi     r3, r1, 4 * regnum;                             \
 112         bri     ex_handler_done;
 113 
 114 /* r3 is the source */
 115 #define R3_TO_LWREG(regnum)                             \
 116         or      NUM_TO_REG (regnum), r0, r3;            \
 117         bri     ex_handler_done;
 118 
 119 /* r3 is the target */
 120 #define SWREG_TO_R3_V(regnum)                           \
 121         lwi     r3, r1, 4 * regnum;                             \
 122         bri     ex_sw_tail;
 123 
 124 /* r3 is the target */
 125 #define SWREG_TO_R3(regnum)                             \
 126         or      r3, r0, NUM_TO_REG (regnum);            \
 127         bri     ex_sw_tail;
 128 
 129 #ifdef CONFIG_MMU
 130         #define R3_TO_LWREG_VM_V(regnum)                \
 131                 brid    ex_lw_end_vm;                   \
 132                 swi     r3, r7, 4 * regnum;
 133 
 134         #define R3_TO_LWREG_VM(regnum)                  \
 135                 brid    ex_lw_end_vm;                   \
 136                 or      NUM_TO_REG (regnum), r0, r3;
 137 
 138         #define SWREG_TO_R3_VM_V(regnum)                \
 139                 brid    ex_sw_tail_vm;                  \
 140                 lwi     r3, r7, 4 * regnum;
 141 
 142         #define SWREG_TO_R3_VM(regnum)                  \
 143                 brid    ex_sw_tail_vm;                  \
 144                 or      r3, r0, NUM_TO_REG (regnum);
 145 
 146         /* Shift right instruction depending on available configuration */
 147         #if CONFIG_XILINX_MICROBLAZE0_USE_BARREL == 0
 148         /* Only the used shift constants defined here - add more if needed */
 149         #define BSRLI2(rD, rA)                          \
 150                 srl rD, rA;             /* << 1 */      \
 151                 srl rD, rD;             /* << 2 */
 152         #define BSRLI4(rD, rA)          \
 153                 BSRLI2(rD, rA);         \
 154                 BSRLI2(rD, rD)
 155         #define BSRLI10(rD, rA)                         \
 156                 srl rD, rA;             /* << 1 */      \
 157                 srl rD, rD;             /* << 2 */      \
 158                 srl rD, rD;             /* << 3 */      \
 159                 srl rD, rD;             /* << 4 */      \
 160                 srl rD, rD;             /* << 5 */      \
 161                 srl rD, rD;             /* << 6 */      \
 162                 srl rD, rD;             /* << 7 */      \
 163                 srl rD, rD;             /* << 8 */      \
 164                 srl rD, rD;             /* << 9 */      \
 165                 srl rD, rD              /* << 10 */
 166         #define BSRLI20(rD, rA)         \
 167                 BSRLI10(rD, rA);        \
 168                 BSRLI10(rD, rD)
 169 
 170         .macro  bsrli, rD, rA, IMM
 171         .if (\IMM) == 2
 172                 BSRLI2(\rD, \rA)
 173         .elseif (\IMM) == 10
 174                 BSRLI10(\rD, \rA)
 175         .elseif (\IMM) == 12
 176                 BSRLI2(\rD, \rA)
 177                 BSRLI10(\rD, \rD)
 178         .elseif (\IMM) == 14
 179                 BSRLI4(\rD, \rA)
 180                 BSRLI10(\rD, \rD)
 181         .elseif (\IMM) == 20
 182                 BSRLI20(\rD, \rA)
 183         .elseif (\IMM) == 24
 184                 BSRLI4(\rD, \rA)
 185                 BSRLI20(\rD, \rD)
 186         .elseif (\IMM) == 28
 187                 BSRLI4(\rD, \rA)
 188                 BSRLI4(\rD, \rD)
 189                 BSRLI20(\rD, \rD)
 190         .else
 191         .error "BSRLI shift macros \IMM"
 192         .endif
 193         .endm
 194         #endif
 195 
 196 #endif /* CONFIG_MMU */
 197 
 198 .extern other_exception_handler /* Defined in exception.c */
 199 
 200 /*
 201  * hw_exception_handler - Handler for exceptions
 202  *
 203  * Exception handler notes:
 204  * - Handles all exceptions
 205  * - Does not handle unaligned exceptions during load into r17, r1, r0.
 206  * - Does not handle unaligned exceptions during store from r17 (cannot be
 207  *   done) and r1 (slows down common case)
 208  *
 209  *  Relevant register structures
 210  *
 211  *  EAR - |----|----|----|----|----|----|----|----|
 212  *      - <  ##   32 bit faulting address     ##  >
 213  *
 214  *  ESR - |----|----|----|----|----| - | - |-----|-----|
 215  *      -                            W   S   REG   EXC
 216  *
 217  *
 218  * STACK FRAME STRUCTURE (for CONFIG_MMU=n)
 219  * ----------------------------------------
 220  *
 221  *      +-------------+         + 0
 222  *      |     MSR     |
 223  *      +-------------+         + 4
 224  *      |     r1      |
 225  *      |      .      |
 226  *      |      .      |
 227  *      |      .      |
 228  *      |      .      |
 229  *      |     r18     |
 230  *      +-------------+         + 76
 231  *      |      .      |
 232  *      |      .      |
 233  *
 234  * MMU kernel uses the same 'pt_pool_space' pointed space
 235  * which is used for storing register values - noMMu style was, that values were
 236  * stored in stack but in case of failure you lost information about register.
 237  * Currently you can see register value in memory in specific place.
 238  * In compare to with previous solution the speed should be the same.
 239  *
 240  * MMU exception handler has different handling compare to no MMU kernel.
 241  * Exception handler use jump table for directing of what happen. For MMU kernel
 242  * is this approach better because MMU relate exception are handled by asm code
 243  * in this file. In compare to with MMU expect of unaligned exception
 244  * is everything handled by C code.
 245  */
 246 
 247 /*
 248  * every of these handlers is entered having R3/4/5/6/11/current saved on stack
 249  * and clobbered so care should be taken to restore them if someone is going to
 250  * return from exception
 251  */
 252 
 253 /* wrappers to restore state before coming to entry.S */
 254 #ifdef CONFIG_MMU
 255 .section .data
 256 .align 4
 257 pt_pool_space:
 258         .space  PT_SIZE
 259 
 260 #ifdef DEBUG
 261 /* Create space for exception counting. */
 262 .section .data
 263 .global exception_debug_table
 264 .align 4
 265 exception_debug_table:
 266         /* Look at exception vector table. There is 32 exceptions * word size */
 267         .space  (32 * 4)
 268 #endif /* DEBUG */
 269 
 270 .section .rodata
 271 .align 4
 272 _MB_HW_ExceptionVectorTable:
 273 /*  0 - Undefined */
 274         .long   TOPHYS(ex_handler_unhandled)
 275 /*  1 - Unaligned data access exception */
 276         .long   TOPHYS(handle_unaligned_ex)
 277 /*  2 - Illegal op-code exception */
 278         .long   TOPHYS(full_exception_trapw)
 279 /*  3 - Instruction bus error exception */
 280         .long   TOPHYS(full_exception_trapw)
 281 /*  4 - Data bus error exception */
 282         .long   TOPHYS(full_exception_trapw)
 283 /*  5 - Divide by zero exception */
 284         .long   TOPHYS(full_exception_trapw)
 285 /*  6 - Floating point unit exception */
 286         .long   TOPHYS(full_exception_trapw)
 287 /*  7 - Privileged instruction exception */
 288         .long   TOPHYS(full_exception_trapw)
 289 /*  8 - 15 - Undefined */
 290         .long   TOPHYS(ex_handler_unhandled)
 291         .long   TOPHYS(ex_handler_unhandled)
 292         .long   TOPHYS(ex_handler_unhandled)
 293         .long   TOPHYS(ex_handler_unhandled)
 294         .long   TOPHYS(ex_handler_unhandled)
 295         .long   TOPHYS(ex_handler_unhandled)
 296         .long   TOPHYS(ex_handler_unhandled)
 297         .long   TOPHYS(ex_handler_unhandled)
 298 /* 16 - Data storage exception */
 299         .long   TOPHYS(handle_data_storage_exception)
 300 /* 17 - Instruction storage exception */
 301         .long   TOPHYS(handle_instruction_storage_exception)
 302 /* 18 - Data TLB miss exception */
 303         .long   TOPHYS(handle_data_tlb_miss_exception)
 304 /* 19 - Instruction TLB miss exception */
 305         .long   TOPHYS(handle_instruction_tlb_miss_exception)
 306 /* 20 - 31 - Undefined */
 307         .long   TOPHYS(ex_handler_unhandled)
 308         .long   TOPHYS(ex_handler_unhandled)
 309         .long   TOPHYS(ex_handler_unhandled)
 310         .long   TOPHYS(ex_handler_unhandled)
 311         .long   TOPHYS(ex_handler_unhandled)
 312         .long   TOPHYS(ex_handler_unhandled)
 313         .long   TOPHYS(ex_handler_unhandled)
 314         .long   TOPHYS(ex_handler_unhandled)
 315         .long   TOPHYS(ex_handler_unhandled)
 316         .long   TOPHYS(ex_handler_unhandled)
 317         .long   TOPHYS(ex_handler_unhandled)
 318         .long   TOPHYS(ex_handler_unhandled)
 319 #endif
 320 
 321 .global _hw_exception_handler
 322 .section .text
 323 .align 4
 324 .ent _hw_exception_handler
 325 _hw_exception_handler:
 326 #ifndef CONFIG_MMU
 327         addik   r1, r1, -(EX_HANDLER_STACK_SIZ); /* Create stack frame */
 328 #else
 329         swi     r1, r0, TOPHYS(pt_pool_space + PT_R1); /* GET_SP */
 330         /* Save date to kernel memory. Here is the problem
 331          * when you came from user space */
 332         ori     r1, r0, TOPHYS(pt_pool_space);
 333 #endif
 334         swi     r3, r1, PT_R3
 335         swi     r4, r1, PT_R4
 336         swi     r5, r1, PT_R5
 337         swi     r6, r1, PT_R6
 338 
 339 #ifdef CONFIG_MMU
 340         swi     r11, r1, PT_R11
 341         swi     r31, r1, PT_R31
 342         lwi     r31, r0, TOPHYS(PER_CPU(CURRENT_SAVE)) /* get saved current */
 343 #endif
 344 
 345         mfs     r5, rmsr;
 346         nop
 347         swi     r5, r1, 0;
 348         mfs     r4, resr
 349         nop
 350         mfs     r3, rear;
 351         nop
 352 
 353 #ifndef CONFIG_MMU
 354         andi    r5, r4, 0x1000;         /* Check ESR[DS] */
 355         beqi    r5, not_in_delay_slot;  /* Branch if ESR[DS] not set */
 356         mfs     r17, rbtr;      /* ESR[DS] set - return address in BTR */
 357         nop
 358 not_in_delay_slot:
 359         swi     r17, r1, PT_R17
 360 #endif
 361 
 362         andi    r5, r4, 0x1F;           /* Extract ESR[EXC] */
 363 
 364 #ifdef CONFIG_MMU
 365         /* Calculate exception vector offset = r5 << 2 */
 366         addk    r6, r5, r5; /* << 1 */
 367         addk    r6, r6, r6; /* << 2 */
 368 
 369 #ifdef DEBUG
 370 /* counting which exception happen */
 371         lwi     r5, r0, TOPHYS(exception_debug_table)
 372         addi    r5, r5, 1
 373         swi     r5, r0, TOPHYS(exception_debug_table)
 374         lwi     r5, r6, TOPHYS(exception_debug_table)
 375         addi    r5, r5, 1
 376         swi     r5, r6, TOPHYS(exception_debug_table)
 377 #endif
 378 /* end */
 379         /* Load the HW Exception vector */
 380         lwi     r6, r6, TOPHYS(_MB_HW_ExceptionVectorTable)
 381         bra     r6
 382 
 383 full_exception_trapw:
 384         RESTORE_STATE
 385         bri     full_exception_trap
 386 #else
 387         /* Exceptions enabled here. This will allow nested exceptions */
 388         mfs     r6, rmsr;
 389         nop
 390         swi     r6, r1, 0; /* RMSR_OFFSET */
 391         ori     r6, r6, 0x100; /* Turn ON the EE bit */
 392         andi    r6, r6, ~2; /* Disable interrupts */
 393         mts     rmsr, r6;
 394         nop
 395 
 396         xori    r6, r5, 1; /* 00001 = Unaligned Exception */
 397         /* Jump to unalignment exception handler */
 398         beqi    r6, handle_unaligned_ex;
 399 
 400 handle_other_ex: /* Handle Other exceptions here */
 401         /* Save other volatiles before we make procedure calls below */
 402         swi     r7, r1, PT_R7
 403         swi     r8, r1, PT_R8
 404         swi     r9, r1, PT_R9
 405         swi     r10, r1, PT_R10
 406         swi     r11, r1, PT_R11
 407         swi     r12, r1, PT_R12
 408         swi     r14, r1, PT_R14
 409         swi     r15, r1, PT_R15
 410         swi     r18, r1, PT_R18
 411 
 412         or      r5, r1, r0
 413         andi    r6, r4, 0x1F; /* Load ESR[EC] */
 414         lwi     r7, r0, PER_CPU(KM) /* MS: saving current kernel mode to regs */
 415         swi     r7, r1, PT_MODE
 416         mfs     r7, rfsr
 417         nop
 418         addk    r8, r17, r0; /* Load exception address */
 419         bralid  r15, full_exception; /* Branch to the handler */
 420         nop;
 421         mts     rfsr, r0;       /* Clear sticky fsr */
 422         nop
 423 
 424         /*
 425          * Trigger execution of the signal handler by enabling
 426          * interrupts and calling an invalid syscall.
 427          */
 428         mfs     r5, rmsr;
 429         nop
 430         ori     r5, r5, 2;
 431         mts     rmsr, r5; /* enable interrupt */
 432         nop
 433         addi    r12, r0, __NR_syscalls;
 434         brki    r14, 0x08;
 435         mfs     r5, rmsr; /* disable interrupt */
 436         nop
 437         andi    r5, r5, ~2;
 438         mts     rmsr, r5;
 439         nop
 440 
 441         lwi     r7, r1, PT_R7
 442         lwi     r8, r1, PT_R8
 443         lwi     r9, r1, PT_R9
 444         lwi     r10, r1, PT_R10
 445         lwi     r11, r1, PT_R11
 446         lwi     r12, r1, PT_R12
 447         lwi     r14, r1, PT_R14
 448         lwi     r15, r1, PT_R15
 449         lwi     r18, r1, PT_R18
 450 
 451         bri     ex_handler_done; /* Complete exception handling */
 452 #endif
 453 
 454 /* 0x01 - Unaligned data access exception
 455  * This occurs when a word access is not aligned on a word boundary,
 456  * or when a 16-bit access is not aligned on a 16-bit boundary.
 457  * This handler perform the access, and returns, except for MMU when
 458  * the unaligned address is last on a 4k page or the physical address is
 459  * not found in the page table, in which case unaligned_data_trap is called.
 460  */
 461 handle_unaligned_ex:
 462         /* Working registers already saved: R3, R4, R5, R6
 463          *  R4 = ESR
 464          *  R3 = EAR
 465          */
 466 #ifdef CONFIG_MMU
 467         andi    r6, r4, 0x1000                  /* Check ESR[DS] */
 468         beqi    r6, _no_delayslot               /* Branch if ESR[DS] not set */
 469         mfs     r17, rbtr;      /* ESR[DS] set - return address in BTR */
 470         nop
 471 _no_delayslot:
 472         /* jump to high level unaligned handler */
 473         RESTORE_STATE;
 474         bri     unaligned_data_trap
 475 #endif
 476         andi    r6, r4, 0x3E0; /* Mask and extract the register operand */
 477         srl     r6, r6; /* r6 >> 5 */
 478         srl     r6, r6;
 479         srl     r6, r6;
 480         srl     r6, r6;
 481         srl     r6, r6;
 482         /* Store the register operand in a temporary location */
 483         sbi     r6, r0, TOPHYS(ex_reg_op);
 484 
 485         andi    r6, r4, 0x400; /* Extract ESR[S] */
 486         bnei    r6, ex_sw;
 487 ex_lw:
 488         andi    r6, r4, 0x800; /* Extract ESR[W] */
 489         beqi    r6, ex_lhw;
 490         lbui    r5, r3, 0; /* Exception address in r3 */
 491         /* Load a word, byte-by-byte from destination address
 492                 and save it in tmp space */
 493         sbi     r5, r0, TOPHYS(ex_tmp_data_loc_0);
 494         lbui    r5, r3, 1;
 495         sbi     r5, r0, TOPHYS(ex_tmp_data_loc_1);
 496         lbui    r5, r3, 2;
 497         sbi     r5, r0, TOPHYS(ex_tmp_data_loc_2);
 498         lbui    r5, r3, 3;
 499         sbi     r5, r0, TOPHYS(ex_tmp_data_loc_3);
 500         /* Get the destination register value into r4 */
 501         lwi     r4, r0, TOPHYS(ex_tmp_data_loc_0);
 502         bri     ex_lw_tail;
 503 ex_lhw:
 504         lbui    r5, r3, 0; /* Exception address in r3 */
 505         /* Load a half-word, byte-by-byte from destination
 506                 address and save it in tmp space */
 507         sbi     r5, r0, TOPHYS(ex_tmp_data_loc_0);
 508         lbui    r5, r3, 1;
 509         sbi     r5, r0, TOPHYS(ex_tmp_data_loc_1);
 510         /* Get the destination register value into r4 */
 511         lhui    r4, r0, TOPHYS(ex_tmp_data_loc_0);
 512 ex_lw_tail:
 513         /* Get the destination register number into r5 */
 514         lbui    r5, r0, TOPHYS(ex_reg_op);
 515         /* Form load_word jump table offset (lw_table + (8 * regnum)) */
 516         addik   r6, r0, TOPHYS(lw_table);
 517         addk    r5, r5, r5;
 518         addk    r5, r5, r5;
 519         addk    r5, r5, r5;
 520         addk    r5, r5, r6;
 521         bra     r5;
 522 ex_lw_end: /* Exception handling of load word, ends */
 523 ex_sw:
 524         /* Get the destination register number into r5 */
 525         lbui    r5, r0, TOPHYS(ex_reg_op);
 526         /* Form store_word jump table offset (sw_table + (8 * regnum)) */
 527         addik   r6, r0, TOPHYS(sw_table);
 528         add     r5, r5, r5;
 529         add     r5, r5, r5;
 530         add     r5, r5, r5;
 531         add     r5, r5, r6;
 532         bra     r5;
 533 ex_sw_tail:
 534         mfs     r6, resr;
 535         nop
 536         andi    r6, r6, 0x800; /* Extract ESR[W] */
 537         beqi    r6, ex_shw;
 538         /* Get the word - delay slot */
 539         swi     r4, r0, TOPHYS(ex_tmp_data_loc_0);
 540         /* Store the word, byte-by-byte into destination address */
 541         lbui    r4, r0, TOPHYS(ex_tmp_data_loc_0);
 542         sbi     r4, r3, 0;
 543         lbui    r4, r0, TOPHYS(ex_tmp_data_loc_1);
 544         sbi     r4, r3, 1;
 545         lbui    r4, r0, TOPHYS(ex_tmp_data_loc_2);
 546         sbi     r4, r3, 2;
 547         lbui    r4, r0, TOPHYS(ex_tmp_data_loc_3);
 548         sbi     r4, r3, 3;
 549         bri     ex_handler_done;
 550 
 551 ex_shw:
 552         /* Store the lower half-word, byte-by-byte into destination address */
 553         swi     r4, r0, TOPHYS(ex_tmp_data_loc_0);
 554         lbui    r4, r0, TOPHYS(ex_tmp_data_loc_2);
 555         sbi     r4, r3, 0;
 556         lbui    r4, r0, TOPHYS(ex_tmp_data_loc_3);
 557         sbi     r4, r3, 1;
 558 ex_sw_end: /* Exception handling of store word, ends. */
 559 
 560 ex_handler_done:
 561 #ifndef CONFIG_MMU
 562         lwi     r5, r1, 0 /* RMSR */
 563         mts     rmsr, r5
 564         nop
 565         lwi     r3, r1, PT_R3
 566         lwi     r4, r1, PT_R4
 567         lwi     r5, r1, PT_R5
 568         lwi     r6, r1, PT_R6
 569         lwi     r17, r1, PT_R17
 570 
 571         rted    r17, 0
 572         addik   r1, r1, (EX_HANDLER_STACK_SIZ); /* Restore stack frame */
 573 #else
 574         RESTORE_STATE;
 575         rted    r17, 0
 576         nop
 577 #endif
 578 
 579 #ifdef CONFIG_MMU
 580         /* Exception vector entry code. This code runs with address translation
 581          * turned off (i.e. using physical addresses). */
 582 
 583         /* Exception vectors. */
 584 
 585         /* 0x10 - Data Storage Exception
 586          * This happens for just a few reasons. U0 set (but we don't do that),
 587          * or zone protection fault (user violation, write to protected page).
 588          * If this is just an update of modified status, we do that quickly
 589          * and exit. Otherwise, we call heavyweight functions to do the work.
 590          */
 591         handle_data_storage_exception:
 592                 /* Working registers already saved: R3, R4, R5, R6
 593                  * R3 = ESR
 594                  */
 595                 mfs     r11, rpid
 596                 nop
 597                 /* If we are faulting a kernel address, we have to use the
 598                  * kernel page tables.
 599                  */
 600                 ori     r5, r0, CONFIG_KERNEL_START
 601                 cmpu    r5, r3, r5
 602                 bgti    r5, ex3
 603                 /* First, check if it was a zone fault (which means a user
 604                  * tried to access a kernel or read-protected page - always
 605                  * a SEGV). All other faults here must be stores, so no
 606                  * need to check ESR_S as well. */
 607                 andi    r4, r4, ESR_DIZ         /* ESR_Z - zone protection */
 608                 bnei    r4, ex2
 609 
 610                 ori     r4, r0, swapper_pg_dir
 611                 mts     rpid, r0                /* TLB will have 0 TID */
 612                 nop
 613                 bri     ex4
 614 
 615                 /* Get the PGD for the current thread. */
 616         ex3:
 617                 /* First, check if it was a zone fault (which means a user
 618                  * tried to access a kernel or read-protected page - always
 619                  * a SEGV). All other faults here must be stores, so no
 620                  * need to check ESR_S as well. */
 621                 andi    r4, r4, ESR_DIZ         /* ESR_Z */
 622                 bnei    r4, ex2
 623                 /* get current task address */
 624                 addi    r4 ,CURRENT_TASK, TOPHYS(0);
 625                 lwi     r4, r4, TASK_THREAD+PGDIR
 626         ex4:
 627                 tophys(r4,r4)
 628                 /* Create L1 (pgdir/pmd) address */
 629                 bsrli   r5, r3, PGDIR_SHIFT - 2
 630                 andi    r5, r5, PAGE_SIZE - 4
 631 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
 632                 or      r4, r4, r5
 633                 lwi     r4, r4, 0               /* Get L1 entry */
 634                 andi    r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
 635                 beqi    r5, ex2                 /* Bail if no table */
 636 
 637                 tophys(r5,r5)
 638                 bsrli   r6, r3, PTE_SHIFT /* Compute PTE address */
 639                 andi    r6, r6, PAGE_SIZE - 4
 640                 or      r5, r5, r6
 641                 lwi     r4, r5, 0               /* Get Linux PTE */
 642 
 643                 andi    r6, r4, _PAGE_RW        /* Is it writeable? */
 644                 beqi    r6, ex2                 /* Bail if not */
 645 
 646                 /* Update 'changed' */
 647                 ori     r4, r4, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
 648                 swi     r4, r5, 0               /* Update Linux page table */
 649 
 650                 /* Most of the Linux PTE is ready to load into the TLB LO.
 651                  * We set ZSEL, where only the LS-bit determines user access.
 652                  * We set execute, because we don't have the granularity to
 653                  * properly set this at the page level (Linux problem).
 654                  * If shared is set, we cause a zero PID->TID load.
 655                  * Many of these bits are software only. Bits we don't set
 656                  * here we (properly should) assume have the appropriate value.
 657                  */
 658 /* Ignore memory coherent, just LSB on ZSEL is used + EX/WR */
 659                 andi    r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
 660                                                 TLB_ZSEL(1) | TLB_ATTR_MASK
 661                 ori     r4, r4, _PAGE_HWEXEC    /* make it executable */
 662 
 663                 /* find the TLB index that caused the fault. It has to be here*/
 664                 mts     rtlbsx, r3
 665                 nop
 666                 mfs     r5, rtlbx               /* DEBUG: TBD */
 667                 nop
 668                 mts     rtlblo, r4              /* Load TLB LO */
 669                 nop
 670                                                 /* Will sync shadow TLBs */
 671 
 672                 /* Done...restore registers and get out of here. */
 673                 mts     rpid, r11
 674                 nop
 675                 bri 4
 676 
 677                 RESTORE_STATE;
 678                 rted    r17, 0
 679                 nop
 680         ex2:
 681                 /* The bailout. Restore registers to pre-exception conditions
 682                  * and call the heavyweights to help us out. */
 683                 mts     rpid, r11
 684                 nop
 685                 bri 4
 686                 RESTORE_STATE;
 687                 bri     page_fault_data_trap
 688 
 689 
 690         /* 0x11 - Instruction Storage Exception
 691          * This is caused by a fetch from non-execute or guarded pages. */
 692         handle_instruction_storage_exception:
 693                 /* Working registers already saved: R3, R4, R5, R6
 694                  * R3 = ESR
 695                  */
 696 
 697                 RESTORE_STATE;
 698                 bri     page_fault_instr_trap
 699 
 700         /* 0x12 - Data TLB Miss Exception
 701          * As the name implies, translation is not in the MMU, so search the
 702          * page tables and fix it. The only purpose of this function is to
 703          * load TLB entries from the page table if they exist.
 704          */
 705         handle_data_tlb_miss_exception:
 706                 /* Working registers already saved: R3, R4, R5, R6
 707                  * R3 = EAR, R4 = ESR
 708                  */
 709                 mfs     r11, rpid
 710                 nop
 711 
 712                 /* If we are faulting a kernel address, we have to use the
 713                  * kernel page tables. */
 714                 ori     r6, r0, CONFIG_KERNEL_START
 715                 cmpu    r4, r3, r6
 716                 bgti    r4, ex5
 717                 ori     r4, r0, swapper_pg_dir
 718                 mts     rpid, r0                /* TLB will have 0 TID */
 719                 nop
 720                 bri     ex6
 721 
 722                 /* Get the PGD for the current thread. */
 723         ex5:
 724                 /* get current task address */
 725                 addi    r4 ,CURRENT_TASK, TOPHYS(0);
 726                 lwi     r4, r4, TASK_THREAD+PGDIR
 727         ex6:
 728                 tophys(r4,r4)
 729                 /* Create L1 (pgdir/pmd) address */
 730                 bsrli   r5, r3, PGDIR_SHIFT - 2
 731                 andi    r5, r5, PAGE_SIZE - 4
 732 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
 733                 or      r4, r4, r5
 734                 lwi     r4, r4, 0               /* Get L1 entry */
 735                 andi    r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
 736                 beqi    r5, ex7                 /* Bail if no table */
 737 
 738                 tophys(r5,r5)
 739                 bsrli   r6, r3, PTE_SHIFT /* Compute PTE address */
 740                 andi    r6, r6, PAGE_SIZE - 4
 741                 or      r5, r5, r6
 742                 lwi     r4, r5, 0               /* Get Linux PTE */
 743 
 744                 andi    r6, r4, _PAGE_PRESENT
 745                 beqi    r6, ex7
 746 
 747                 ori     r4, r4, _PAGE_ACCESSED
 748                 swi     r4, r5, 0
 749 
 750                 /* Most of the Linux PTE is ready to load into the TLB LO.
 751                  * We set ZSEL, where only the LS-bit determines user access.
 752                  * We set execute, because we don't have the granularity to
 753                  * properly set this at the page level (Linux problem).
 754                  * If shared is set, we cause a zero PID->TID load.
 755                  * Many of these bits are software only. Bits we don't set
 756                  * here we (properly should) assume have the appropriate value.
 757                  */
 758                 brid    finish_tlb_load
 759                 andi    r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
 760                                                 TLB_ZSEL(1) | TLB_ATTR_MASK
 761         ex7:
 762                 /* The bailout. Restore registers to pre-exception conditions
 763                  * and call the heavyweights to help us out.
 764                  */
 765                 mts     rpid, r11
 766                 nop
 767                 bri     4
 768                 RESTORE_STATE;
 769                 bri     page_fault_data_trap
 770 
 771         /* 0x13 - Instruction TLB Miss Exception
 772          * Nearly the same as above, except we get our information from
 773          * different registers and bailout to a different point.
 774          */
 775         handle_instruction_tlb_miss_exception:
 776                 /* Working registers already saved: R3, R4, R5, R6
 777                  *  R3 = ESR
 778                  */
 779                 mfs     r11, rpid
 780                 nop
 781 
 782                 /* If we are faulting a kernel address, we have to use the
 783                  * kernel page tables.
 784                  */
 785                 ori     r4, r0, CONFIG_KERNEL_START
 786                 cmpu    r4, r3, r4
 787                 bgti    r4, ex8
 788                 ori     r4, r0, swapper_pg_dir
 789                 mts     rpid, r0                /* TLB will have 0 TID */
 790                 nop
 791                 bri     ex9
 792 
 793                 /* Get the PGD for the current thread. */
 794         ex8:
 795                 /* get current task address */
 796                 addi    r4 ,CURRENT_TASK, TOPHYS(0);
 797                 lwi     r4, r4, TASK_THREAD+PGDIR
 798         ex9:
 799                 tophys(r4,r4)
 800                 /* Create L1 (pgdir/pmd) address */
 801                 bsrli   r5, r3, PGDIR_SHIFT - 2
 802                 andi    r5, r5, PAGE_SIZE - 4
 803 /* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
 804                 or      r4, r4, r5
 805                 lwi     r4, r4, 0               /* Get L1 entry */
 806                 andi    r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
 807                 beqi    r5, ex10                /* Bail if no table */
 808 
 809                 tophys(r5,r5)
 810                 bsrli   r6, r3, PTE_SHIFT /* Compute PTE address */
 811                 andi    r6, r6, PAGE_SIZE - 4
 812                 or      r5, r5, r6
 813                 lwi     r4, r5, 0               /* Get Linux PTE */
 814 
 815                 andi    r6, r4, _PAGE_PRESENT
 816                 beqi    r6, ex10
 817 
 818                 ori     r4, r4, _PAGE_ACCESSED
 819                 swi     r4, r5, 0
 820 
 821                 /* Most of the Linux PTE is ready to load into the TLB LO.
 822                  * We set ZSEL, where only the LS-bit determines user access.
 823                  * We set execute, because we don't have the granularity to
 824                  * properly set this at the page level (Linux problem).
 825                  * If shared is set, we cause a zero PID->TID load.
 826                  * Many of these bits are software only. Bits we don't set
 827                  * here we (properly should) assume have the appropriate value.
 828                  */
 829                 brid    finish_tlb_load
 830                 andi    r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
 831                                                 TLB_ZSEL(1) | TLB_ATTR_MASK
 832         ex10:
 833                 /* The bailout. Restore registers to pre-exception conditions
 834                  * and call the heavyweights to help us out.
 835                  */
 836                 mts     rpid, r11
 837                 nop
 838                 bri 4
 839                 RESTORE_STATE;
 840                 bri     page_fault_instr_trap
 841 
 842 /* Both the instruction and data TLB miss get to this point to load the TLB.
 843  *      r3 - EA of fault
 844  *      r4 - TLB LO (info from Linux PTE)
 845  *      r5, r6 - available to use
 846  *      PID - loaded with proper value when we get here
 847  *      Upon exit, we reload everything and RFI.
 848  * A common place to load the TLB.
 849  */
 850 .section .data
 851 .align 4
 852 .global tlb_skip
 853         tlb_skip:
 854                 .long   MICROBLAZE_TLB_SKIP
 855         tlb_index:
 856                 /* MS: storing last used tlb index */
 857                 .long   MICROBLAZE_TLB_SIZE/2
 858 .previous
 859         finish_tlb_load:
 860                 /* MS: load the last used TLB index. */
 861                 lwi     r5, r0, TOPHYS(tlb_index)
 862                 addik   r5, r5, 1 /* MS: inc tlb_index -> use next one */
 863 
 864 /* MS: FIXME this is potential fault, because this is mask not count */
 865                 andi    r5, r5, MICROBLAZE_TLB_SIZE - 1
 866                 ori     r6, r0, 1
 867                 cmp     r31, r5, r6
 868                 blti    r31, ex12
 869                 lwi     r5, r0, TOPHYS(tlb_skip)
 870         ex12:
 871                 /* MS: save back current TLB index */
 872                 swi     r5, r0, TOPHYS(tlb_index)
 873 
 874                 ori     r4, r4, _PAGE_HWEXEC    /* make it executable */
 875                 mts     rtlbx, r5               /* MS: save current TLB */
 876                 nop
 877                 mts     rtlblo, r4              /* MS: save to TLB LO */
 878                 nop
 879 
 880                 /* Create EPN. This is the faulting address plus a static
 881                  * set of bits. These are size, valid, E, U0, and ensure
 882                  * bits 20 and 21 are zero.
 883                  */
 884                 andi    r3, r3, PAGE_MASK
 885 #ifdef CONFIG_MICROBLAZE_64K_PAGES
 886                 ori     r3, r3, TLB_VALID | TLB_PAGESZ(PAGESZ_64K)
 887 #elif CONFIG_MICROBLAZE_16K_PAGES
 888                 ori     r3, r3, TLB_VALID | TLB_PAGESZ(PAGESZ_16K)
 889 #else
 890                 ori     r3, r3, TLB_VALID | TLB_PAGESZ(PAGESZ_4K)
 891 #endif
 892                 mts     rtlbhi, r3              /* Load TLB HI */
 893                 nop
 894 
 895                 /* Done...restore registers and get out of here. */
 896                 mts     rpid, r11
 897                 nop
 898                 bri 4
 899                 RESTORE_STATE;
 900                 rted    r17, 0
 901                 nop
 902 
 903         /* extern void giveup_fpu(struct task_struct *prev)
 904          *
 905          * The MicroBlaze processor may have an FPU, so this should not just
 906          * return: TBD.
 907          */
 908         .globl giveup_fpu;
 909         .align 4;
 910         giveup_fpu:
 911                 bralid  r15,0                   /* TBD */
 912                 nop
 913 
 914         /* At present, this routine just hangs. - extern void abort(void) */
 915         .globl abort;
 916         .align 4;
 917         abort:
 918                 br      r0
 919 
 920         .globl set_context;
 921         .align 4;
 922         set_context:
 923                 mts     rpid, r5        /* Shadow TLBs are automatically */
 924                 nop
 925                 bri     4               /* flushed by changing PID */
 926                 rtsd    r15,8
 927                 nop
 928 
 929 #endif
 930 .end _hw_exception_handler
 931 
 932 #ifdef CONFIG_MMU
 933 /* Unaligned data access exception last on a 4k page for MMU.
 934  * When this is called, we are in virtual mode with exceptions enabled
 935  * and registers 1-13,15,17,18 saved.
 936  *
 937  * R3 = ESR
 938  * R4 = EAR
 939  * R7 = pointer to saved registers (struct pt_regs *regs)
 940  *
 941  * This handler perform the access, and returns via ret_from_exc.
 942  */
 943 .global _unaligned_data_exception
 944 .ent _unaligned_data_exception
 945 _unaligned_data_exception:
 946         andi    r8, r3, 0x3E0;  /* Mask and extract the register operand */
 947         bsrli   r8, r8, 2;              /* r8 >> 2 = register operand * 8 */
 948         andi    r6, r3, 0x400;  /* Extract ESR[S] */
 949         bneid   r6, ex_sw_vm;
 950         andi    r6, r3, 0x800;  /* Extract ESR[W] - delay slot */
 951 ex_lw_vm:
 952         beqid   r6, ex_lhw_vm;
 953 load1:  lbui    r5, r4, 0;      /* Exception address in r4 - delay slot */
 954 /* Load a word, byte-by-byte from destination address and save it in tmp space*/
 955         addik   r6, r0, ex_tmp_data_loc_0;
 956         sbi     r5, r6, 0;
 957 load2:  lbui    r5, r4, 1;
 958         sbi     r5, r6, 1;
 959 load3:  lbui    r5, r4, 2;
 960         sbi     r5, r6, 2;
 961 load4:  lbui    r5, r4, 3;
 962         sbi     r5, r6, 3;
 963         brid    ex_lw_tail_vm;
 964 /* Get the destination register value into r3 - delay slot */
 965         lwi     r3, r6, 0;
 966 ex_lhw_vm:
 967         /* Load a half-word, byte-by-byte from destination address and
 968          * save it in tmp space */
 969         addik   r6, r0, ex_tmp_data_loc_0;
 970         sbi     r5, r6, 0;
 971 load5:  lbui    r5, r4, 1;
 972         sbi     r5, r6, 1;
 973         lhui    r3, r6, 0;      /* Get the destination register value into r3 */
 974 ex_lw_tail_vm:
 975         /* Form load_word jump table offset (lw_table_vm + (8 * regnum)) */
 976         addik   r5, r8, lw_table_vm;
 977         bra     r5;
 978 ex_lw_end_vm:                   /* Exception handling of load word, ends */
 979         brai    ret_from_exc;
 980 ex_sw_vm:
 981 /* Form store_word jump table offset (sw_table_vm + (8 * regnum)) */
 982         addik   r5, r8, sw_table_vm;
 983         bra     r5;
 984 ex_sw_tail_vm:
 985         addik   r5, r0, ex_tmp_data_loc_0;
 986         beqid   r6, ex_shw_vm;
 987         swi     r3, r5, 0;      /* Get the word - delay slot */
 988         /* Store the word, byte-by-byte into destination address */
 989         lbui    r3, r5, 0;
 990 store1: sbi     r3, r4, 0;
 991         lbui    r3, r5, 1;
 992 store2: sbi     r3, r4, 1;
 993         lbui    r3, r5, 2;
 994 store3: sbi     r3, r4, 2;
 995         lbui    r3, r5, 3;
 996         brid    ret_from_exc;
 997 store4: sbi     r3, r4, 3;      /* Delay slot */
 998 ex_shw_vm:
 999         /* Store the lower half-word, byte-by-byte into destination address */
1000 #ifdef __MICROBLAZEEL__
1001         lbui    r3, r5, 0;
1002 store5: sbi     r3, r4, 0;
1003         lbui    r3, r5, 1;
1004         brid    ret_from_exc;
1005 store6: sbi     r3, r4, 1;      /* Delay slot */
1006 #else
1007         lbui    r3, r5, 2;
1008 store5: sbi     r3, r4, 0;
1009         lbui    r3, r5, 3;
1010         brid    ret_from_exc;
1011 store6: sbi     r3, r4, 1;      /* Delay slot */
1012 #endif
1013 
1014 ex_sw_end_vm:                   /* Exception handling of store word, ends. */
1015 
1016 /* We have to prevent cases that get/put_user macros get unaligned pointer
1017  * to bad page area. We have to find out which origin instruction caused it
1018  * and called fixup for that origin instruction not instruction in unaligned
1019  * handler */
1020 ex_unaligned_fixup:
1021         ori     r5, r7, 0 /* setup pointer to pt_regs */
1022         lwi     r6, r7, PT_PC; /* faulting address is one instruction above */
1023         addik   r6, r6, -4 /* for finding proper fixup */
1024         swi     r6, r7, PT_PC; /* a save back it to PT_PC */
1025         addik   r7, r0, SIGSEGV
1026         /* call bad_page_fault for finding aligned fixup, fixup address is saved
1027          * in PT_PC which is used as return address from exception */
1028         addik   r15, r0, ret_from_exc-8 /* setup return address */
1029         brid    bad_page_fault
1030         nop
1031 
1032 /* We prevent all load/store because it could failed any attempt to access */
1033 .section __ex_table,"a";
1034         .word   load1,ex_unaligned_fixup;
1035         .word   load2,ex_unaligned_fixup;
1036         .word   load3,ex_unaligned_fixup;
1037         .word   load4,ex_unaligned_fixup;
1038         .word   load5,ex_unaligned_fixup;
1039         .word   store1,ex_unaligned_fixup;
1040         .word   store2,ex_unaligned_fixup;
1041         .word   store3,ex_unaligned_fixup;
1042         .word   store4,ex_unaligned_fixup;
1043         .word   store5,ex_unaligned_fixup;
1044         .word   store6,ex_unaligned_fixup;
1045 .previous;
1046 .end _unaligned_data_exception
1047 #endif /* CONFIG_MMU */
1048 
1049 .global ex_handler_unhandled
1050 ex_handler_unhandled:
1051 /* FIXME add handle function for unhandled exception - dump register */
1052         bri 0
1053 
1054 /*
1055  * hw_exception_handler Jump Table
1056  * - Contains code snippets for each register that caused the unalign exception
1057  * - Hence exception handler is NOT self-modifying
1058  * - Separate table for load exceptions and store exceptions.
1059  * - Each table is of size: (8 * 32) = 256 bytes
1060  */
1061 
1062 .section .text
1063 .align 4
1064 lw_table:
1065 lw_r0:          R3_TO_LWREG     (0);
1066 lw_r1:          LWREG_NOP;
1067 lw_r2:          R3_TO_LWREG     (2);
1068 lw_r3:          R3_TO_LWREG_V   (3);
1069 lw_r4:          R3_TO_LWREG_V   (4);
1070 lw_r5:          R3_TO_LWREG_V   (5);
1071 lw_r6:          R3_TO_LWREG_V   (6);
1072 lw_r7:          R3_TO_LWREG     (7);
1073 lw_r8:          R3_TO_LWREG     (8);
1074 lw_r9:          R3_TO_LWREG     (9);
1075 lw_r10:         R3_TO_LWREG     (10);
1076 lw_r11:         R3_TO_LWREG     (11);
1077 lw_r12:         R3_TO_LWREG     (12);
1078 lw_r13:         R3_TO_LWREG     (13);
1079 lw_r14:         R3_TO_LWREG     (14);
1080 lw_r15:         R3_TO_LWREG     (15);
1081 lw_r16:         R3_TO_LWREG     (16);
1082 lw_r17:         LWREG_NOP;
1083 lw_r18:         R3_TO_LWREG     (18);
1084 lw_r19:         R3_TO_LWREG     (19);
1085 lw_r20:         R3_TO_LWREG     (20);
1086 lw_r21:         R3_TO_LWREG     (21);
1087 lw_r22:         R3_TO_LWREG     (22);
1088 lw_r23:         R3_TO_LWREG     (23);
1089 lw_r24:         R3_TO_LWREG     (24);
1090 lw_r25:         R3_TO_LWREG     (25);
1091 lw_r26:         R3_TO_LWREG     (26);
1092 lw_r27:         R3_TO_LWREG     (27);
1093 lw_r28:         R3_TO_LWREG     (28);
1094 lw_r29:         R3_TO_LWREG     (29);
1095 lw_r30:         R3_TO_LWREG     (30);
1096 #ifdef CONFIG_MMU
1097 lw_r31:         R3_TO_LWREG_V   (31);
1098 #else
1099 lw_r31:         R3_TO_LWREG     (31);
1100 #endif
1101 
1102 sw_table:
1103 sw_r0:          SWREG_TO_R3     (0);
1104 sw_r1:          SWREG_NOP;
1105 sw_r2:          SWREG_TO_R3     (2);
1106 sw_r3:          SWREG_TO_R3_V   (3);
1107 sw_r4:          SWREG_TO_R3_V   (4);
1108 sw_r5:          SWREG_TO_R3_V   (5);
1109 sw_r6:          SWREG_TO_R3_V   (6);
1110 sw_r7:          SWREG_TO_R3     (7);
1111 sw_r8:          SWREG_TO_R3     (8);
1112 sw_r9:          SWREG_TO_R3     (9);
1113 sw_r10:         SWREG_TO_R3     (10);
1114 sw_r11:         SWREG_TO_R3     (11);
1115 sw_r12:         SWREG_TO_R3     (12);
1116 sw_r13:         SWREG_TO_R3     (13);
1117 sw_r14:         SWREG_TO_R3     (14);
1118 sw_r15:         SWREG_TO_R3     (15);
1119 sw_r16:         SWREG_TO_R3     (16);
1120 sw_r17:         SWREG_NOP;
1121 sw_r18:         SWREG_TO_R3     (18);
1122 sw_r19:         SWREG_TO_R3     (19);
1123 sw_r20:         SWREG_TO_R3     (20);
1124 sw_r21:         SWREG_TO_R3     (21);
1125 sw_r22:         SWREG_TO_R3     (22);
1126 sw_r23:         SWREG_TO_R3     (23);
1127 sw_r24:         SWREG_TO_R3     (24);
1128 sw_r25:         SWREG_TO_R3     (25);
1129 sw_r26:         SWREG_TO_R3     (26);
1130 sw_r27:         SWREG_TO_R3     (27);
1131 sw_r28:         SWREG_TO_R3     (28);
1132 sw_r29:         SWREG_TO_R3     (29);
1133 sw_r30:         SWREG_TO_R3     (30);
1134 #ifdef CONFIG_MMU
1135 sw_r31:         SWREG_TO_R3_V   (31);
1136 #else
1137 sw_r31:         SWREG_TO_R3     (31);
1138 #endif
1139 
1140 #ifdef CONFIG_MMU
1141 lw_table_vm:
1142 lw_r0_vm:       R3_TO_LWREG_VM          (0);
1143 lw_r1_vm:       R3_TO_LWREG_VM_V        (1);
1144 lw_r2_vm:       R3_TO_LWREG_VM_V        (2);
1145 lw_r3_vm:       R3_TO_LWREG_VM_V        (3);
1146 lw_r4_vm:       R3_TO_LWREG_VM_V        (4);
1147 lw_r5_vm:       R3_TO_LWREG_VM_V        (5);
1148 lw_r6_vm:       R3_TO_LWREG_VM_V        (6);
1149 lw_r7_vm:       R3_TO_LWREG_VM_V        (7);
1150 lw_r8_vm:       R3_TO_LWREG_VM_V        (8);
1151 lw_r9_vm:       R3_TO_LWREG_VM_V        (9);
1152 lw_r10_vm:      R3_TO_LWREG_VM_V        (10);
1153 lw_r11_vm:      R3_TO_LWREG_VM_V        (11);
1154 lw_r12_vm:      R3_TO_LWREG_VM_V        (12);
1155 lw_r13_vm:      R3_TO_LWREG_VM_V        (13);
1156 lw_r14_vm:      R3_TO_LWREG_VM_V        (14);
1157 lw_r15_vm:      R3_TO_LWREG_VM_V        (15);
1158 lw_r16_vm:      R3_TO_LWREG_VM_V        (16);
1159 lw_r17_vm:      R3_TO_LWREG_VM_V        (17);
1160 lw_r18_vm:      R3_TO_LWREG_VM_V        (18);
1161 lw_r19_vm:      R3_TO_LWREG_VM_V        (19);
1162 lw_r20_vm:      R3_TO_LWREG_VM_V        (20);
1163 lw_r21_vm:      R3_TO_LWREG_VM_V        (21);
1164 lw_r22_vm:      R3_TO_LWREG_VM_V        (22);
1165 lw_r23_vm:      R3_TO_LWREG_VM_V        (23);
1166 lw_r24_vm:      R3_TO_LWREG_VM_V        (24);
1167 lw_r25_vm:      R3_TO_LWREG_VM_V        (25);
1168 lw_r26_vm:      R3_TO_LWREG_VM_V        (26);
1169 lw_r27_vm:      R3_TO_LWREG_VM_V        (27);
1170 lw_r28_vm:      R3_TO_LWREG_VM_V        (28);
1171 lw_r29_vm:      R3_TO_LWREG_VM_V        (29);
1172 lw_r30_vm:      R3_TO_LWREG_VM_V        (30);
1173 lw_r31_vm:      R3_TO_LWREG_VM_V        (31);
1174 
1175 sw_table_vm:
1176 sw_r0_vm:       SWREG_TO_R3_VM          (0);
1177 sw_r1_vm:       SWREG_TO_R3_VM_V        (1);
1178 sw_r2_vm:       SWREG_TO_R3_VM_V        (2);
1179 sw_r3_vm:       SWREG_TO_R3_VM_V        (3);
1180 sw_r4_vm:       SWREG_TO_R3_VM_V        (4);
1181 sw_r5_vm:       SWREG_TO_R3_VM_V        (5);
1182 sw_r6_vm:       SWREG_TO_R3_VM_V        (6);
1183 sw_r7_vm:       SWREG_TO_R3_VM_V        (7);
1184 sw_r8_vm:       SWREG_TO_R3_VM_V        (8);
1185 sw_r9_vm:       SWREG_TO_R3_VM_V        (9);
1186 sw_r10_vm:      SWREG_TO_R3_VM_V        (10);
1187 sw_r11_vm:      SWREG_TO_R3_VM_V        (11);
1188 sw_r12_vm:      SWREG_TO_R3_VM_V        (12);
1189 sw_r13_vm:      SWREG_TO_R3_VM_V        (13);
1190 sw_r14_vm:      SWREG_TO_R3_VM_V        (14);
1191 sw_r15_vm:      SWREG_TO_R3_VM_V        (15);
1192 sw_r16_vm:      SWREG_TO_R3_VM_V        (16);
1193 sw_r17_vm:      SWREG_TO_R3_VM_V        (17);
1194 sw_r18_vm:      SWREG_TO_R3_VM_V        (18);
1195 sw_r19_vm:      SWREG_TO_R3_VM_V        (19);
1196 sw_r20_vm:      SWREG_TO_R3_VM_V        (20);
1197 sw_r21_vm:      SWREG_TO_R3_VM_V        (21);
1198 sw_r22_vm:      SWREG_TO_R3_VM_V        (22);
1199 sw_r23_vm:      SWREG_TO_R3_VM_V        (23);
1200 sw_r24_vm:      SWREG_TO_R3_VM_V        (24);
1201 sw_r25_vm:      SWREG_TO_R3_VM_V        (25);
1202 sw_r26_vm:      SWREG_TO_R3_VM_V        (26);
1203 sw_r27_vm:      SWREG_TO_R3_VM_V        (27);
1204 sw_r28_vm:      SWREG_TO_R3_VM_V        (28);
1205 sw_r29_vm:      SWREG_TO_R3_VM_V        (29);
1206 sw_r30_vm:      SWREG_TO_R3_VM_V        (30);
1207 sw_r31_vm:      SWREG_TO_R3_VM_V        (31);
1208 #endif /* CONFIG_MMU */
1209 
1210 /* Temporary data structures used in the handler */
1211 .section .data
1212 .align 4
1213 ex_tmp_data_loc_0:
1214         .byte 0
1215 ex_tmp_data_loc_1:
1216         .byte 0
1217 ex_tmp_data_loc_2:
1218         .byte 0
1219 ex_tmp_data_loc_3:
1220         .byte 0
1221 ex_reg_op:
1222         .byte 0
/* [<][>][^][v][top][bottom][index][help] */
root/arch/microblaze/kernel/hw_exception_handler.S
