1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2016 Cavium, Inc.
4 */
5
6 #ifndef __CPT_HW_TYPES_H
7 #define __CPT_HW_TYPES_H
8
9 #include "cpt_common.h"
10
11 /**
12 * Enumeration cpt_comp_e
13 *
14 * CPT Completion Enumeration
15 * Enumerates the values of CPT_RES_S[COMPCODE].
16 */
17 enum cpt_comp_e {
18 CPT_COMP_E_NOTDONE = 0x00,
19 CPT_COMP_E_GOOD = 0x01,
20 CPT_COMP_E_FAULT = 0x02,
21 CPT_COMP_E_SWERR = 0x03,
22 CPT_COMP_E_LAST_ENTRY = 0xFF
23 };
24
25 /**
26 * Structure cpt_inst_s
27 *
28 * CPT Instruction Structure
29 * This structure specifies the instruction layout. Instructions are
30 * stored in memory as little-endian unless CPT()_PF_Q()_CTL[INST_BE] is set.
31 * cpt_inst_s_s
32 * Word 0
33 * doneint:1 Done interrupt.
34 * 0 = No interrupts related to this instruction.
35 * 1 = When the instruction completes, CPT()_VQ()_DONE[DONE] will be
36 * incremented,and based on the rules described there an interrupt may
37 * occur.
38 * Word 1
39 * res_addr [127: 64] Result IOVA.
40 * If nonzero, specifies where to write CPT_RES_S.
41 * If zero, no result structure will be written.
42 * Address must be 16-byte aligned.
43 * Bits <63:49> are ignored by hardware; software should use a
44 * sign-extended bit <48> for forward compatibility.
45 * Word 2
46 * grp:10 [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to use when
47 * CPT submits work SSO.
48 * For the SSO to not discard the add-work request, FPA_PF_MAP() must map
49 * [GRP] and CPT()_PF_Q()_GMCTL[GMID] as valid.
50 * tt:2 [161:160] If [WQ_PTR] is nonzero, the SSO tag type to use when CPT
51 * submits work to SSO
52 * tag:32 [159:128] If [WQ_PTR] is nonzero, the SSO tag to use when CPT
53 * submits work to SSO.
54 * Word 3
55 * wq_ptr [255:192] If [WQ_PTR] is nonzero, it is a pointer to a
56 * work-queue entry that CPT submits work to SSO after all context,
57 * output data, and result write operations are visible to other
58 * CNXXXX units and the cores. Bits <2:0> must be zero.
59 * Bits <63:49> are ignored by hardware; software should
60 * use a sign-extended bit <48> for forward compatibility.
61 * Internal:
62 * Bits <63:49>, <2:0> are ignored by hardware, treated as always 0x0.
63 * Word 4
64 * ei0; [319:256] Engine instruction word 0. Passed to the AE/SE.
65 * Word 5
66 * ei1; [383:320] Engine instruction word 1. Passed to the AE/SE.
67 * Word 6
68 * ei2; [447:384] Engine instruction word 1. Passed to the AE/SE.
69 * Word 7
70 * ei3; [511:448] Engine instruction word 1. Passed to the AE/SE.
71 *
72 */
73 union cpt_inst_s {
74 u64 u[8];
75 struct cpt_inst_s_s {
76 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
77 u64 reserved_17_63:47;
78 u64 doneint:1;
79 u64 reserved_0_1:16;
80 #else /* Word 0 - Little Endian */
81 u64 reserved_0_15:16;
82 u64 doneint:1;
83 u64 reserved_17_63:47;
84 #endif /* Word 0 - End */
85 u64 res_addr;
86 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 2 - Big Endian */
87 u64 reserved_172_19:20;
88 u64 grp:10;
89 u64 tt:2;
90 u64 tag:32;
91 #else /* Word 2 - Little Endian */
92 u64 tag:32;
93 u64 tt:2;
94 u64 grp:10;
95 u64 reserved_172_191:20;
96 #endif /* Word 2 - End */
97 u64 wq_ptr;
98 u64 ei0;
99 u64 ei1;
100 u64 ei2;
101 u64 ei3;
102 } s;
103 };
104
105 /**
106 * Structure cpt_res_s
107 *
108 * CPT Result Structure
109 * The CPT coprocessor writes the result structure after it completes a
110 * CPT_INST_S instruction. The result structure is exactly 16 bytes, and
111 * each instruction completion produces exactly one result structure.
112 *
113 * This structure is stored in memory as little-endian unless
114 * CPT()_PF_Q()_CTL[INST_BE] is set.
115 * cpt_res_s_s
116 * Word 0
117 * doneint:1 [16:16] Done interrupt. This bit is copied from the
118 * corresponding instruction's CPT_INST_S[DONEINT].
119 * compcode:8 [7:0] Indicates completion/error status of the CPT coprocessor
120 * for the associated instruction, as enumerated by CPT_COMP_E.
121 * Core software may write the memory location containing [COMPCODE] to
122 * 0x0 before ringing the doorbell, and then poll for completion by
123 * checking for a nonzero value.
124 * Once the core observes a nonzero [COMPCODE] value in this case,the CPT
125 * coprocessor will have also completed L2/DRAM write operations.
126 * Word 1
127 * reserved
128 *
129 */
130 union cpt_res_s {
131 u64 u[2];
132 struct cpt_res_s_s {
133 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
134 u64 reserved_17_63:47;
135 u64 doneint:1;
136 u64 reserved_8_15:8;
137 u64 compcode:8;
138 #else /* Word 0 - Little Endian */
139 u64 compcode:8;
140 u64 reserved_8_15:8;
141 u64 doneint:1;
142 u64 reserved_17_63:47;
143 #endif /* Word 0 - End */
144 u64 reserved_64_127;
145 } s;
146 };
147
148 /**
149 * Register (NCB) cpt#_pf_bist_status
150 *
151 * CPT PF Control Bist Status Register
152 * This register has the BIST status of memories. Each bit is the BIST result
153 * of an individual memory (per bit, 0 = pass and 1 = fail).
154 * cptx_pf_bist_status_s
155 * Word0
156 * bstatus [29:0](RO/H) BIST status. One bit per memory, enumerated by
157 * CPT_RAMS_E.
158 */
159 union cptx_pf_bist_status {
160 u64 u;
161 struct cptx_pf_bist_status_s {
162 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
163 u64 reserved_30_63:34;
164 u64 bstatus:30;
165 #else /* Word 0 - Little Endian */
166 u64 bstatus:30;
167 u64 reserved_30_63:34;
168 #endif /* Word 0 - End */
169 } s;
170 };
171
172 /**
173 * Register (NCB) cpt#_pf_constants
174 *
175 * CPT PF Constants Register
176 * This register contains implementation-related parameters of CPT in CNXXXX.
177 * cptx_pf_constants_s
178 * Word 0
179 * reserved_40_63:24 [63:40] Reserved.
180 * epcis:8 [39:32](RO) Number of EPCI busses.
181 * grps:8 [31:24](RO) Number of engine groups implemented.
182 * ae:8 [23:16](RO/H) Number of AEs. In CNXXXX, for CPT0 returns 0x0,
183 * for CPT1 returns 0x18, or less if there are fuse-disables.
184 * se:8 [15:8](RO/H) Number of SEs. In CNXXXX, for CPT0 returns 0x30,
185 * or less if there are fuse-disables, for CPT1 returns 0x0.
186 * vq:8 [7:0](RO) Number of VQs.
187 */
188 union cptx_pf_constants {
189 u64 u;
190 struct cptx_pf_constants_s {
191 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
192 u64 reserved_40_63:24;
193 u64 epcis:8;
194 u64 grps:8;
195 u64 ae:8;
196 u64 se:8;
197 u64 vq:8;
198 #else /* Word 0 - Little Endian */
199 u64 vq:8;
200 u64 se:8;
201 u64 ae:8;
202 u64 grps:8;
203 u64 epcis:8;
204 u64 reserved_40_63:24;
205 #endif /* Word 0 - End */
206 } s;
207 };
208
209 /**
210 * Register (NCB) cpt#_pf_exe_bist_status
211 *
212 * CPT PF Engine Bist Status Register
213 * This register has the BIST status of each engine. Each bit is the
214 * BIST result of an individual engine (per bit, 0 = pass and 1 = fail).
215 * cptx_pf_exe_bist_status_s
216 * Word0
217 * reserved_48_63:16 [63:48] reserved
218 * bstatus:48 [47:0](RO/H) BIST status. One bit per engine.
219 *
220 */
221 union cptx_pf_exe_bist_status {
222 u64 u;
223 struct cptx_pf_exe_bist_status_s {
224 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
225 u64 reserved_48_63:16;
226 u64 bstatus:48;
227 #else /* Word 0 - Little Endian */
228 u64 bstatus:48;
229 u64 reserved_48_63:16;
230 #endif /* Word 0 - End */
231 } s;
232 };
233
234 /**
235 * Register (NCB) cpt#_pf_q#_ctl
236 *
237 * CPT Queue Control Register
238 * This register configures queues. This register should be changed only
239 * when quiescent (see CPT()_VQ()_INPROG[INFLIGHT]).
240 * cptx_pf_qx_ctl_s
241 * Word0
242 * reserved_60_63:4 [63:60] reserved.
243 * aura:12; [59:48](R/W) Guest-aura for returning this queue's
244 * instruction-chunk buffers to FPA. Only used when [INST_FREE] is set.
245 * For the FPA to not discard the request, FPA_PF_MAP() must map
246 * [AURA] and CPT()_PF_Q()_GMCTL[GMID] as valid.
247 * reserved_45_47:3 [47:45] reserved.
248 * size:13 [44:32](R/W) Command-buffer size, in number of 64-bit words per
249 * command buffer segment. Must be 8*n + 1, where n is the number of
250 * instructions per buffer segment.
251 * reserved_11_31:21 [31:11] Reserved.
252 * cont_err:1 [10:10](R/W) Continue on error.
253 * 0 = When CPT()_VQ()_MISC_INT[NWRP], CPT()_VQ()_MISC_INT[IRDE] or
254 * CPT()_VQ()_MISC_INT[DOVF] are set by hardware or software via
255 * CPT()_VQ()_MISC_INT_W1S, then CPT()_VQ()_CTL[ENA] is cleared. Due to
256 * pipelining, additional instructions may have been processed between the
257 * instruction causing the error and the next instruction in the disabled
258 * queue (the instruction at CPT()_VQ()_SADDR).
259 * 1 = Ignore errors and continue processing instructions.
260 * For diagnostic use only.
261 * inst_free:1 [9:9](R/W) Instruction FPA free. When set, when CPT reaches the
262 * end of an instruction chunk, that chunk will be freed to the FPA.
263 * inst_be:1 [8:8](R/W) Instruction big-endian control. When set, instructions,
264 * instruction next chunk pointers, and result structures are stored in
265 * big-endian format in memory.
266 * iqb_ldwb:1 [7:7](R/W) Instruction load don't write back.
267 * 0 = The hardware issues NCB transient load (LDT) towards the cache,
268 * which if the line hits and is is dirty will cause the line to be
269 * written back before being replaced.
270 * 1 = The hardware issues NCB LDWB read-and-invalidate command towards
271 * the cache when fetching the last word of instructions; as a result the
272 * line will not be written back when replaced. This improves
273 * performance, but software must not read the instructions after they are
274 * posted to the hardware. Reads that do not consume the last word of a
275 * cache line always use LDI.
276 * reserved_4_6:3 [6:4] Reserved.
277 * grp:3; [3:1](R/W) Engine group.
278 * pri:1; [0:0](R/W) Queue priority.
279 * 1 = This queue has higher priority. Round-robin between higher
280 * priority queues.
281 * 0 = This queue has lower priority. Round-robin between lower
282 * priority queues.
283 */
284 union cptx_pf_qx_ctl {
285 u64 u;
286 struct cptx_pf_qx_ctl_s {
287 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
288 u64 reserved_60_63:4;
289 u64 aura:12;
290 u64 reserved_45_47:3;
291 u64 size:13;
292 u64 reserved_11_31:21;
293 u64 cont_err:1;
294 u64 inst_free:1;
295 u64 inst_be:1;
296 u64 iqb_ldwb:1;
297 u64 reserved_4_6:3;
298 u64 grp:3;
299 u64 pri:1;
300 #else /* Word 0 - Little Endian */
301 u64 pri:1;
302 u64 grp:3;
303 u64 reserved_4_6:3;
304 u64 iqb_ldwb:1;
305 u64 inst_be:1;
306 u64 inst_free:1;
307 u64 cont_err:1;
308 u64 reserved_11_31:21;
309 u64 size:13;
310 u64 reserved_45_47:3;
311 u64 aura:12;
312 u64 reserved_60_63:4;
313 #endif /* Word 0 - End */
314 } s;
315 };
316
317 /**
318 * Register (NCB) cpt#_vq#_saddr
319 *
320 * CPT Queue Starting Buffer Address Registers
321 * These registers set the instruction buffer starting address.
322 * cptx_vqx_saddr_s
323 * Word0
324 * reserved_49_63:15 [63:49] Reserved.
325 * ptr:43 [48:6](R/W/H) Instruction buffer IOVA <48:6> (64-byte aligned).
326 * When written, it is the initial buffer starting address; when read,
327 * it is the next read pointer to be requested from L2C. The PTR field
328 * is overwritten with the next pointer each time that the command buffer
329 * segment is exhausted. New commands will then be read from the newly
330 * specified command buffer pointer.
331 * reserved_0_5:6 [5:0] Reserved.
332 *
333 */
334 union cptx_vqx_saddr {
335 u64 u;
336 struct cptx_vqx_saddr_s {
337 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
338 u64 reserved_49_63:15;
339 u64 ptr:43;
340 u64 reserved_0_5:6;
341 #else /* Word 0 - Little Endian */
342 u64 reserved_0_5:6;
343 u64 ptr:43;
344 u64 reserved_49_63:15;
345 #endif /* Word 0 - End */
346 } s;
347 };
348
349 /**
350 * Register (NCB) cpt#_vq#_misc_ena_w1s
351 *
352 * CPT Queue Misc Interrupt Enable Set Register
353 * This register sets interrupt enable bits.
354 * cptx_vqx_misc_ena_w1s_s
355 * Word0
356 * reserved_5_63:59 [63:5] Reserved.
357 * swerr:1 [4:4](R/W1S/H) Reads or sets enable for
358 * CPT(0..1)_VQ(0..63)_MISC_INT[SWERR].
359 * nwrp:1 [3:3](R/W1S/H) Reads or sets enable for
360 * CPT(0..1)_VQ(0..63)_MISC_INT[NWRP].
361 * irde:1 [2:2](R/W1S/H) Reads or sets enable for
362 * CPT(0..1)_VQ(0..63)_MISC_INT[IRDE].
363 * dovf:1 [1:1](R/W1S/H) Reads or sets enable for
364 * CPT(0..1)_VQ(0..63)_MISC_INT[DOVF].
365 * mbox:1 [0:0](R/W1S/H) Reads or sets enable for
366 * CPT(0..1)_VQ(0..63)_MISC_INT[MBOX].
367 *
368 */
369 union cptx_vqx_misc_ena_w1s {
370 u64 u;
371 struct cptx_vqx_misc_ena_w1s_s {
372 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
373 u64 reserved_5_63:59;
374 u64 swerr:1;
375 u64 nwrp:1;
376 u64 irde:1;
377 u64 dovf:1;
378 u64 mbox:1;
379 #else /* Word 0 - Little Endian */
380 u64 mbox:1;
381 u64 dovf:1;
382 u64 irde:1;
383 u64 nwrp:1;
384 u64 swerr:1;
385 u64 reserved_5_63:59;
386 #endif /* Word 0 - End */
387 } s;
388 };
389
390 /**
391 * Register (NCB) cpt#_vq#_doorbell
392 *
393 * CPT Queue Doorbell Registers
394 * Doorbells for the CPT instruction queues.
395 * cptx_vqx_doorbell_s
396 * Word0
397 * reserved_20_63:44 [63:20] Reserved.
398 * dbell_cnt:20 [19:0](R/W/H) Number of instruction queue 64-bit words to add
399 * to the CPT instruction doorbell count. Readback value is the the
400 * current number of pending doorbell requests. If counter overflows
401 * CPT()_VQ()_MISC_INT[DBELL_DOVF] is set. To reset the count back to
402 * zero, write one to clear CPT()_VQ()_MISC_INT_ENA_W1C[DBELL_DOVF],
403 * then write a value of 2^20 minus the read [DBELL_CNT], then write one
404 * to CPT()_VQ()_MISC_INT_W1C[DBELL_DOVF] and
405 * CPT()_VQ()_MISC_INT_ENA_W1S[DBELL_DOVF]. Must be a multiple of 8.
406 * All CPT instructions are 8 words and require a doorbell count of
407 * multiple of 8.
408 */
409 union cptx_vqx_doorbell {
410 u64 u;
411 struct cptx_vqx_doorbell_s {
412 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
413 u64 reserved_20_63:44;
414 u64 dbell_cnt:20;
415 #else /* Word 0 - Little Endian */
416 u64 dbell_cnt:20;
417 u64 reserved_20_63:44;
418 #endif /* Word 0 - End */
419 } s;
420 };
421
422 /**
423 * Register (NCB) cpt#_vq#_inprog
424 *
425 * CPT Queue In Progress Count Registers
426 * These registers contain the per-queue instruction in flight registers.
427 * cptx_vqx_inprog_s
428 * Word0
429 * reserved_8_63:56 [63:8] Reserved.
430 * inflight:8 [7:0](RO/H) Inflight count. Counts the number of instructions
431 * for the VF for which CPT is fetching, executing or responding to
432 * instructions. However this does not include any interrupts that are
433 * awaiting software handling (CPT()_VQ()_DONE[DONE] != 0x0).
434 * A queue may not be reconfigured until:
435 * 1. CPT()_VQ()_CTL[ENA] is cleared by software.
436 * 2. [INFLIGHT] is polled until equals to zero.
437 */
438 union cptx_vqx_inprog {
439 u64 u;
440 struct cptx_vqx_inprog_s {
441 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
442 u64 reserved_8_63:56;
443 u64 inflight:8;
444 #else /* Word 0 - Little Endian */
445 u64 inflight:8;
446 u64 reserved_8_63:56;
447 #endif /* Word 0 - End */
448 } s;
449 };
450
451 /**
452 * Register (NCB) cpt#_vq#_misc_int
453 *
454 * CPT Queue Misc Interrupt Register
455 * These registers contain the per-queue miscellaneous interrupts.
456 * cptx_vqx_misc_int_s
457 * Word 0
458 * reserved_5_63:59 [63:5] Reserved.
459 * swerr:1 [4:4](R/W1C/H) Software error from engines.
460 * nwrp:1 [3:3](R/W1C/H) NCB result write response error.
461 * irde:1 [2:2](R/W1C/H) Instruction NCB read response error.
462 * dovf:1 [1:1](R/W1C/H) Doorbell overflow.
463 * mbox:1 [0:0](R/W1C/H) PF to VF mailbox interrupt. Set when
464 * CPT()_VF()_PF_MBOX(0) is written.
465 *
466 */
467 union cptx_vqx_misc_int {
468 u64 u;
469 struct cptx_vqx_misc_int_s {
470 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
471 u64 reserved_5_63:59;
472 u64 swerr:1;
473 u64 nwrp:1;
474 u64 irde:1;
475 u64 dovf:1;
476 u64 mbox:1;
477 #else /* Word 0 - Little Endian */
478 u64 mbox:1;
479 u64 dovf:1;
480 u64 irde:1;
481 u64 nwrp:1;
482 u64 swerr:1;
483 u64 reserved_5_63:59;
484 #endif /* Word 0 - End */
485 } s;
486 };
487
488 /**
489 * Register (NCB) cpt#_vq#_done_ack
490 *
491 * CPT Queue Done Count Ack Registers
492 * This register is written by software to acknowledge interrupts.
493 * cptx_vqx_done_ack_s
494 * Word0
495 * reserved_20_63:44 [63:20] Reserved.
496 * done_ack:20 [19:0](R/W/H) Number of decrements to CPT()_VQ()_DONE[DONE].
497 * Reads CPT()_VQ()_DONE[DONE]. Written by software to acknowledge
498 * interrupts. If CPT()_VQ()_DONE[DONE] is still nonzero the interrupt
499 * will be re-sent if the conditions described in CPT()_VQ()_DONE[DONE]
500 * are satisfied.
501 *
502 */
503 union cptx_vqx_done_ack {
504 u64 u;
505 struct cptx_vqx_done_ack_s {
506 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
507 u64 reserved_20_63:44;
508 u64 done_ack:20;
509 #else /* Word 0 - Little Endian */
510 u64 done_ack:20;
511 u64 reserved_20_63:44;
512 #endif /* Word 0 - End */
513 } s;
514 };
515
516 /**
517 * Register (NCB) cpt#_vq#_done
518 *
519 * CPT Queue Done Count Registers
520 * These registers contain the per-queue instruction done count.
521 * cptx_vqx_done_s
522 * Word0
523 * reserved_20_63:44 [63:20] Reserved.
524 * done:20 [19:0](R/W/H) Done count. When CPT_INST_S[DONEINT] set and that
525 * instruction completes, CPT()_VQ()_DONE[DONE] is incremented when the
526 * instruction finishes. Write to this field are for diagnostic use only;
527 * instead software writes CPT()_VQ()_DONE_ACK with the number of
528 * decrements for this field.
529 * Interrupts are sent as follows:
530 * * When CPT()_VQ()_DONE[DONE] = 0, then no results are pending, the
531 * interrupt coalescing timer is held to zero, and an interrupt is not
532 * sent.
533 * * When CPT()_VQ()_DONE[DONE] != 0, then the interrupt coalescing timer
534 * counts. If the counter is >= CPT()_VQ()_DONE_WAIT[TIME_WAIT]*1024, or
535 * CPT()_VQ()_DONE[DONE] >= CPT()_VQ()_DONE_WAIT[NUM_WAIT], i.e. enough
536 * time has passed or enough results have arrived, then the interrupt is
537 * sent.
538 * * When CPT()_VQ()_DONE_ACK is written (or CPT()_VQ()_DONE is written
539 * but this is not typical), the interrupt coalescing timer restarts.
540 * Note after decrementing this interrupt equation is recomputed,
541 * for example if CPT()_VQ()_DONE[DONE] >= CPT()_VQ()_DONE_WAIT[NUM_WAIT]
542 * and because the timer is zero, the interrupt will be resent immediately.
543 * (This covers the race case between software acknowledging an interrupt
544 * and a result returning.)
545 * * When CPT()_VQ()_DONE_ENA_W1S[DONE] = 0, interrupts are not sent,
546 * but the counting described above still occurs.
547 * Since CPT instructions complete out-of-order, if software is using
548 * completion interrupts the suggested scheme is to request a DONEINT on
549 * each request, and when an interrupt arrives perform a "greedy" scan for
550 * completions; even if a later command is acknowledged first this will
551 * not result in missing a completion.
552 * Software is responsible for making sure [DONE] does not overflow;
553 * for example by insuring there are not more than 2^20-1 instructions in
554 * flight that may request interrupts.
555 *
556 */
557 union cptx_vqx_done {
558 u64 u;
559 struct cptx_vqx_done_s {
560 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
561 u64 reserved_20_63:44;
562 u64 done:20;
563 #else /* Word 0 - Little Endian */
564 u64 done:20;
565 u64 reserved_20_63:44;
566 #endif /* Word 0 - End */
567 } s;
568 };
569
570 /**
571 * Register (NCB) cpt#_vq#_done_wait
572 *
573 * CPT Queue Done Interrupt Coalescing Wait Registers
574 * Specifies the per queue interrupt coalescing settings.
575 * cptx_vqx_done_wait_s
576 * Word0
577 * reserved_48_63:16 [63:48] Reserved.
578 * time_wait:16; [47:32](R/W) Time hold-off. When CPT()_VQ()_DONE[DONE] = 0
579 * or CPT()_VQ()_DONE_ACK is written a timer is cleared. When the timer
580 * reaches [TIME_WAIT]*1024 then interrupt coalescing ends.
581 * see CPT()_VQ()_DONE[DONE]. If 0x0, time coalescing is disabled.
582 * reserved_20_31:12 [31:20] Reserved.
583 * num_wait:20 [19:0](R/W) Number of messages hold-off.
584 * When CPT()_VQ()_DONE[DONE] >= [NUM_WAIT] then interrupt coalescing ends
585 * see CPT()_VQ()_DONE[DONE]. If 0x0, same behavior as 0x1.
586 *
587 */
588 union cptx_vqx_done_wait {
589 u64 u;
590 struct cptx_vqx_done_wait_s {
591 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
592 u64 reserved_48_63:16;
593 u64 time_wait:16;
594 u64 reserved_20_31:12;
595 u64 num_wait:20;
596 #else /* Word 0 - Little Endian */
597 u64 num_wait:20;
598 u64 reserved_20_31:12;
599 u64 time_wait:16;
600 u64 reserved_48_63:16;
601 #endif /* Word 0 - End */
602 } s;
603 };
604
605 /**
606 * Register (NCB) cpt#_vq#_done_ena_w1s
607 *
608 * CPT Queue Done Interrupt Enable Set Registers
609 * Write 1 to these registers will enable the DONEINT interrupt for the queue.
610 * cptx_vqx_done_ena_w1s_s
611 * Word0
612 * reserved_1_63:63 [63:1] Reserved.
613 * done:1 [0:0](R/W1S/H) Write 1 will enable DONEINT for this queue.
614 * Write 0 has no effect. Read will return the enable bit.
615 */
616 union cptx_vqx_done_ena_w1s {
617 u64 u;
618 struct cptx_vqx_done_ena_w1s_s {
619 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
620 u64 reserved_1_63:63;
621 u64 done:1;
622 #else /* Word 0 - Little Endian */
623 u64 done:1;
624 u64 reserved_1_63:63;
625 #endif /* Word 0 - End */
626 } s;
627 };
628
629 /**
630 * Register (NCB) cpt#_vq#_ctl
631 *
632 * CPT VF Queue Control Registers
633 * This register configures queues. This register should be changed (other than
634 * clearing [ENA]) only when quiescent (see CPT()_VQ()_INPROG[INFLIGHT]).
635 * cptx_vqx_ctl_s
636 * Word0
637 * reserved_1_63:63 [63:1] Reserved.
638 * ena:1 [0:0](R/W/H) Enables the logical instruction queue.
639 * See also CPT()_PF_Q()_CTL[CONT_ERR] and CPT()_VQ()_INPROG[INFLIGHT].
640 * 1 = Queue is enabled.
641 * 0 = Queue is disabled.
642 */
643 union cptx_vqx_ctl {
644 u64 u;
645 struct cptx_vqx_ctl_s {
646 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
647 u64 reserved_1_63:63;
648 u64 ena:1;
649 #else /* Word 0 - Little Endian */
650 u64 ena:1;
651 u64 reserved_1_63:63;
652 #endif /* Word 0 - End */
653 } s;
654 };
655 #endif /*__CPT_HW_TYPES_H*/