1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) ST-Ericsson SA 2010
4 * Author: Shujuan Chen (shujuan.chen@stericsson.com)
5 * Author: Joakim Bech (joakim.xx.bech@stericsson.com)
6 * Author: Berne Hebark (berne.hebark@stericsson.com))
7 */
8 #ifndef _HASH_ALG_H
9 #define _HASH_ALG_H
10
11 #include <linux/bitops.h>
12
13 #define HASH_BLOCK_SIZE 64
14 #define HASH_DMA_FIFO 4
15 #define HASH_DMA_ALIGN_SIZE 4
16 #define HASH_DMA_PERFORMANCE_MIN_SIZE 1024
17 #define HASH_BYTES_PER_WORD 4
18
19 /* Maximum value of the length's high word */
20 #define HASH_HIGH_WORD_MAX_VAL 0xFFFFFFFFUL
21
22 /* Power on Reset values HASH registers */
23 #define HASH_RESET_CR_VALUE 0x0
24 #define HASH_RESET_STR_VALUE 0x0
25
26 /* Number of context swap registers */
27 #define HASH_CSR_COUNT 52
28
29 #define HASH_RESET_CSRX_REG_VALUE 0x0
30 #define HASH_RESET_CSFULL_REG_VALUE 0x0
31 #define HASH_RESET_CSDATAIN_REG_VALUE 0x0
32
33 #define HASH_RESET_INDEX_VAL 0x0
34 #define HASH_RESET_BIT_INDEX_VAL 0x0
35 #define HASH_RESET_BUFFER_VAL 0x0
36 #define HASH_RESET_LEN_HIGH_VAL 0x0
37 #define HASH_RESET_LEN_LOW_VAL 0x0
38
39 /* Control register bitfields */
40 #define HASH_CR_RESUME_MASK 0x11FCF
41
42 #define HASH_CR_SWITCHON_POS 31
43 #define HASH_CR_SWITCHON_MASK BIT(31)
44
45 #define HASH_CR_EMPTYMSG_POS 20
46 #define HASH_CR_EMPTYMSG_MASK BIT(20)
47
48 #define HASH_CR_DINF_POS 12
49 #define HASH_CR_DINF_MASK BIT(12)
50
51 #define HASH_CR_NBW_POS 8
52 #define HASH_CR_NBW_MASK 0x00000F00UL
53
54 #define HASH_CR_LKEY_POS 16
55 #define HASH_CR_LKEY_MASK BIT(16)
56
57 #define HASH_CR_ALGO_POS 7
58 #define HASH_CR_ALGO_MASK BIT(7)
59
60 #define HASH_CR_MODE_POS 6
61 #define HASH_CR_MODE_MASK BIT(6)
62
63 #define HASH_CR_DATAFORM_POS 4
64 #define HASH_CR_DATAFORM_MASK (BIT(4) | BIT(5))
65
66 #define HASH_CR_DMAE_POS 3
67 #define HASH_CR_DMAE_MASK BIT(3)
68
69 #define HASH_CR_INIT_POS 2
70 #define HASH_CR_INIT_MASK BIT(2)
71
72 #define HASH_CR_PRIVN_POS 1
73 #define HASH_CR_PRIVN_MASK BIT(1)
74
75 #define HASH_CR_SECN_POS 0
76 #define HASH_CR_SECN_MASK BIT(0)
77
78 /* Start register bitfields */
79 #define HASH_STR_DCAL_POS 8
80 #define HASH_STR_DCAL_MASK BIT(8)
81 #define HASH_STR_DEFAULT 0x0
82
83 #define HASH_STR_NBLW_POS 0
84 #define HASH_STR_NBLW_MASK 0x0000001FUL
85
86 #define HASH_NBLW_MAX_VAL 0x1F
87
88 /* PrimeCell IDs */
89 #define HASH_P_ID0 0xE0
90 #define HASH_P_ID1 0x05
91 #define HASH_P_ID2 0x38
92 #define HASH_P_ID3 0x00
93 #define HASH_CELL_ID0 0x0D
94 #define HASH_CELL_ID1 0xF0
95 #define HASH_CELL_ID2 0x05
96 #define HASH_CELL_ID3 0xB1
97
98 #define HASH_SET_BITS(reg_name, mask) \
99 writel_relaxed((readl_relaxed(reg_name) | mask), reg_name)
100
101 #define HASH_CLEAR_BITS(reg_name, mask) \
102 writel_relaxed((readl_relaxed(reg_name) & ~mask), reg_name)
103
104 #define HASH_PUT_BITS(reg, val, shift, mask) \
105 writel_relaxed(((readl(reg) & ~(mask)) | \
106 (((u32)val << shift) & (mask))), reg)
107
108 #define HASH_SET_DIN(val, len) writesl(&device_data->base->din, (val), (len))
109
110 #define HASH_INITIALIZE \
111 HASH_PUT_BITS( \
112 &device_data->base->cr, \
113 0x01, HASH_CR_INIT_POS, \
114 HASH_CR_INIT_MASK)
115
116 #define HASH_SET_DATA_FORMAT(data_format) \
117 HASH_PUT_BITS( \
118 &device_data->base->cr, \
119 (u32) (data_format), HASH_CR_DATAFORM_POS, \
120 HASH_CR_DATAFORM_MASK)
121 #define HASH_SET_NBLW(val) \
122 HASH_PUT_BITS( \
123 &device_data->base->str, \
124 (u32) (val), HASH_STR_NBLW_POS, \
125 HASH_STR_NBLW_MASK)
126 #define HASH_SET_DCAL \
127 HASH_PUT_BITS( \
128 &device_data->base->str, \
129 0x01, HASH_STR_DCAL_POS, \
130 HASH_STR_DCAL_MASK)
131
132 /* Hardware access method */
133 enum hash_mode {
134 HASH_MODE_CPU,
135 HASH_MODE_DMA
136 };
137
138 /**
139 * struct uint64 - Structure to handle 64 bits integers.
140 * @high_word: Most significant bits.
141 * @low_word: Least significant bits.
142 *
143 * Used to handle 64 bits integers.
144 */
145 struct uint64 {
146 u32 high_word;
147 u32 low_word;
148 };
149
150 /**
151 * struct hash_register - Contains all registers in ux500 hash hardware.
152 * @cr: HASH control register (0x000).
153 * @din: HASH data input register (0x004).
154 * @str: HASH start register (0x008).
155 * @hx: HASH digest register 0..7 (0x00c-0x01C).
156 * @padding0: Reserved (0x02C).
157 * @itcr: Integration test control register (0x080).
158 * @itip: Integration test input register (0x084).
159 * @itop: Integration test output register (0x088).
160 * @padding1: Reserved (0x08C).
161 * @csfull: HASH context full register (0x0F8).
162 * @csdatain: HASH context swap data input register (0x0FC).
163 * @csrx: HASH context swap register 0..51 (0x100-0x1CC).
164 * @padding2: Reserved (0x1D0).
165 * @periphid0: HASH peripheral identification register 0 (0xFE0).
166 * @periphid1: HASH peripheral identification register 1 (0xFE4).
167 * @periphid2: HASH peripheral identification register 2 (0xFE8).
168 * @periphid3: HASH peripheral identification register 3 (0xFEC).
169 * @cellid0: HASH PCell identification register 0 (0xFF0).
170 * @cellid1: HASH PCell identification register 1 (0xFF4).
171 * @cellid2: HASH PCell identification register 2 (0xFF8).
172 * @cellid3: HASH PCell identification register 3 (0xFFC).
173 *
174 * The device communicates to the HASH via 32-bit-wide control registers
175 * accessible via the 32-bit width AMBA rev. 2.0 AHB Bus. Below is a structure
176 * with the registers used.
177 */
178 struct hash_register {
179 u32 cr;
180 u32 din;
181 u32 str;
182 u32 hx[8];
183
184 u32 padding0[(0x080 - 0x02C) / sizeof(u32)];
185
186 u32 itcr;
187 u32 itip;
188 u32 itop;
189
190 u32 padding1[(0x0F8 - 0x08C) / sizeof(u32)];
191
192 u32 csfull;
193 u32 csdatain;
194 u32 csrx[HASH_CSR_COUNT];
195
196 u32 padding2[(0xFE0 - 0x1D0) / sizeof(u32)];
197
198 u32 periphid0;
199 u32 periphid1;
200 u32 periphid2;
201 u32 periphid3;
202
203 u32 cellid0;
204 u32 cellid1;
205 u32 cellid2;
206 u32 cellid3;
207 };
208
209 /**
210 * struct hash_state - Hash context state.
211 * @temp_cr: Temporary HASH Control Register.
212 * @str_reg: HASH Start Register.
213 * @din_reg: HASH Data Input Register.
214 * @csr[52]: HASH Context Swap Registers 0-39.
215 * @csfull: HASH Context Swap Registers 40 ie Status flags.
216 * @csdatain: HASH Context Swap Registers 41 ie Input data.
217 * @buffer: Working buffer for messages going to the hardware.
218 * @length: Length of the part of message hashed so far (floor(N/64) * 64).
219 * @index: Valid number of bytes in buffer (N % 64).
220 * @bit_index: Valid number of bits in buffer (N % 8).
221 *
222 * This structure is used between context switches, i.e. when ongoing jobs are
223 * interupted with new jobs. When this happens we need to store intermediate
224 * results in software.
225 *
226 * WARNING: "index" is the member of the structure, to be sure that "buffer"
227 * is aligned on a 4-bytes boundary. This is highly implementation dependent
228 * and MUST be checked whenever this code is ported on new platforms.
229 */
230 struct hash_state {
231 u32 temp_cr;
232 u32 str_reg;
233 u32 din_reg;
234 u32 csr[52];
235 u32 csfull;
236 u32 csdatain;
237 u32 buffer[HASH_BLOCK_SIZE / sizeof(u32)];
238 struct uint64 length;
239 u8 index;
240 u8 bit_index;
241 };
242
243 /**
244 * enum hash_device_id - HASH device ID.
245 * @HASH_DEVICE_ID_0: Hash hardware with ID 0
246 * @HASH_DEVICE_ID_1: Hash hardware with ID 1
247 */
248 enum hash_device_id {
249 HASH_DEVICE_ID_0 = 0,
250 HASH_DEVICE_ID_1 = 1
251 };
252
253 /**
254 * enum hash_data_format - HASH data format.
255 * @HASH_DATA_32_BITS: 32 bits data format
256 * @HASH_DATA_16_BITS: 16 bits data format
257 * @HASH_DATA_8_BITS: 8 bits data format.
258 * @HASH_DATA_1_BITS: 1 bit data format.
259 */
260 enum hash_data_format {
261 HASH_DATA_32_BITS = 0x0,
262 HASH_DATA_16_BITS = 0x1,
263 HASH_DATA_8_BITS = 0x2,
264 HASH_DATA_1_BIT = 0x3
265 };
266
267 /**
268 * enum hash_algo - Enumeration for selecting between SHA1 or SHA2 algorithm.
269 * @HASH_ALGO_SHA1: Indicates that SHA1 is used.
270 * @HASH_ALGO_SHA2: Indicates that SHA2 (SHA256) is used.
271 */
272 enum hash_algo {
273 HASH_ALGO_SHA1 = 0x0,
274 HASH_ALGO_SHA256 = 0x1
275 };
276
277 /**
278 * enum hash_op - Enumeration for selecting between HASH or HMAC mode.
279 * @HASH_OPER_MODE_HASH: Indicates usage of normal HASH mode.
280 * @HASH_OPER_MODE_HMAC: Indicates usage of HMAC.
281 */
282 enum hash_op {
283 HASH_OPER_MODE_HASH = 0x0,
284 HASH_OPER_MODE_HMAC = 0x1
285 };
286
287 /**
288 * struct hash_config - Configuration data for the hardware.
289 * @data_format: Format of data entered into the hash data in register.
290 * @algorithm: Algorithm selection bit.
291 * @oper_mode: Operating mode selection bit.
292 */
293 struct hash_config {
294 int data_format;
295 int algorithm;
296 int oper_mode;
297 };
298
299 /**
300 * struct hash_dma - Structure used for dma.
301 * @mask: DMA capabilities bitmap mask.
302 * @complete: Used to maintain state for a "completion".
303 * @chan_mem2hash: DMA channel.
304 * @cfg_mem2hash: DMA channel configuration.
305 * @sg_len: Scatterlist length.
306 * @sg: Scatterlist.
307 * @nents: Number of sg entries.
308 */
309 struct hash_dma {
310 dma_cap_mask_t mask;
311 struct completion complete;
312 struct dma_chan *chan_mem2hash;
313 void *cfg_mem2hash;
314 int sg_len;
315 struct scatterlist *sg;
316 int nents;
317 };
318
319 /**
320 * struct hash_ctx - The context used for hash calculations.
321 * @key: The key used in the operation.
322 * @keylen: The length of the key.
323 * @state: The state of the current calculations.
324 * @config: The current configuration.
325 * @digestsize: The size of current digest.
326 * @device: Pointer to the device structure.
327 */
328 struct hash_ctx {
329 u8 *key;
330 u32 keylen;
331 struct hash_config config;
332 int digestsize;
333 struct hash_device_data *device;
334 };
335
336 /**
337 * struct hash_ctx - The request context used for hash calculations.
338 * @state: The state of the current calculations.
339 * @dma_mode: Used in special cases (workaround), e.g. need to change to
340 * cpu mode, if not supported/working in dma mode.
341 * @updated: Indicates if hardware is initialized for new operations.
342 */
343 struct hash_req_ctx {
344 struct hash_state state;
345 bool dma_mode;
346 u8 updated;
347 };
348
349 /**
350 * struct hash_device_data - structure for a hash device.
351 * @base: Pointer to virtual base address of the hash device.
352 * @phybase: Pointer to physical memory location of the hash device.
353 * @list_node: For inclusion in klist.
354 * @dev: Pointer to the device dev structure.
355 * @ctx_lock: Spinlock for current_ctx.
356 * @current_ctx: Pointer to the currently allocated context.
357 * @power_state: TRUE = power state on, FALSE = power state off.
358 * @power_state_lock: Spinlock for power_state.
359 * @regulator: Pointer to the device's power control.
360 * @clk: Pointer to the device's clock control.
361 * @restore_dev_state: TRUE = saved state, FALSE = no saved state.
362 * @dma: Structure used for dma.
363 */
364 struct hash_device_data {
365 struct hash_register __iomem *base;
366 phys_addr_t phybase;
367 struct klist_node list_node;
368 struct device *dev;
369 spinlock_t ctx_lock;
370 struct hash_ctx *current_ctx;
371 bool power_state;
372 spinlock_t power_state_lock;
373 struct regulator *regulator;
374 struct clk *clk;
375 bool restore_dev_state;
376 struct hash_state state; /* Used for saving and resuming state */
377 struct hash_dma dma;
378 };
379
380 int hash_check_hw(struct hash_device_data *device_data);
381
382 int hash_setconfiguration(struct hash_device_data *device_data,
383 struct hash_config *config);
384
385 void hash_begin(struct hash_device_data *device_data, struct hash_ctx *ctx);
386
387 void hash_get_digest(struct hash_device_data *device_data,
388 u8 *digest, int algorithm);
389
390 int hash_hw_update(struct ahash_request *req);
391
392 int hash_save_state(struct hash_device_data *device_data,
393 struct hash_state *state);
394
395 int hash_resume_state(struct hash_device_data *device_data,
396 const struct hash_state *state);
397
398 #endif