This source file includes following definitions.
- eip197_noop_token
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8 #ifndef __SAFEXCEL_H__
9 #define __SAFEXCEL_H__
10
11 #include <crypto/aead.h>
12 #include <crypto/algapi.h>
13 #include <crypto/internal/hash.h>
14 #include <crypto/sha.h>
15 #include <crypto/skcipher.h>
16
17 #define EIP197_HIA_VERSION_BE 0xca35
18 #define EIP197_HIA_VERSION_LE 0x35ca
19 #define EIP97_VERSION_LE 0x9e61
20 #define EIP197_VERSION_LE 0x3ac5
21 #define EIP96_VERSION_LE 0x9f60
22 #define EIP197_REG_LO16(reg) (reg & 0xffff)
23 #define EIP197_REG_HI16(reg) ((reg >> 16) & 0xffff)
24 #define EIP197_VERSION_MASK(reg) ((reg >> 16) & 0xfff)
25 #define EIP197_VERSION_SWAP(reg) (((reg & 0xf0) << 4) | \
26 ((reg >> 4) & 0xf0) | \
27 ((reg >> 12) & 0xf))
28
29
30 #define EIP197_DEFAULT_RING_SIZE 400
31 #define EIP197_MAX_TOKENS 18
32 #define EIP197_MAX_RINGS 4
33 #define EIP197_FETCH_DEPTH 2
34 #define EIP197_MAX_BATCH_SZ 64
35
36 #define EIP197_GFP_FLAGS(base) ((base).flags & CRYPTO_TFM_REQ_MAY_SLEEP ? \
37 GFP_KERNEL : GFP_ATOMIC)
38
39
40 #define EIP197_SKCIPHER_REQ_SIZE sizeof(struct skcipher_request) + \
41 sizeof(struct safexcel_cipher_req)
42 #define EIP197_AHASH_REQ_SIZE sizeof(struct ahash_request) + \
43 sizeof(struct safexcel_ahash_req)
44 #define EIP197_AEAD_REQ_SIZE sizeof(struct aead_request) + \
45 sizeof(struct safexcel_cipher_req)
46 #define EIP197_REQUEST_ON_STACK(name, type, size) \
47 char __##name##_desc[size] CRYPTO_MINALIGN_ATTR; \
48 struct type##_request *name = (void *)__##name##_desc
49
50
51 #define EIP197_XLX_GPIO_BASE 0x200000
52 #define EIP197_XLX_IRQ_BLOCK_ID_ADDR 0x2000
53 #define EIP197_XLX_IRQ_BLOCK_ID_VALUE 0x1fc2
54 #define EIP197_XLX_USER_INT_ENB_MSK 0x2004
55 #define EIP197_XLX_USER_INT_ENB_SET 0x2008
56 #define EIP197_XLX_USER_INT_ENB_CLEAR 0x200c
57 #define EIP197_XLX_USER_INT_BLOCK 0x2040
58 #define EIP197_XLX_USER_INT_PEND 0x2048
59 #define EIP197_XLX_USER_VECT_LUT0_ADDR 0x2080
60 #define EIP197_XLX_USER_VECT_LUT0_IDENT 0x03020100
61 #define EIP197_XLX_USER_VECT_LUT1_ADDR 0x2084
62 #define EIP197_XLX_USER_VECT_LUT1_IDENT 0x07060504
63 #define EIP197_XLX_USER_VECT_LUT2_ADDR 0x2088
64 #define EIP197_XLX_USER_VECT_LUT2_IDENT 0x0b0a0908
65 #define EIP197_XLX_USER_VECT_LUT3_ADDR 0x208c
66 #define EIP197_XLX_USER_VECT_LUT3_IDENT 0x0f0e0d0c
67
68
69 #define EIP197_IRQ_NUMBER(i, is_pci) (i + is_pci)
70
71
72 #define EIP197_HIA_AIC(priv) ((priv)->base + (priv)->offsets.hia_aic)
73 #define EIP197_HIA_AIC_G(priv) ((priv)->base + (priv)->offsets.hia_aic_g)
74 #define EIP197_HIA_AIC_R(priv) ((priv)->base + (priv)->offsets.hia_aic_r)
75 #define EIP197_HIA_AIC_xDR(priv) ((priv)->base + (priv)->offsets.hia_aic_xdr)
76 #define EIP197_HIA_DFE(priv) ((priv)->base + (priv)->offsets.hia_dfe)
77 #define EIP197_HIA_DFE_THR(priv) ((priv)->base + (priv)->offsets.hia_dfe_thr)
78 #define EIP197_HIA_DSE(priv) ((priv)->base + (priv)->offsets.hia_dse)
79 #define EIP197_HIA_DSE_THR(priv) ((priv)->base + (priv)->offsets.hia_dse_thr)
80 #define EIP197_HIA_GEN_CFG(priv) ((priv)->base + (priv)->offsets.hia_gen_cfg)
81 #define EIP197_PE(priv) ((priv)->base + (priv)->offsets.pe)
82 #define EIP197_GLOBAL(priv) ((priv)->base + (priv)->offsets.global)
83
84
85 #define EIP197_HIA_AIC_BASE 0x90000
86 #define EIP197_HIA_AIC_G_BASE 0x90000
87 #define EIP197_HIA_AIC_R_BASE 0x90800
88 #define EIP197_HIA_AIC_xDR_BASE 0x80000
89 #define EIP197_HIA_DFE_BASE 0x8c000
90 #define EIP197_HIA_DFE_THR_BASE 0x8c040
91 #define EIP197_HIA_DSE_BASE 0x8d000
92 #define EIP197_HIA_DSE_THR_BASE 0x8d040
93 #define EIP197_HIA_GEN_CFG_BASE 0xf0000
94 #define EIP197_PE_BASE 0xa0000
95 #define EIP197_GLOBAL_BASE 0xf0000
96
97
98 #define EIP97_HIA_AIC_BASE 0x0
99 #define EIP97_HIA_AIC_G_BASE 0x0
100 #define EIP97_HIA_AIC_R_BASE 0x0
101 #define EIP97_HIA_AIC_xDR_BASE 0x0
102 #define EIP97_HIA_DFE_BASE 0xf000
103 #define EIP97_HIA_DFE_THR_BASE 0xf200
104 #define EIP97_HIA_DSE_BASE 0xf400
105 #define EIP97_HIA_DSE_THR_BASE 0xf600
106 #define EIP97_HIA_GEN_CFG_BASE 0x10000
107 #define EIP97_PE_BASE 0x10000
108 #define EIP97_GLOBAL_BASE 0x10000
109
110
111 #define EIP197_HIA_xDR_OFF(priv, r) (EIP197_HIA_AIC_xDR(priv) + (r) * 0x1000)
112 #define EIP197_HIA_CDR(priv, r) (EIP197_HIA_xDR_OFF(priv, r))
113 #define EIP197_HIA_RDR(priv, r) (EIP197_HIA_xDR_OFF(priv, r) + 0x800)
114 #define EIP197_HIA_xDR_RING_BASE_ADDR_LO 0x0000
115 #define EIP197_HIA_xDR_RING_BASE_ADDR_HI 0x0004
116 #define EIP197_HIA_xDR_RING_SIZE 0x0018
117 #define EIP197_HIA_xDR_DESC_SIZE 0x001c
118 #define EIP197_HIA_xDR_CFG 0x0020
119 #define EIP197_HIA_xDR_DMA_CFG 0x0024
120 #define EIP197_HIA_xDR_THRESH 0x0028
121 #define EIP197_HIA_xDR_PREP_COUNT 0x002c
122 #define EIP197_HIA_xDR_PROC_COUNT 0x0030
123 #define EIP197_HIA_xDR_PREP_PNTR 0x0034
124 #define EIP197_HIA_xDR_PROC_PNTR 0x0038
125 #define EIP197_HIA_xDR_STAT 0x003c
126
127
128 #define EIP197_HIA_DFE_CFG(n) (0x0000 + (128 * (n)))
129 #define EIP197_HIA_DFE_THR_CTRL(n) (0x0000 + (128 * (n)))
130 #define EIP197_HIA_DFE_THR_STAT(n) (0x0004 + (128 * (n)))
131 #define EIP197_HIA_DSE_CFG(n) (0x0000 + (128 * (n)))
132 #define EIP197_HIA_DSE_THR_CTRL(n) (0x0000 + (128 * (n)))
133 #define EIP197_HIA_DSE_THR_STAT(n) (0x0004 + (128 * (n)))
134 #define EIP197_HIA_RA_PE_CTRL(n) (0x0010 + (8 * (n)))
135 #define EIP197_HIA_RA_PE_STAT 0x0014
136 #define EIP197_HIA_AIC_R_OFF(r) ((r) * 0x1000)
137 #define EIP197_HIA_AIC_R_ENABLE_CTRL(r) (0xe008 - EIP197_HIA_AIC_R_OFF(r))
138 #define EIP197_HIA_AIC_R_ENABLED_STAT(r) (0xe010 - EIP197_HIA_AIC_R_OFF(r))
139 #define EIP197_HIA_AIC_R_ACK(r) (0xe010 - EIP197_HIA_AIC_R_OFF(r))
140 #define EIP197_HIA_AIC_R_ENABLE_CLR(r) (0xe014 - EIP197_HIA_AIC_R_OFF(r))
141 #define EIP197_HIA_AIC_G_ENABLE_CTRL 0xf808
142 #define EIP197_HIA_AIC_G_ENABLED_STAT 0xf810
143 #define EIP197_HIA_AIC_G_ACK 0xf810
144 #define EIP197_HIA_MST_CTRL 0xfff4
145 #define EIP197_HIA_OPTIONS 0xfff8
146 #define EIP197_HIA_VERSION 0xfffc
147 #define EIP197_PE_IN_DBUF_THRES(n) (0x0000 + (0x2000 * (n)))
148 #define EIP197_PE_IN_TBUF_THRES(n) (0x0100 + (0x2000 * (n)))
149 #define EIP197_PE_ICE_SCRATCH_RAM(n) (0x0800 + (0x2000 * (n)))
150 #define EIP197_PE_ICE_PUE_CTRL(n) (0x0c80 + (0x2000 * (n)))
151 #define EIP197_PE_ICE_PUTF_CTRL(n) (0x0d00 + (0x2000 * (n)))
152 #define EIP197_PE_ICE_SCRATCH_CTRL(n) (0x0d04 + (0x2000 * (n)))
153 #define EIP197_PE_ICE_FPP_CTRL(n) (0x0d80 + (0x2000 * (n)))
154 #define EIP197_PE_ICE_PPTF_CTRL(n) (0x0e00 + (0x2000 * (n)))
155 #define EIP197_PE_ICE_RAM_CTRL(n) (0x0ff0 + (0x2000 * (n)))
156 #define EIP197_PE_EIP96_TOKEN_CTRL(n) (0x1000 + (0x2000 * (n)))
157 #define EIP197_PE_EIP96_FUNCTION_EN(n) (0x1004 + (0x2000 * (n)))
158 #define EIP197_PE_EIP96_CONTEXT_CTRL(n) (0x1008 + (0x2000 * (n)))
159 #define EIP197_PE_EIP96_CONTEXT_STAT(n) (0x100c + (0x2000 * (n)))
160 #define EIP197_PE_EIP96_FUNCTION2_EN(n) (0x1030 + (0x2000 * (n)))
161 #define EIP197_PE_EIP96_OPTIONS(n) (0x13f8 + (0x2000 * (n)))
162 #define EIP197_PE_EIP96_VERSION(n) (0x13fc + (0x2000 * (n)))
163 #define EIP197_PE_OUT_DBUF_THRES(n) (0x1c00 + (0x2000 * (n)))
164 #define EIP197_PE_OUT_TBUF_THRES(n) (0x1d00 + (0x2000 * (n)))
165 #define EIP197_MST_CTRL 0xfff4
166 #define EIP197_VERSION 0xfffc
167
168
169 #define EIP197_CLASSIFICATION_RAMS 0xe0000
170 #define EIP197_TRC_CTRL 0xf0800
171 #define EIP197_TRC_LASTRES 0xf0804
172 #define EIP197_TRC_REGINDEX 0xf0808
173 #define EIP197_TRC_PARAMS 0xf0820
174 #define EIP197_TRC_FREECHAIN 0xf0824
175 #define EIP197_TRC_PARAMS2 0xf0828
176 #define EIP197_TRC_ECCCTRL 0xf0830
177 #define EIP197_TRC_ECCSTAT 0xf0834
178 #define EIP197_TRC_ECCADMINSTAT 0xf0838
179 #define EIP197_TRC_ECCDATASTAT 0xf083c
180 #define EIP197_TRC_ECCDATA 0xf0840
181 #define EIP197_FLUE_CACHEBASE_LO(n) (0xf6000 + (32 * (n)))
182 #define EIP197_FLUE_CACHEBASE_HI(n) (0xf6004 + (32 * (n)))
183 #define EIP197_FLUE_CONFIG(n) (0xf6010 + (32 * (n)))
184 #define EIP197_FLUE_OFFSETS 0xf6808
185 #define EIP197_FLUE_ARC4_OFFSET 0xf680c
186 #define EIP197_FLUE_IFC_LUT(n) (0xf6820 + (4 * (n)))
187 #define EIP197_CS_RAM_CTRL 0xf7ff0
188
189
190 #define EIP197_xDR_DESC_MODE_64BIT BIT(31)
191
192
193 #define EIP197_HIA_xDR_WR_RES_BUF BIT(22)
194 #define EIP197_HIA_xDR_WR_CTRL_BUF BIT(23)
195 #define EIP197_HIA_xDR_WR_OWN_BUF BIT(24)
196 #define EIP197_HIA_xDR_CFG_WR_CACHE(n) (((n) & 0x7) << 25)
197 #define EIP197_HIA_xDR_CFG_RD_CACHE(n) (((n) & 0x7) << 29)
198
199
200 #define EIP197_HIA_CDR_THRESH_PROC_PKT(n) (n)
201 #define EIP197_HIA_CDR_THRESH_PROC_MODE BIT(22)
202 #define EIP197_HIA_CDR_THRESH_PKT_MODE BIT(23)
203 #define EIP197_HIA_CDR_THRESH_TIMEOUT(n) ((n) << 24)
204
205
206 #define EIP197_HIA_RDR_THRESH_PROC_PKT(n) (n)
207 #define EIP197_HIA_RDR_THRESH_PKT_MODE BIT(23)
208 #define EIP197_HIA_RDR_THRESH_TIMEOUT(n) ((n) << 24)
209
210
211 #define EIP197_xDR_PREP_CLR_COUNT BIT(31)
212
213
214 #define EIP197_xDR_PROC_xD_PKT_OFFSET 24
215 #define EIP197_xDR_PROC_xD_PKT_MASK GENMASK(6, 0)
216 #define EIP197_xDR_PROC_xD_COUNT(n) ((n) << 2)
217 #define EIP197_xDR_PROC_xD_PKT(n) ((n) << 24)
218 #define EIP197_xDR_PROC_CLR_COUNT BIT(31)
219
220
221 #define EIP197_xDR_DMA_ERR BIT(0)
222 #define EIP197_xDR_PREP_CMD_THRES BIT(1)
223 #define EIP197_xDR_ERR BIT(2)
224 #define EIP197_xDR_THRESH BIT(4)
225 #define EIP197_xDR_TIMEOUT BIT(5)
226
227 #define EIP197_HIA_RA_PE_CTRL_RESET BIT(31)
228 #define EIP197_HIA_RA_PE_CTRL_EN BIT(30)
229
230
231 #define EIP197_N_PES_OFFSET 4
232 #define EIP197_N_PES_MASK GENMASK(4, 0)
233 #define EIP97_N_PES_MASK GENMASK(2, 0)
234 #define EIP197_HWDATAW_OFFSET 25
235 #define EIP197_HWDATAW_MASK GENMASK(3, 0)
236 #define EIP97_HWDATAW_MASK GENMASK(2, 0)
237 #define EIP197_CFSIZE_OFFSET 9
238 #define EIP197_CFSIZE_ADJUST 4
239 #define EIP97_CFSIZE_OFFSET 8
240 #define EIP197_CFSIZE_MASK GENMASK(3, 0)
241 #define EIP97_CFSIZE_MASK GENMASK(4, 0)
242 #define EIP197_RFSIZE_OFFSET 12
243 #define EIP197_RFSIZE_ADJUST 4
244 #define EIP97_RFSIZE_OFFSET 12
245 #define EIP197_RFSIZE_MASK GENMASK(3, 0)
246 #define EIP97_RFSIZE_MASK GENMASK(4, 0)
247
248
249 #define EIP197_CDR_IRQ(n) BIT((n) * 2)
250 #define EIP197_RDR_IRQ(n) BIT((n) * 2 + 1)
251
252
253 #define EIP197_HIA_DxE_CFG_MIN_DATA_SIZE(n) ((n) << 0)
254 #define EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(n) (((n) & 0x7) << 4)
255 #define EIP197_HIA_DxE_CFG_MAX_DATA_SIZE(n) ((n) << 8)
256 #define EIP197_HIA_DSE_CFG_ALWAYS_BUFFERABLE GENMASK(15, 14)
257 #define EIP197_HIA_DxE_CFG_MIN_CTRL_SIZE(n) ((n) << 16)
258 #define EIP197_HIA_DxE_CFG_CTRL_CACHE_CTRL(n) (((n) & 0x7) << 20)
259 #define EIP197_HIA_DxE_CFG_MAX_CTRL_SIZE(n) ((n) << 24)
260 #define EIP197_HIA_DFE_CFG_DIS_DEBUG (BIT(31) | BIT(29))
261 #define EIP197_HIA_DSE_CFG_EN_SINGLE_WR BIT(29)
262 #define EIP197_HIA_DSE_CFG_DIS_DEBUG BIT(31)
263
264
265 #define EIP197_DxE_THR_CTRL_EN BIT(30)
266 #define EIP197_DxE_THR_CTRL_RESET_PE BIT(31)
267
268
269 #define EIP197_PE_ICE_UENG_START_OFFSET(n) ((n) << 16)
270 #define EIP197_PE_ICE_UENG_INIT_ALIGN_MASK 0x7ff0
271 #define EIP197_PE_ICE_UENG_DEBUG_RESET BIT(3)
272
273
274 #define EIP197_G_IRQ_DFE(n) BIT((n) << 1)
275 #define EIP197_G_IRQ_DSE(n) BIT(((n) << 1) + 1)
276 #define EIP197_G_IRQ_RING BIT(16)
277 #define EIP197_G_IRQ_PE(n) BIT((n) + 20)
278
279
280 #define RD_CACHE_3BITS 0x5
281 #define WR_CACHE_3BITS 0x3
282 #define RD_CACHE_4BITS (RD_CACHE_3BITS << 1 | BIT(0))
283 #define WR_CACHE_4BITS (WR_CACHE_3BITS << 1 | BIT(0))
284 #define EIP197_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0)
285 #define EIP197_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4)
286 #define EIP197_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 20)
287 #define EIP197_MST_CTRL_BYTE_SWAP BIT(24)
288 #define EIP197_MST_CTRL_NO_BYTE_SWAP BIT(25)
289 #define EIP197_MST_CTRL_BYTE_SWAP_BITS GENMASK(25, 24)
290
291
292 #define EIP197_PE_IN_xBUF_THRES_MIN(n) ((n) << 8)
293 #define EIP197_PE_IN_xBUF_THRES_MAX(n) ((n) << 12)
294
295
296 #define EIP197_PE_OUT_DBUF_THRES_MIN(n) ((n) << 0)
297 #define EIP197_PE_OUT_DBUF_THRES_MAX(n) ((n) << 4)
298
299
300 #define EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_TIMER BIT(2)
301 #define EIP197_PE_ICE_SCRATCH_CTRL_TIMER_EN BIT(3)
302 #define EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_ACCESS BIT(24)
303 #define EIP197_PE_ICE_SCRATCH_CTRL_SCRATCH_ACCESS BIT(25)
304
305
306 #define EIP197_NUM_OF_SCRATCH_BLOCKS 32
307
308
309 #define EIP197_PE_ICE_x_CTRL_SW_RESET BIT(0)
310 #define EIP197_PE_ICE_x_CTRL_CLR_ECC_NON_CORR BIT(14)
311 #define EIP197_PE_ICE_x_CTRL_CLR_ECC_CORR BIT(15)
312
313
314 #define EIP197_PE_ICE_RAM_CTRL_PUE_PROG_EN BIT(0)
315 #define EIP197_PE_ICE_RAM_CTRL_FPP_PROG_EN BIT(1)
316
317
318 #define EIP197_PE_EIP96_TOKEN_CTRL_CTX_UPDATES BIT(16)
319 #define EIP197_PE_EIP96_TOKEN_CTRL_NO_TOKEN_WAIT BIT(17)
320 #define EIP197_PE_EIP96_TOKEN_CTRL_ENABLE_TIMEOUT BIT(22)
321
322
323 #define EIP197_FUNCTION_ALL 0xffffffff
324
325
326 #define EIP197_CONTEXT_SIZE(n) (n)
327 #define EIP197_ADDRESS_MODE BIT(8)
328 #define EIP197_CONTROL_MODE BIT(9)
329
330
331 #define EIP197_FLUE_CONFIG_MAGIC 0xc7000004
332
333
334 struct safexcel_context_record {
335 u32 control0;
336 u32 control1;
337
338 __le32 data[40];
339 } __packed;
340
341
342 #define CONTEXT_CONTROL_TYPE_NULL_OUT 0x0
343 #define CONTEXT_CONTROL_TYPE_NULL_IN 0x1
344 #define CONTEXT_CONTROL_TYPE_HASH_OUT 0x2
345 #define CONTEXT_CONTROL_TYPE_HASH_IN 0x3
346 #define CONTEXT_CONTROL_TYPE_CRYPTO_OUT 0x4
347 #define CONTEXT_CONTROL_TYPE_CRYPTO_IN 0x5
348 #define CONTEXT_CONTROL_TYPE_ENCRYPT_HASH_OUT 0x6
349 #define CONTEXT_CONTROL_TYPE_DECRYPT_HASH_IN 0x7
350 #define CONTEXT_CONTROL_TYPE_HASH_ENCRYPT_OUT 0xe
351 #define CONTEXT_CONTROL_TYPE_HASH_DECRYPT_IN 0xf
352 #define CONTEXT_CONTROL_RESTART_HASH BIT(4)
353 #define CONTEXT_CONTROL_NO_FINISH_HASH BIT(5)
354 #define CONTEXT_CONTROL_SIZE(n) ((n) << 8)
355 #define CONTEXT_CONTROL_KEY_EN BIT(16)
356 #define CONTEXT_CONTROL_CRYPTO_ALG_DES (0x0 << 17)
357 #define CONTEXT_CONTROL_CRYPTO_ALG_3DES (0x2 << 17)
358 #define CONTEXT_CONTROL_CRYPTO_ALG_AES128 (0x5 << 17)
359 #define CONTEXT_CONTROL_CRYPTO_ALG_AES192 (0x6 << 17)
360 #define CONTEXT_CONTROL_CRYPTO_ALG_AES256 (0x7 << 17)
361 #define CONTEXT_CONTROL_DIGEST_PRECOMPUTED (0x1 << 21)
362 #define CONTEXT_CONTROL_DIGEST_XCM (0x2 << 21)
363 #define CONTEXT_CONTROL_DIGEST_HMAC (0x3 << 21)
364 #define CONTEXT_CONTROL_CRYPTO_ALG_MD5 (0x0 << 23)
365 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA1 (0x2 << 23)
366 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA224 (0x4 << 23)
367 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA256 (0x3 << 23)
368 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA384 (0x6 << 23)
369 #define CONTEXT_CONTROL_CRYPTO_ALG_SHA512 (0x5 << 23)
370 #define CONTEXT_CONTROL_CRYPTO_ALG_GHASH (0x4 << 23)
371 #define CONTEXT_CONTROL_CRYPTO_ALG_XCBC128 (0x1 << 23)
372 #define CONTEXT_CONTROL_CRYPTO_ALG_XCBC192 (0x2 << 23)
373 #define CONTEXT_CONTROL_CRYPTO_ALG_XCBC256 (0x3 << 23)
374 #define CONTEXT_CONTROL_INV_FR (0x5 << 24)
375 #define CONTEXT_CONTROL_INV_TR (0x6 << 24)
376
377
378 #define CONTEXT_CONTROL_CRYPTO_MODE_ECB (0 << 0)
379 #define CONTEXT_CONTROL_CRYPTO_MODE_CBC (1 << 0)
380 #define CONTEXT_CONTROL_CRYPTO_MODE_OFB (4 << 0)
381 #define CONTEXT_CONTROL_CRYPTO_MODE_CFB (5 << 0)
382 #define CONTEXT_CONTROL_CRYPTO_MODE_CTR_LOAD (6 << 0)
383 #define CONTEXT_CONTROL_CRYPTO_MODE_XTS (7 << 0)
384 #define CONTEXT_CONTROL_CRYPTO_MODE_XCM ((6 << 0) | BIT(17))
385 #define CONTEXT_CONTROL_IV0 BIT(5)
386 #define CONTEXT_CONTROL_IV1 BIT(6)
387 #define CONTEXT_CONTROL_IV2 BIT(7)
388 #define CONTEXT_CONTROL_IV3 BIT(8)
389 #define CONTEXT_CONTROL_DIGEST_CNT BIT(9)
390 #define CONTEXT_CONTROL_COUNTER_MODE BIT(10)
391 #define CONTEXT_CONTROL_CRYPTO_STORE BIT(12)
392 #define CONTEXT_CONTROL_HASH_STORE BIT(19)
393
394 #define EIP197_XCM_MODE_GCM 1
395 #define EIP197_XCM_MODE_CCM 2
396
397
398
399
400 #define EIP197_COUNTER_BLOCK_SIZE 64
401
402
403 #define EIP197_TRC_ENABLE_0 BIT(4)
404 #define EIP197_TRC_ENABLE_1 BIT(5)
405 #define EIP197_TRC_ENABLE_2 BIT(6)
406 #define EIP197_TRC_ENABLE_MASK GENMASK(6, 4)
407 #define EIP197_CS_BANKSEL_MASK GENMASK(14, 12)
408 #define EIP197_CS_BANKSEL_OFS 12
409
410
411 #define EIP197_TRC_PARAMS_SW_RESET BIT(0)
412 #define EIP197_TRC_PARAMS_DATA_ACCESS BIT(2)
413 #define EIP197_TRC_PARAMS_HTABLE_SZ(x) ((x) << 4)
414 #define EIP197_TRC_PARAMS_BLK_TIMER_SPEED(x) ((x) << 10)
415 #define EIP197_TRC_PARAMS_RC_SZ_LARGE(n) ((n) << 18)
416
417
418 #define EIP197_TRC_FREECHAIN_HEAD_PTR(p) (p)
419 #define EIP197_TRC_FREECHAIN_TAIL_PTR(p) ((p) << 16)
420
421
422 #define EIP197_TRC_PARAMS2_HTABLE_PTR(p) (p)
423 #define EIP197_TRC_PARAMS2_RC_SZ_SMALL(n) ((n) << 18)
424
425
426 #define EIP197_CS_TRC_REC_WC 64
427 #define EIP197_CS_RC_SIZE (4 * sizeof(u32))
428 #define EIP197_CS_RC_NEXT(x) (x)
429 #define EIP197_CS_RC_PREV(x) ((x) << 10)
430 #define EIP197_RC_NULL 0x3ff
431
432
433 struct result_data_desc {
434 u32 packet_length:17;
435 u32 error_code:15;
436
437 u8 bypass_length:4;
438 u8 e15:1;
439 u16 rsvd0;
440 u8 hash_bytes:1;
441 u8 hash_length:6;
442 u8 generic_bytes:1;
443 u8 checksum:1;
444 u8 next_header:1;
445 u8 length:1;
446
447 u16 application_id;
448 u16 rsvd1;
449
450 u32 rsvd2;
451 } __packed;
452
453
454
455 struct safexcel_result_desc {
456 u32 particle_size:17;
457 u8 rsvd0:3;
458 u8 descriptor_overflow:1;
459 u8 buffer_overflow:1;
460 u8 last_seg:1;
461 u8 first_seg:1;
462 u16 result_size:8;
463
464 u32 rsvd1;
465
466 u32 data_lo;
467 u32 data_hi;
468
469 struct result_data_desc result_data;
470 } __packed;
471
472
473
474
475
476 #define EIP197_RD64_FETCH_SIZE ((sizeof(struct safexcel_result_desc) -\
477 sizeof(struct result_data_desc)) /\
478 sizeof(u32))
479
480 struct safexcel_token {
481 u32 packet_length:17;
482 u8 stat:2;
483 u16 instructions:9;
484 u8 opcode:4;
485 } __packed;
486
487 #define EIP197_TOKEN_HASH_RESULT_VERIFY BIT(16)
488
489 #define EIP197_TOKEN_CTX_OFFSET(x) (x)
490 #define EIP197_TOKEN_DIRECTION_EXTERNAL BIT(11)
491 #define EIP197_TOKEN_EXEC_IF_SUCCESSFUL (0x1 << 12)
492
493 #define EIP197_TOKEN_STAT_LAST_HASH BIT(0)
494 #define EIP197_TOKEN_STAT_LAST_PACKET BIT(1)
495 #define EIP197_TOKEN_OPCODE_DIRECTION 0x0
496 #define EIP197_TOKEN_OPCODE_INSERT 0x2
497 #define EIP197_TOKEN_OPCODE_NOOP EIP197_TOKEN_OPCODE_INSERT
498 #define EIP197_TOKEN_OPCODE_RETRIEVE 0x4
499 #define EIP197_TOKEN_OPCODE_INSERT_REMRES 0xa
500 #define EIP197_TOKEN_OPCODE_VERIFY 0xd
501 #define EIP197_TOKEN_OPCODE_CTX_ACCESS 0xe
502 #define EIP197_TOKEN_OPCODE_BYPASS GENMASK(3, 0)
503
504 static inline void eip197_noop_token(struct safexcel_token *token)
505 {
506 token->opcode = EIP197_TOKEN_OPCODE_NOOP;
507 token->packet_length = BIT(2);
508 }
509
510
511 #define EIP197_TOKEN_INS_INSERT_HASH_DIGEST 0x1c
512 #define EIP197_TOKEN_INS_ORIGIN_IV0 0x14
513 #define EIP197_TOKEN_INS_ORIGIN_TOKEN 0x1b
514 #define EIP197_TOKEN_INS_ORIGIN_LEN(x) ((x) << 5)
515 #define EIP197_TOKEN_INS_TYPE_OUTPUT BIT(5)
516 #define EIP197_TOKEN_INS_TYPE_HASH BIT(6)
517 #define EIP197_TOKEN_INS_TYPE_CRYPTO BIT(7)
518 #define EIP197_TOKEN_INS_LAST BIT(8)
519
520
521 struct safexcel_control_data_desc {
522 u32 packet_length:17;
523 u16 options:13;
524 u8 type:2;
525
526 u16 application_id;
527 u16 rsvd;
528
529 u8 refresh:2;
530 u32 context_lo:30;
531 u32 context_hi;
532
533 u32 control0;
534 u32 control1;
535
536 u32 token[EIP197_MAX_TOKENS];
537 } __packed;
538
539 #define EIP197_OPTION_MAGIC_VALUE BIT(0)
540 #define EIP197_OPTION_64BIT_CTX BIT(1)
541 #define EIP197_OPTION_RC_AUTO (0x2 << 3)
542 #define EIP197_OPTION_CTX_CTRL_IN_CMD BIT(8)
543 #define EIP197_OPTION_2_TOKEN_IV_CMD GENMASK(11, 10)
544 #define EIP197_OPTION_4_TOKEN_IV_CMD GENMASK(11, 9)
545
546 #define EIP197_TYPE_EXTENDED 0x3
547
548
549 struct safexcel_command_desc {
550 u32 particle_size:17;
551 u8 rsvd0:5;
552 u8 last_seg:1;
553 u8 first_seg:1;
554 u16 additional_cdata_size:8;
555
556 u32 rsvd1;
557
558 u32 data_lo;
559 u32 data_hi;
560
561 struct safexcel_control_data_desc control_data;
562 } __packed;
563
564
565
566
567
568 #define EIP197_FW_TERMINAL_NOPS 2
569 #define EIP197_FW_START_POLLCNT 16
570 #define EIP197_FW_PUE_READY 0x14
571 #define EIP197_FW_FPP_READY 0x18
572
573 enum eip197_fw {
574 FW_IFPP = 0,
575 FW_IPUE,
576 FW_NB
577 };
578
579 struct safexcel_desc_ring {
580 void *base;
581 void *base_end;
582 dma_addr_t base_dma;
583
584
585 void *write;
586 void *read;
587
588
589 unsigned offset;
590 };
591
592 enum safexcel_alg_type {
593 SAFEXCEL_ALG_TYPE_SKCIPHER,
594 SAFEXCEL_ALG_TYPE_AEAD,
595 SAFEXCEL_ALG_TYPE_AHASH,
596 };
597
598 struct safexcel_config {
599 u32 pes;
600 u32 rings;
601
602 u32 cd_size;
603 u32 cd_offset;
604
605 u32 rd_size;
606 u32 rd_offset;
607 };
608
609 struct safexcel_work_data {
610 struct work_struct work;
611 struct safexcel_crypto_priv *priv;
612 int ring;
613 };
614
615 struct safexcel_ring {
616 spinlock_t lock;
617
618 struct workqueue_struct *workqueue;
619 struct safexcel_work_data work_data;
620
621
622 struct safexcel_desc_ring cdr;
623 struct safexcel_desc_ring rdr;
624
625
626 struct crypto_async_request **rdr_req;
627
628
629 struct crypto_queue queue;
630 spinlock_t queue_lock;
631
632
633 int requests;
634
635
636 bool busy;
637
638
639
640
641 struct crypto_async_request *req;
642 struct crypto_async_request *backlog;
643 };
644
645
646 enum safexcel_eip_version {
647
648 EIP97IES_MRVL,
649 EIP197B_MRVL,
650 EIP197D_MRVL,
651 EIP197_DEVBRD
652 };
653
654
655 #define SAFEXCEL_CRA_PRIORITY 300
656
657
658 enum safexcel_eip_algorithms {
659 SAFEXCEL_ALG_BC0 = BIT(5),
660 SAFEXCEL_ALG_SM4 = BIT(6),
661 SAFEXCEL_ALG_SM3 = BIT(7),
662 SAFEXCEL_ALG_CHACHA20 = BIT(8),
663 SAFEXCEL_ALG_POLY1305 = BIT(9),
664 SAFEXCEL_SEQMASK_256 = BIT(10),
665 SAFEXCEL_SEQMASK_384 = BIT(11),
666 SAFEXCEL_ALG_AES = BIT(12),
667 SAFEXCEL_ALG_AES_XFB = BIT(13),
668 SAFEXCEL_ALG_DES = BIT(15),
669 SAFEXCEL_ALG_DES_XFB = BIT(16),
670 SAFEXCEL_ALG_ARC4 = BIT(18),
671 SAFEXCEL_ALG_AES_XTS = BIT(20),
672 SAFEXCEL_ALG_WIRELESS = BIT(21),
673 SAFEXCEL_ALG_MD5 = BIT(22),
674 SAFEXCEL_ALG_SHA1 = BIT(23),
675 SAFEXCEL_ALG_SHA2_256 = BIT(25),
676 SAFEXCEL_ALG_SHA2_512 = BIT(26),
677 SAFEXCEL_ALG_XCBC_MAC = BIT(27),
678 SAFEXCEL_ALG_CBC_MAC_ALL = BIT(29),
679 SAFEXCEL_ALG_GHASH = BIT(30),
680 SAFEXCEL_ALG_SHA3 = BIT(31),
681 };
682
683 struct safexcel_register_offsets {
684 u32 hia_aic;
685 u32 hia_aic_g;
686 u32 hia_aic_r;
687 u32 hia_aic_xdr;
688 u32 hia_dfe;
689 u32 hia_dfe_thr;
690 u32 hia_dse;
691 u32 hia_dse_thr;
692 u32 hia_gen_cfg;
693 u32 pe;
694 u32 global;
695 };
696
697 enum safexcel_flags {
698 EIP197_TRC_CACHE = BIT(0),
699 SAFEXCEL_HW_EIP197 = BIT(1),
700 };
701
702 struct safexcel_hwconfig {
703 enum safexcel_eip_algorithms algo_flags;
704 int hwver;
705 int hiaver;
706 int pever;
707 int hwdataw;
708 int hwcfsize;
709 int hwrfsize;
710 };
711
712 struct safexcel_crypto_priv {
713 void __iomem *base;
714 struct device *dev;
715 struct clk *clk;
716 struct clk *reg_clk;
717 struct safexcel_config config;
718
719 enum safexcel_eip_version version;
720 struct safexcel_register_offsets offsets;
721 struct safexcel_hwconfig hwconfig;
722 u32 flags;
723
724
725 struct dma_pool *context_pool;
726
727 atomic_t ring_used;
728
729 struct safexcel_ring *ring;
730 };
731
732 struct safexcel_context {
733 int (*send)(struct crypto_async_request *req, int ring,
734 int *commands, int *results);
735 int (*handle_result)(struct safexcel_crypto_priv *priv, int ring,
736 struct crypto_async_request *req, bool *complete,
737 int *ret);
738 struct safexcel_context_record *ctxr;
739 dma_addr_t ctxr_dma;
740
741 int ring;
742 bool needs_inv;
743 bool exit_inv;
744 };
745
746 #define HASH_CACHE_SIZE SHA512_BLOCK_SIZE
747
748 struct safexcel_ahash_export_state {
749 u64 len;
750 u64 processed;
751
752 u32 digest;
753
754 u32 state[SHA512_DIGEST_SIZE / sizeof(u32)];
755 u8 cache[HASH_CACHE_SIZE];
756 };
757
758
759
760
761
762
763 struct safexcel_alg_template {
764 struct safexcel_crypto_priv *priv;
765 enum safexcel_alg_type type;
766 enum safexcel_eip_algorithms algo_mask;
767 union {
768 struct skcipher_alg skcipher;
769 struct aead_alg aead;
770 struct ahash_alg ahash;
771 } alg;
772 };
773
774 struct safexcel_inv_result {
775 struct completion completion;
776 int error;
777 };
778
779 void safexcel_dequeue(struct safexcel_crypto_priv *priv, int ring);
780 int safexcel_rdesc_check_errors(struct safexcel_crypto_priv *priv,
781 struct safexcel_result_desc *rdesc);
782 void safexcel_complete(struct safexcel_crypto_priv *priv, int ring);
783 int safexcel_invalidate_cache(struct crypto_async_request *async,
784 struct safexcel_crypto_priv *priv,
785 dma_addr_t ctxr_dma, int ring);
786 int safexcel_init_ring_descriptors(struct safexcel_crypto_priv *priv,
787 struct safexcel_desc_ring *cdr,
788 struct safexcel_desc_ring *rdr);
789 int safexcel_select_ring(struct safexcel_crypto_priv *priv);
790 void *safexcel_ring_next_rptr(struct safexcel_crypto_priv *priv,
791 struct safexcel_desc_ring *ring);
792 void *safexcel_ring_first_rptr(struct safexcel_crypto_priv *priv, int ring);
793 void safexcel_ring_rollback_wptr(struct safexcel_crypto_priv *priv,
794 struct safexcel_desc_ring *ring);
795 struct safexcel_command_desc *safexcel_add_cdesc(struct safexcel_crypto_priv *priv,
796 int ring_id,
797 bool first, bool last,
798 dma_addr_t data, u32 len,
799 u32 full_data_len,
800 dma_addr_t context);
801 struct safexcel_result_desc *safexcel_add_rdesc(struct safexcel_crypto_priv *priv,
802 int ring_id,
803 bool first, bool last,
804 dma_addr_t data, u32 len);
805 int safexcel_ring_first_rdr_index(struct safexcel_crypto_priv *priv,
806 int ring);
807 int safexcel_ring_rdr_rdesc_index(struct safexcel_crypto_priv *priv,
808 int ring,
809 struct safexcel_result_desc *rdesc);
810 void safexcel_rdr_req_set(struct safexcel_crypto_priv *priv,
811 int ring,
812 struct safexcel_result_desc *rdesc,
813 struct crypto_async_request *req);
814 inline struct crypto_async_request *
815 safexcel_rdr_req_get(struct safexcel_crypto_priv *priv, int ring);
816 void safexcel_inv_complete(struct crypto_async_request *req, int error);
817 int safexcel_hmac_setkey(const char *alg, const u8 *key, unsigned int keylen,
818 void *istate, void *ostate);
819
820
821 extern struct safexcel_alg_template safexcel_alg_ecb_des;
822 extern struct safexcel_alg_template safexcel_alg_cbc_des;
823 extern struct safexcel_alg_template safexcel_alg_ecb_des3_ede;
824 extern struct safexcel_alg_template safexcel_alg_cbc_des3_ede;
825 extern struct safexcel_alg_template safexcel_alg_ecb_aes;
826 extern struct safexcel_alg_template safexcel_alg_cbc_aes;
827 extern struct safexcel_alg_template safexcel_alg_cfb_aes;
828 extern struct safexcel_alg_template safexcel_alg_ofb_aes;
829 extern struct safexcel_alg_template safexcel_alg_ctr_aes;
830 extern struct safexcel_alg_template safexcel_alg_md5;
831 extern struct safexcel_alg_template safexcel_alg_sha1;
832 extern struct safexcel_alg_template safexcel_alg_sha224;
833 extern struct safexcel_alg_template safexcel_alg_sha256;
834 extern struct safexcel_alg_template safexcel_alg_sha384;
835 extern struct safexcel_alg_template safexcel_alg_sha512;
836 extern struct safexcel_alg_template safexcel_alg_hmac_md5;
837 extern struct safexcel_alg_template safexcel_alg_hmac_sha1;
838 extern struct safexcel_alg_template safexcel_alg_hmac_sha224;
839 extern struct safexcel_alg_template safexcel_alg_hmac_sha256;
840 extern struct safexcel_alg_template safexcel_alg_hmac_sha384;
841 extern struct safexcel_alg_template safexcel_alg_hmac_sha512;
842 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_aes;
843 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_cbc_aes;
844 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_cbc_aes;
845 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_cbc_aes;
846 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_cbc_aes;
847 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_des3_ede;
848 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_ctr_aes;
849 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_ctr_aes;
850 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_ctr_aes;
851 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_ctr_aes;
852 extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_ctr_aes;
853 extern struct safexcel_alg_template safexcel_alg_xts_aes;
854 extern struct safexcel_alg_template safexcel_alg_gcm;
855 extern struct safexcel_alg_template safexcel_alg_ccm;
856
857 #endif