root/drivers/crypto/caam/regs.h

INCLUDED FROM

DEFINITIONS

1. caam_to_cpu
2. rd_reg32
3. clrsetbits_32
4. wr_reg64
5. rd_reg64
6. cpu_to_caam_dma64
7. caam_dma64_to_cpu
8. cpu_to_caam_dma
9. caam_dma_to_cpu
10. jr_outentry_get
11. jr_outentry_desc
12. jr_outentry_jrstatus
13. jr_inpentry_set

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * CAAM hardware register-level view
   4  *
   5  * Copyright 2008-2011 Freescale Semiconductor, Inc.
   6  * Copyright 2018 NXP
   7  */
   8 
   9 #ifndef REGS_H
  10 #define REGS_H
  11 
  12 #include <linux/types.h>
  13 #include <linux/bitops.h>
  14 #include <linux/io.h>
  15 #include <linux/io-64-nonatomic-hi-lo.h>
  16 
  17 /*
  18  * Architecture-specific register access methods
  19  *
  20  * CAAM's bus-addressable registers are 64 bits internally.
  21  * They have been wired to be safely accessible on 32-bit
  22  * architectures, however. Registers were organized such
  23  * that (a) they can be contained in 32 bits, (b) if not, then they
  24  * can be treated as two 32-bit entities, or finally (c) if they
  25  * must be treated as a single 64-bit value, then this can safely
  26  * be done with two 32-bit cycles.
  27  *
  28  * For 32-bit operations on 64-bit values, CAAM follows the same
  29  * 64-bit register access conventions as it's predecessors, in that
  30  * writes are "triggered" by a write to the register at the numerically
  31  * higher address, thus, a full 64-bit write cycle requires a write
  32  * to the lower address, followed by a write to the higher address,
  33  * which will latch/execute the write cycle.
  34  *
  35  * For example, let's assume a SW reset of CAAM through the master
  36  * configuration register.
  37  * - SWRST is in bit 31 of MCFG.
  38  * - MCFG begins at base+0x0000.
  39  * - Bits 63-32 are a 32-bit word at base+0x0000 (numerically-lower)
  40  * - Bits 31-0 are a 32-bit word at base+0x0004 (numerically-higher)
  41  *
  42  * (and on Power, the convention is 0-31, 32-63, I know...)
  43  *
  44  * Assuming a 64-bit write to this MCFG to perform a software reset
  45  * would then require a write of 0 to base+0x0000, followed by a
  46  * write of 0x80000000 to base+0x0004, which would "execute" the
  47  * reset.
  48  *
  49  * Of course, since MCFG 63-32 is all zero, we could cheat and simply
  50  * write 0x8000000 to base+0x0004, and the reset would work fine.
  51  * However, since CAAM does contain some write-and-read-intended
  52  * 64-bit registers, this code defines 64-bit access methods for
  53  * the sake of internal consistency and simplicity, and so that a
  54  * clean transition to 64-bit is possible when it becomes necessary.
  55  *
  56  * There are limitations to this that the developer must recognize.
  57  * 32-bit architectures cannot enforce an atomic-64 operation,
  58  * Therefore:
  59  *
  60  * - On writes, since the HW is assumed to latch the cycle on the
  61  *   write of the higher-numeric-address word, then ordered
  62  *   writes work OK.
  63  *
  64  * - For reads, where a register contains a relevant value of more
  65  *   that 32 bits, the hardware employs logic to latch the other
  66  *   "half" of the data until read, ensuring an accurate value.
  67  *   This is of particular relevance when dealing with CAAM's
  68  *   performance counters.
  69  *
  70  */
  71 
  72 extern bool caam_little_end;
  73 extern bool caam_imx;
  74 extern size_t caam_ptr_sz;
  75 
  76 #define caam_to_cpu(len)                                                \
  77 static inline u##len caam##len ## _to_cpu(u##len val)                   \
  78 {                                                                       \
  79         if (caam_little_end)                                            \
  80                 return le##len ## _to_cpu((__force __le##len)val);      \
  81         else                                                            \
  82                 return be##len ## _to_cpu((__force __be##len)val);      \
  83 }
  84 
  85 #define cpu_to_caam(len)                                        \
  86 static inline u##len cpu_to_caam##len(u##len val)               \
  87 {                                                               \
  88         if (caam_little_end)                                    \
  89                 return (__force u##len)cpu_to_le##len(val);     \
  90         else                                                    \
  91                 return (__force u##len)cpu_to_be##len(val);     \
  92 }
  93 
  94 caam_to_cpu(16)
  95 caam_to_cpu(32)
  96 caam_to_cpu(64)
  97 cpu_to_caam(16)
  98 cpu_to_caam(32)
  99 cpu_to_caam(64)
 100 
 101 static inline void wr_reg32(void __iomem *reg, u32 data)
 102 {
 103         if (caam_little_end)
 104                 iowrite32(data, reg);
 105         else
 106                 iowrite32be(data, reg);
 107 }
 108 
 109 static inline u32 rd_reg32(void __iomem *reg)
 110 {
 111         if (caam_little_end)
 112                 return ioread32(reg);
 113 
 114         return ioread32be(reg);
 115 }
 116 
 117 static inline void clrsetbits_32(void __iomem *reg, u32 clear, u32 set)
 118 {
 119         if (caam_little_end)
 120                 iowrite32((ioread32(reg) & ~clear) | set, reg);
 121         else
 122                 iowrite32be((ioread32be(reg) & ~clear) | set, reg);
 123 }
 124 
 125 /*
 126  * The only users of these wr/rd_reg64 functions is the Job Ring (JR).
 127  * The DMA address registers in the JR are handled differently depending on
 128  * platform:
 129  *
 130  * 1. All BE CAAM platforms and i.MX platforms (LE CAAM):
 131  *
 132  *    base + 0x0000 : most-significant 32 bits
 133  *    base + 0x0004 : least-significant 32 bits
 134  *
 135  * The 32-bit version of this core therefore has to write to base + 0x0004
 136  * to set the 32-bit wide DMA address.
 137  *
 138  * 2. All other LE CAAM platforms (LS1021A etc.)
 139  *    base + 0x0000 : least-significant 32 bits
 140  *    base + 0x0004 : most-significant 32 bits
 141  */
 142 static inline void wr_reg64(void __iomem *reg, u64 data)
 143 {
 144         if (caam_little_end) {
 145                 if (caam_imx) {
 146                         iowrite32(data >> 32, (u32 __iomem *)(reg));
 147                         iowrite32(data, (u32 __iomem *)(reg) + 1);
 148                 } else {
 149                         iowrite64(data, reg);
 150                 }
 151         } else {
 152                 iowrite64be(data, reg);
 153         }
 154 }
 155 
 156 static inline u64 rd_reg64(void __iomem *reg)
 157 {
 158         if (caam_little_end) {
 159                 if (caam_imx) {
 160                         u32 low, high;
 161 
 162                         high = ioread32(reg);
 163                         low  = ioread32(reg + sizeof(u32));
 164 
 165                         return low + ((u64)high << 32);
 166                 } else {
 167                         return ioread64(reg);
 168                 }
 169         } else {
 170                 return ioread64be(reg);
 171         }
 172 }
 173 
 174 static inline u64 cpu_to_caam_dma64(dma_addr_t value)
 175 {
 176         if (caam_imx)
 177                 return (((u64)cpu_to_caam32(lower_32_bits(value)) << 32) |
 178                          (u64)cpu_to_caam32(upper_32_bits(value)));
 179 
 180         return cpu_to_caam64(value);
 181 }
 182 
 183 static inline u64 caam_dma64_to_cpu(u64 value)
 184 {
 185         if (caam_imx)
 186                 return (((u64)caam32_to_cpu(lower_32_bits(value)) << 32) |
 187                          (u64)caam32_to_cpu(upper_32_bits(value)));
 188 
 189         return caam64_to_cpu(value);
 190 }
 191 
 192 static inline u64 cpu_to_caam_dma(u64 value)
 193 {
 194         if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) &&
 195             caam_ptr_sz == sizeof(u64))
 196                 return cpu_to_caam_dma64(value);
 197         else
 198                 return cpu_to_caam32(value);
 199 }
 200 
 201 static inline u64 caam_dma_to_cpu(u64 value)
 202 {
 203         if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) &&
 204             caam_ptr_sz == sizeof(u64))
 205                 return caam_dma64_to_cpu(value);
 206         else
 207                 return caam32_to_cpu(value);
 208 }
 209 
 210 /*
 211  * jr_outentry
 212  * Represents each entry in a JobR output ring
 213  */
 214 
 215 static inline void jr_outentry_get(void *outring, int hw_idx, dma_addr_t *desc,
 216                                    u32 *jrstatus)
 217 {
 218 
 219         if (caam_ptr_sz == sizeof(u32)) {
 220                 struct {
 221                         u32 desc;
 222                         u32 jrstatus;
 223                 } __packed *outentry = outring;
 224 
 225                 *desc = outentry[hw_idx].desc;
 226                 *jrstatus = outentry[hw_idx].jrstatus;
 227         } else {
 228                 struct {
 229                         dma_addr_t desc;/* Pointer to completed descriptor */
 230                         u32 jrstatus;   /* Status for completed descriptor */
 231                 } __packed *outentry = outring;
 232 
 233                 *desc = outentry[hw_idx].desc;
 234                 *jrstatus = outentry[hw_idx].jrstatus;
 235         }
 236 }
 237 
 238 #define SIZEOF_JR_OUTENTRY      (caam_ptr_sz + sizeof(u32))
 239 
 240 static inline dma_addr_t jr_outentry_desc(void *outring, int hw_idx)
 241 {
 242         dma_addr_t desc;
 243         u32 unused;
 244 
 245         jr_outentry_get(outring, hw_idx, &desc, &unused);
 246 
 247         return desc;
 248 }
 249 
 250 static inline u32 jr_outentry_jrstatus(void *outring, int hw_idx)
 251 {
 252         dma_addr_t unused;
 253         u32 jrstatus;
 254 
 255         jr_outentry_get(outring, hw_idx, &unused, &jrstatus);
 256 
 257         return jrstatus;
 258 }
 259 
 260 static inline void jr_inpentry_set(void *inpring, int hw_idx, dma_addr_t val)
 261 {
 262         if (caam_ptr_sz == sizeof(u32)) {
 263                 u32 *inpentry = inpring;
 264 
 265                 inpentry[hw_idx] = val;
 266         } else {
 267                 dma_addr_t *inpentry = inpring;
 268 
 269                 inpentry[hw_idx] = val;
 270         }
 271 }
 272 
 273 #define SIZEOF_JR_INPENTRY      caam_ptr_sz
 274 
 275 
 276 /* Version registers (Era 10+)  e80-eff */
 277 struct version_regs {
 278         u32 crca;       /* CRCA_VERSION */
 279         u32 afha;       /* AFHA_VERSION */
 280         u32 kfha;       /* KFHA_VERSION */
 281         u32 pkha;       /* PKHA_VERSION */
 282         u32 aesa;       /* AESA_VERSION */
 283         u32 mdha;       /* MDHA_VERSION */
 284         u32 desa;       /* DESA_VERSION */
 285         u32 snw8a;      /* SNW8A_VERSION */
 286         u32 snw9a;      /* SNW9A_VERSION */
 287         u32 zuce;       /* ZUCE_VERSION */
 288         u32 zuca;       /* ZUCA_VERSION */
 289         u32 ccha;       /* CCHA_VERSION */
 290         u32 ptha;       /* PTHA_VERSION */
 291         u32 rng;        /* RNG_VERSION */
 292         u32 trng;       /* TRNG_VERSION */
 293         u32 aaha;       /* AAHA_VERSION */
 294         u32 rsvd[10];
 295         u32 sr;         /* SR_VERSION */
 296         u32 dma;        /* DMA_VERSION */
 297         u32 ai;         /* AI_VERSION */
 298         u32 qi;         /* QI_VERSION */
 299         u32 jr;         /* JR_VERSION */
 300         u32 deco;       /* DECO_VERSION */
 301 };
 302 
 303 /* Version registers bitfields */
 304 
 305 /* Number of CHAs instantiated */
 306 #define CHA_VER_NUM_MASK        0xffull
 307 /* CHA Miscellaneous Information */
 308 #define CHA_VER_MISC_SHIFT      8
 309 #define CHA_VER_MISC_MASK       (0xffull << CHA_VER_MISC_SHIFT)
 310 /* CHA Revision Number */
 311 #define CHA_VER_REV_SHIFT       16
 312 #define CHA_VER_REV_MASK        (0xffull << CHA_VER_REV_SHIFT)
 313 /* CHA Version ID */
 314 #define CHA_VER_VID_SHIFT       24
 315 #define CHA_VER_VID_MASK        (0xffull << CHA_VER_VID_SHIFT)
 316 
 317 /* CHA Miscellaneous Information - AESA_MISC specific */
 318 #define CHA_VER_MISC_AES_GCM    BIT(1 + CHA_VER_MISC_SHIFT)
 319 
 320 /*
 321  * caam_perfmon - Performance Monitor/Secure Memory Status/
 322  *                CAAM Global Status/Component Version IDs
 323  *
 324  * Spans f00-fff wherever instantiated
 325  */
 326 
 327 /* Number of DECOs */
 328 #define CHA_NUM_MS_DECONUM_SHIFT        24
 329 #define CHA_NUM_MS_DECONUM_MASK (0xfull << CHA_NUM_MS_DECONUM_SHIFT)
 330 
 331 /*
 332  * CHA version IDs / instantiation bitfields (< Era 10)
 333  * Defined for use with the cha_id fields in perfmon, but the same shift/mask
 334  * selectors can be used to pull out the number of instantiated blocks within
 335  * cha_num fields in perfmon because the locations are the same.
 336  */
 337 #define CHA_ID_LS_AES_SHIFT     0
 338 #define CHA_ID_LS_AES_MASK      (0xfull << CHA_ID_LS_AES_SHIFT)
 339 
 340 #define CHA_ID_LS_DES_SHIFT     4
 341 #define CHA_ID_LS_DES_MASK      (0xfull << CHA_ID_LS_DES_SHIFT)
 342 
 343 #define CHA_ID_LS_ARC4_SHIFT    8
 344 #define CHA_ID_LS_ARC4_MASK     (0xfull << CHA_ID_LS_ARC4_SHIFT)
 345 
 346 #define CHA_ID_LS_MD_SHIFT      12
 347 #define CHA_ID_LS_MD_MASK       (0xfull << CHA_ID_LS_MD_SHIFT)
 348 
 349 #define CHA_ID_LS_RNG_SHIFT     16
 350 #define CHA_ID_LS_RNG_MASK      (0xfull << CHA_ID_LS_RNG_SHIFT)
 351 
 352 #define CHA_ID_LS_SNW8_SHIFT    20
 353 #define CHA_ID_LS_SNW8_MASK     (0xfull << CHA_ID_LS_SNW8_SHIFT)
 354 
 355 #define CHA_ID_LS_KAS_SHIFT     24
 356 #define CHA_ID_LS_KAS_MASK      (0xfull << CHA_ID_LS_KAS_SHIFT)
 357 
 358 #define CHA_ID_LS_PK_SHIFT      28
 359 #define CHA_ID_LS_PK_MASK       (0xfull << CHA_ID_LS_PK_SHIFT)
 360 
 361 #define CHA_ID_MS_CRC_SHIFT     0
 362 #define CHA_ID_MS_CRC_MASK      (0xfull << CHA_ID_MS_CRC_SHIFT)
 363 
 364 #define CHA_ID_MS_SNW9_SHIFT    4
 365 #define CHA_ID_MS_SNW9_MASK     (0xfull << CHA_ID_MS_SNW9_SHIFT)
 366 
 367 #define CHA_ID_MS_DECO_SHIFT    24
 368 #define CHA_ID_MS_DECO_MASK     (0xfull << CHA_ID_MS_DECO_SHIFT)
 369 
 370 #define CHA_ID_MS_JR_SHIFT      28
 371 #define CHA_ID_MS_JR_MASK       (0xfull << CHA_ID_MS_JR_SHIFT)
 372 
 373 /* Specific CHA version IDs */
 374 #define CHA_VER_VID_AES_LP      0x3ull
 375 #define CHA_VER_VID_AES_HP      0x4ull
 376 #define CHA_VER_VID_MD_LP256    0x0ull
 377 #define CHA_VER_VID_MD_LP512    0x1ull
 378 #define CHA_VER_VID_MD_HP       0x2ull
 379 
 380 struct sec_vid {
 381         u16 ip_id;
 382         u8 maj_rev;
 383         u8 min_rev;
 384 };
 385 
 386 struct caam_perfmon {
 387         /* Performance Monitor Registers                        f00-f9f */
 388         u64 req_dequeued;       /* PC_REQ_DEQ - Dequeued Requests            */
 389         u64 ob_enc_req; /* PC_OB_ENC_REQ - Outbound Encrypt Requests */
 390         u64 ib_dec_req; /* PC_IB_DEC_REQ - Inbound Decrypt Requests  */
 391         u64 ob_enc_bytes;       /* PC_OB_ENCRYPT - Outbound Bytes Encrypted  */
 392         u64 ob_prot_bytes;      /* PC_OB_PROTECT - Outbound Bytes Protected  */
 393         u64 ib_dec_bytes;       /* PC_IB_DECRYPT - Inbound Bytes Decrypted   */
 394         u64 ib_valid_bytes;     /* PC_IB_VALIDATED Inbound Bytes Validated   */
 395         u64 rsvd[13];
 396 
 397         /* CAAM Hardware Instantiation Parameters               fa0-fbf */
 398         u32 cha_rev_ms;         /* CRNR - CHA Rev No. Most significant half*/
 399         u32 cha_rev_ls;         /* CRNR - CHA Rev No. Least significant half*/
 400 #define CTPR_MS_QI_SHIFT        25
 401 #define CTPR_MS_QI_MASK         (0x1ull << CTPR_MS_QI_SHIFT)
 402 #define CTPR_MS_PS              BIT(17)
 403 #define CTPR_MS_DPAA2           BIT(13)
 404 #define CTPR_MS_VIRT_EN_INCL    0x00000001
 405 #define CTPR_MS_VIRT_EN_POR     0x00000002
 406 #define CTPR_MS_PG_SZ_MASK      0x10
 407 #define CTPR_MS_PG_SZ_SHIFT     4
 408         u32 comp_parms_ms;      /* CTPR - Compile Parameters Register   */
 409         u32 comp_parms_ls;      /* CTPR - Compile Parameters Register   */
 410         u64 rsvd1[2];
 411 
 412         /* CAAM Global Status                                   fc0-fdf */
 413         u64 faultaddr;  /* FAR  - Fault Address         */
 414         u32 faultliodn; /* FALR - Fault Address LIODN   */
 415         u32 faultdetail;        /* FADR - Fault Addr Detail     */
 416         u32 rsvd2;
 417 #define CSTA_PLEND              BIT(10)
 418 #define CSTA_ALT_PLEND          BIT(18)
 419         u32 status;             /* CSTA - CAAM Status */
 420         u64 rsvd3;
 421 
 422         /* Component Instantiation Parameters                   fe0-fff */
 423         u32 rtic_id;            /* RVID - RTIC Version ID       */
 424 #define CCBVID_ERA_MASK         0xff000000
 425 #define CCBVID_ERA_SHIFT        24
 426         u32 ccb_id;             /* CCBVID - CCB Version ID      */
 427         u32 cha_id_ms;          /* CHAVID - CHA Version ID Most Significant*/
 428         u32 cha_id_ls;          /* CHAVID - CHA Version ID Least Significant*/
 429         u32 cha_num_ms;         /* CHANUM - CHA Number Most Significant */
 430         u32 cha_num_ls;         /* CHANUM - CHA Number Least Significant*/
 431 #define SECVID_MS_IPID_MASK     0xffff0000
 432 #define SECVID_MS_IPID_SHIFT    16
 433 #define SECVID_MS_MAJ_REV_MASK  0x0000ff00
 434 #define SECVID_MS_MAJ_REV_SHIFT 8
 435         u32 caam_id_ms;         /* CAAMVID - CAAM Version ID MS */
 436         u32 caam_id_ls;         /* CAAMVID - CAAM Version ID LS */
 437 };
 438 
 439 /* LIODN programming for DMA configuration */
 440 #define MSTRID_LOCK_LIODN       0x80000000
 441 #define MSTRID_LOCK_MAKETRUSTED 0x00010000      /* only for JR masterid */
 442 
 443 #define MSTRID_LIODN_MASK       0x0fff
 444 struct masterid {
 445         u32 liodn_ms;   /* lock and make-trusted control bits */
 446         u32 liodn_ls;   /* LIODN for non-sequence and seq access */
 447 };
 448 
 449 /* Partition ID for DMA configuration */
 450 struct partid {
 451         u32 rsvd1;
 452         u32 pidr;       /* partition ID, DECO */
 453 };
 454 
 455 /* RNGB test mode (replicated twice in some configurations) */
 456 /* Padded out to 0x100 */
 457 struct rngtst {
 458         u32 mode;               /* RTSTMODEx - Test mode */
 459         u32 rsvd1[3];
 460         u32 reset;              /* RTSTRESETx - Test reset control */
 461         u32 rsvd2[3];
 462         u32 status;             /* RTSTSSTATUSx - Test status */
 463         u32 rsvd3;
 464         u32 errstat;            /* RTSTERRSTATx - Test error status */
 465         u32 rsvd4;
 466         u32 errctl;             /* RTSTERRCTLx - Test error control */
 467         u32 rsvd5;
 468         u32 entropy;            /* RTSTENTROPYx - Test entropy */
 469         u32 rsvd6[15];
 470         u32 verifctl;   /* RTSTVERIFCTLx - Test verification control */
 471         u32 rsvd7;
 472         u32 verifstat;  /* RTSTVERIFSTATx - Test verification status */
 473         u32 rsvd8;
 474         u32 verifdata;  /* RTSTVERIFDx - Test verification data */
 475         u32 rsvd9;
 476         u32 xkey;               /* RTSTXKEYx - Test XKEY */
 477         u32 rsvd10;
 478         u32 oscctctl;   /* RTSTOSCCTCTLx - Test osc. counter control */
 479         u32 rsvd11;
 480         u32 oscct;              /* RTSTOSCCTx - Test oscillator counter */
 481         u32 rsvd12;
 482         u32 oscctstat;  /* RTSTODCCTSTATx - Test osc counter status */
 483         u32 rsvd13[2];
 484         u32 ofifo[4];   /* RTSTOFIFOx - Test output FIFO */
 485         u32 rsvd14[15];
 486 };
 487 
 488 /* RNG4 TRNG test registers */
 489 struct rng4tst {
 490 #define RTMCTL_PRGM     0x00010000      /* 1 -> program mode, 0 -> run mode */
 491 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC      0 /* use von Neumann data in
 492                                                      both entropy shifter and
 493                                                      statistical checker */
 494 #define RTMCTL_SAMP_MODE_RAW_ES_SC              1 /* use raw data in both
 495                                                      entropy shifter and
 496                                                      statistical checker */
 497 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC  2 /* use von Neumann data in
 498                                                      entropy shifter, raw data
 499                                                      in statistical checker */
 500 #define RTMCTL_SAMP_MODE_INVALID                3 /* invalid combination */
 501         u32 rtmctl;             /* misc. control register */
 502         u32 rtscmisc;           /* statistical check misc. register */
 503         u32 rtpkrrng;           /* poker range register */
 504         union {
 505                 u32 rtpkrmax;   /* PRGM=1: poker max. limit register */
 506                 u32 rtpkrsq;    /* PRGM=0: poker square calc. result register */
 507         };
 508 #define RTSDCTL_ENT_DLY_SHIFT 16
 509 #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
 510 #define RTSDCTL_ENT_DLY_MIN 3200
 511 #define RTSDCTL_ENT_DLY_MAX 12800
 512         u32 rtsdctl;            /* seed control register */
 513         union {
 514                 u32 rtsblim;    /* PRGM=1: sparse bit limit register */
 515                 u32 rttotsam;   /* PRGM=0: total samples register */
 516         };
 517         u32 rtfrqmin;           /* frequency count min. limit register */
 518 #define RTFRQMAX_DISABLE        (1 << 20)
 519         union {
 520                 u32 rtfrqmax;   /* PRGM=1: freq. count max. limit register */
 521                 u32 rtfrqcnt;   /* PRGM=0: freq. count register */
 522         };
 523         u32 rsvd1[40];
 524 #define RDSTA_SKVT 0x80000000
 525 #define RDSTA_SKVN 0x40000000
 526 #define RDSTA_IF0 0x00000001
 527 #define RDSTA_IF1 0x00000002
 528 #define RDSTA_IFMASK (RDSTA_IF1 | RDSTA_IF0)
 529         u32 rdsta;
 530         u32 rsvd2[15];
 531 };
 532 
 533 /*
 534  * caam_ctrl - basic core configuration
 535  * starts base + 0x0000 padded out to 0x1000
 536  */
 537 
 538 #define KEK_KEY_SIZE            8
 539 #define TKEK_KEY_SIZE           8
 540 #define TDSK_KEY_SIZE           8
 541 
 542 #define DECO_RESET      1       /* Use with DECO reset/availability regs */
 543 #define DECO_RESET_0    (DECO_RESET << 0)
 544 #define DECO_RESET_1    (DECO_RESET << 1)
 545 #define DECO_RESET_2    (DECO_RESET << 2)
 546 #define DECO_RESET_3    (DECO_RESET << 3)
 547 #define DECO_RESET_4    (DECO_RESET << 4)
 548 
 549 struct caam_ctrl {
 550         /* Basic Configuration Section                          000-01f */
 551         /* Read/Writable                                                */
 552         u32 rsvd1;
 553         u32 mcr;                /* MCFG      Master Config Register  */
 554         u32 rsvd2;
 555         u32 scfgr;              /* SCFGR, Security Config Register */
 556 
 557         /* Bus Access Configuration Section                     010-11f */
 558         /* Read/Writable                                                */
 559         struct masterid jr_mid[4];      /* JRxLIODNR - JobR LIODN setup */
 560         u32 rsvd3[11];
 561         u32 jrstart;                    /* JRSTART - Job Ring Start Register */
 562         struct masterid rtic_mid[4];    /* RTICxLIODNR - RTIC LIODN setup */
 563         u32 rsvd4[5];
 564         u32 deco_rsr;                   /* DECORSR - Deco Request Source */
 565         u32 rsvd11;
 566         u32 deco_rq;                    /* DECORR - DECO Request */
 567         struct partid deco_mid[5];      /* DECOxLIODNR - 1 per DECO */
 568         u32 rsvd5[22];
 569 
 570         /* DECO Availability/Reset Section                      120-3ff */
 571         u32 deco_avail;         /* DAR - DECO availability */
 572         u32 deco_reset;         /* DRR - DECO reset */
 573         u32 rsvd6[182];
 574 
 575         /* Key Encryption/Decryption Configuration              400-5ff */
 576         /* Read/Writable only while in Non-secure mode                  */
 577         u32 kek[KEK_KEY_SIZE];  /* JDKEKR - Key Encryption Key */
 578         u32 tkek[TKEK_KEY_SIZE];        /* TDKEKR - Trusted Desc KEK */
 579         u32 tdsk[TDSK_KEY_SIZE];        /* TDSKR - Trusted Desc Signing Key */
 580         u32 rsvd7[32];
 581         u64 sknonce;                    /* SKNR - Secure Key Nonce */
 582         u32 rsvd8[70];
 583 
 584         /* RNG Test/Verification/Debug Access                   600-7ff */
 585         /* (Useful in Test/Debug modes only...)                         */
 586         union {
 587                 struct rngtst rtst[2];
 588                 struct rng4tst r4tst[2];
 589         };
 590 
 591         u32 rsvd9[416];
 592 
 593         /* Version registers - introduced with era 10           e80-eff */
 594         struct version_regs vreg;
 595         /* Performance Monitor                                  f00-fff */
 596         struct caam_perfmon perfmon;
 597 };
 598 
 599 /*
 600  * Controller master config register defs
 601  */
 602 #define MCFGR_SWRESET           0x80000000 /* software reset */
 603 #define MCFGR_WDENABLE          0x40000000 /* DECO watchdog enable */
 604 #define MCFGR_WDFAIL            0x20000000 /* DECO watchdog force-fail */
 605 #define MCFGR_DMA_RESET         0x10000000
 606 #define MCFGR_LONG_PTR          0x00010000 /* Use >32-bit desc addressing */
 607 #define SCFGR_RDBENABLE         0x00000400
 608 #define SCFGR_VIRT_EN           0x00008000
 609 #define DECORR_RQD0ENABLE       0x00000001 /* Enable DECO0 for direct access */
 610 #define DECORSR_JR0             0x00000001 /* JR to supply TZ, SDID, ICID */
 611 #define DECORSR_VALID           0x80000000
 612 #define DECORR_DEN0             0x00010000 /* DECO0 available for access*/
 613 
 614 /* AXI read cache control */
 615 #define MCFGR_ARCACHE_SHIFT     12
 616 #define MCFGR_ARCACHE_MASK      (0xf << MCFGR_ARCACHE_SHIFT)
 617 #define MCFGR_ARCACHE_BUFF      (0x1 << MCFGR_ARCACHE_SHIFT)
 618 #define MCFGR_ARCACHE_CACH      (0x2 << MCFGR_ARCACHE_SHIFT)
 619 #define MCFGR_ARCACHE_RALL      (0x4 << MCFGR_ARCACHE_SHIFT)
 620 
 621 /* AXI write cache control */
 622 #define MCFGR_AWCACHE_SHIFT     8
 623 #define MCFGR_AWCACHE_MASK      (0xf << MCFGR_AWCACHE_SHIFT)
 624 #define MCFGR_AWCACHE_BUFF      (0x1 << MCFGR_AWCACHE_SHIFT)
 625 #define MCFGR_AWCACHE_CACH      (0x2 << MCFGR_AWCACHE_SHIFT)
 626 #define MCFGR_AWCACHE_WALL      (0x8 << MCFGR_AWCACHE_SHIFT)
 627 
 628 /* AXI pipeline depth */
 629 #define MCFGR_AXIPIPE_SHIFT     4
 630 #define MCFGR_AXIPIPE_MASK      (0xf << MCFGR_AXIPIPE_SHIFT)
 631 
 632 #define MCFGR_AXIPRI            0x00000008 /* Assert AXI priority sideband */
 633 #define MCFGR_LARGE_BURST       0x00000004 /* 128/256-byte burst size */
 634 #define MCFGR_BURST_64          0x00000001 /* 64-byte burst size */
 635 
 636 /* JRSTART register offsets */
 637 #define JRSTART_JR0_START       0x00000001 /* Start Job ring 0 */
 638 #define JRSTART_JR1_START       0x00000002 /* Start Job ring 1 */
 639 #define JRSTART_JR2_START       0x00000004 /* Start Job ring 2 */
 640 #define JRSTART_JR3_START       0x00000008 /* Start Job ring 3 */
 641 
 642 /*
 643  * caam_job_ring - direct job ring setup
 644  * 1-4 possible per instantiation, base + 1000/2000/3000/4000
 645  * Padded out to 0x1000
 646  */
 647 struct caam_job_ring {
 648         /* Input ring */
 649         u64 inpring_base;       /* IRBAx -  Input desc ring baseaddr */
 650         u32 rsvd1;
 651         u32 inpring_size;       /* IRSx - Input ring size */
 652         u32 rsvd2;
 653         u32 inpring_avail;      /* IRSAx - Input ring room remaining */
 654         u32 rsvd3;
 655         u32 inpring_jobadd;     /* IRJAx - Input ring jobs added */
 656 
 657         /* Output Ring */
 658         u64 outring_base;       /* ORBAx - Output status ring base addr */
 659         u32 rsvd4;
 660         u32 outring_size;       /* ORSx - Output ring size */
 661         u32 rsvd5;
 662         u32 outring_rmvd;       /* ORJRx - Output ring jobs removed */
 663         u32 rsvd6;
 664         u32 outring_used;       /* ORSFx - Output ring slots full */
 665 
 666         /* Status/Configuration */
 667         u32 rsvd7;
 668         u32 jroutstatus;        /* JRSTAx - JobR output status */
 669         u32 rsvd8;
 670         u32 jrintstatus;        /* JRINTx - JobR interrupt status */
 671         u32 rconfig_hi; /* JRxCFG - Ring configuration */
 672         u32 rconfig_lo;
 673 
 674         /* Indices. CAAM maintains as "heads" of each queue */
 675         u32 rsvd9;
 676         u32 inp_rdidx;  /* IRRIx - Input ring read index */
 677         u32 rsvd10;
 678         u32 out_wtidx;  /* ORWIx - Output ring write index */
 679 
 680         /* Command/control */
 681         u32 rsvd11;
 682         u32 jrcommand;  /* JRCRx - JobR command */
 683 
 684         u32 rsvd12[900];
 685 
 686         /* Version registers - introduced with era 10           e80-eff */
 687         struct version_regs vreg;
 688         /* Performance Monitor                                  f00-fff */
 689         struct caam_perfmon perfmon;
 690 };
 691 
 692 #define JR_RINGSIZE_MASK        0x03ff
 693 /*
 694  * jrstatus - Job Ring Output Status
 695  * All values in lo word
 696  * Also note, same values written out as status through QI
 697  * in the command/status field of a frame descriptor
 698  */
 699 #define JRSTA_SSRC_SHIFT            28
 700 #define JRSTA_SSRC_MASK             0xf0000000
 701 
 702 #define JRSTA_SSRC_NONE             0x00000000
 703 #define JRSTA_SSRC_CCB_ERROR        0x20000000
 704 #define JRSTA_SSRC_JUMP_HALT_USER   0x30000000
 705 #define JRSTA_SSRC_DECO             0x40000000
 706 #define JRSTA_SSRC_QI               0x50000000
 707 #define JRSTA_SSRC_JRERROR          0x60000000
 708 #define JRSTA_SSRC_JUMP_HALT_CC     0x70000000
 709 
 710 #define JRSTA_DECOERR_JUMP          0x08000000
 711 #define JRSTA_DECOERR_INDEX_SHIFT   8
 712 #define JRSTA_DECOERR_INDEX_MASK    0xff00
 713 #define JRSTA_DECOERR_ERROR_MASK    0x00ff
 714 
 715 #define JRSTA_DECOERR_NONE          0x00
 716 #define JRSTA_DECOERR_LINKLEN       0x01
 717 #define JRSTA_DECOERR_LINKPTR       0x02
 718 #define JRSTA_DECOERR_JRCTRL        0x03
 719 #define JRSTA_DECOERR_DESCCMD       0x04
 720 #define JRSTA_DECOERR_ORDER         0x05
 721 #define JRSTA_DECOERR_KEYCMD        0x06
 722 #define JRSTA_DECOERR_LOADCMD       0x07
 723 #define JRSTA_DECOERR_STORECMD      0x08
 724 #define JRSTA_DECOERR_OPCMD         0x09
 725 #define JRSTA_DECOERR_FIFOLDCMD     0x0a
 726 #define JRSTA_DECOERR_FIFOSTCMD     0x0b
 727 #define JRSTA_DECOERR_MOVECMD       0x0c
 728 #define JRSTA_DECOERR_JUMPCMD       0x0d
 729 #define JRSTA_DECOERR_MATHCMD       0x0e
 730 #define JRSTA_DECOERR_SHASHCMD      0x0f
 731 #define JRSTA_DECOERR_SEQCMD        0x10
 732 #define JRSTA_DECOERR_DECOINTERNAL  0x11
 733 #define JRSTA_DECOERR_SHDESCHDR     0x12
 734 #define JRSTA_DECOERR_HDRLEN        0x13
 735 #define JRSTA_DECOERR_BURSTER       0x14
 736 #define JRSTA_DECOERR_DESCSIGNATURE 0x15
 737 #define JRSTA_DECOERR_DMA           0x16
 738 #define JRSTA_DECOERR_BURSTFIFO     0x17
 739 #define JRSTA_DECOERR_JRRESET       0x1a
 740 #define JRSTA_DECOERR_JOBFAIL       0x1b
 741 #define JRSTA_DECOERR_DNRERR        0x80
 742 #define JRSTA_DECOERR_UNDEFPCL      0x81
 743 #define JRSTA_DECOERR_PDBERR        0x82
 744 #define JRSTA_DECOERR_ANRPLY_LATE   0x83
 745 #define JRSTA_DECOERR_ANRPLY_REPLAY 0x84
 746 #define JRSTA_DECOERR_SEQOVF        0x85
 747 #define JRSTA_DECOERR_INVSIGN       0x86
 748 #define JRSTA_DECOERR_DSASIGN       0x87
 749 
 750 #define JRSTA_QIERR_ERROR_MASK      0x00ff
 751 
 752 #define JRSTA_CCBERR_JUMP           0x08000000
 753 #define JRSTA_CCBERR_INDEX_MASK     0xff00
 754 #define JRSTA_CCBERR_INDEX_SHIFT    8
 755 #define JRSTA_CCBERR_CHAID_MASK     0x00f0
 756 #define JRSTA_CCBERR_CHAID_SHIFT    4
 757 #define JRSTA_CCBERR_ERRID_MASK     0x000f
 758 
 759 #define JRSTA_CCBERR_CHAID_AES      (0x01 << JRSTA_CCBERR_CHAID_SHIFT)
 760 #define JRSTA_CCBERR_CHAID_DES      (0x02 << JRSTA_CCBERR_CHAID_SHIFT)
 761 #define JRSTA_CCBERR_CHAID_ARC4     (0x03 << JRSTA_CCBERR_CHAID_SHIFT)
 762 #define JRSTA_CCBERR_CHAID_MD       (0x04 << JRSTA_CCBERR_CHAID_SHIFT)
 763 #define JRSTA_CCBERR_CHAID_RNG      (0x05 << JRSTA_CCBERR_CHAID_SHIFT)
 764 #define JRSTA_CCBERR_CHAID_SNOW     (0x06 << JRSTA_CCBERR_CHAID_SHIFT)
 765 #define JRSTA_CCBERR_CHAID_KASUMI   (0x07 << JRSTA_CCBERR_CHAID_SHIFT)
 766 #define JRSTA_CCBERR_CHAID_PK       (0x08 << JRSTA_CCBERR_CHAID_SHIFT)
 767 #define JRSTA_CCBERR_CHAID_CRC      (0x09 << JRSTA_CCBERR_CHAID_SHIFT)
 768 
 769 #define JRSTA_CCBERR_ERRID_NONE     0x00
 770 #define JRSTA_CCBERR_ERRID_MODE     0x01
 771 #define JRSTA_CCBERR_ERRID_DATASIZ  0x02
 772 #define JRSTA_CCBERR_ERRID_KEYSIZ   0x03
 773 #define JRSTA_CCBERR_ERRID_PKAMEMSZ 0x04
 774 #define JRSTA_CCBERR_ERRID_PKBMEMSZ 0x05
 775 #define JRSTA_CCBERR_ERRID_SEQUENCE 0x06
 776 #define JRSTA_CCBERR_ERRID_PKDIVZRO 0x07
 777 #define JRSTA_CCBERR_ERRID_PKMODEVN 0x08
 778 #define JRSTA_CCBERR_ERRID_KEYPARIT 0x09
 779 #define JRSTA_CCBERR_ERRID_ICVCHK   0x0a
 780 #define JRSTA_CCBERR_ERRID_HARDWARE 0x0b
 781 #define JRSTA_CCBERR_ERRID_CCMAAD   0x0c
 782 #define JRSTA_CCBERR_ERRID_INVCHA   0x0f
 783 
 784 #define JRINT_ERR_INDEX_MASK        0x3fff0000
 785 #define JRINT_ERR_INDEX_SHIFT       16
 786 #define JRINT_ERR_TYPE_MASK         0xf00
 787 #define JRINT_ERR_TYPE_SHIFT        8
 788 #define JRINT_ERR_HALT_MASK         0xc
 789 #define JRINT_ERR_HALT_SHIFT        2
 790 #define JRINT_ERR_HALT_INPROGRESS   0x4
 791 #define JRINT_ERR_HALT_COMPLETE     0x8
 792 #define JRINT_JR_ERROR              0x02
 793 #define JRINT_JR_INT                0x01
 794 
 795 #define JRINT_ERR_TYPE_WRITE        1
 796 #define JRINT_ERR_TYPE_BAD_INPADDR  3
 797 #define JRINT_ERR_TYPE_BAD_OUTADDR  4
 798 #define JRINT_ERR_TYPE_INV_INPWRT   5
 799 #define JRINT_ERR_TYPE_INV_OUTWRT   6
 800 #define JRINT_ERR_TYPE_RESET        7
 801 #define JRINT_ERR_TYPE_REMOVE_OFL   8
 802 #define JRINT_ERR_TYPE_ADD_OFL      9
 803 
 804 #define JRCFG_SOE               0x04
 805 #define JRCFG_ICEN              0x02
 806 #define JRCFG_IMSK              0x01
 807 #define JRCFG_ICDCT_SHIFT       8
 808 #define JRCFG_ICTT_SHIFT        16
 809 
 810 #define JRCR_RESET                  0x01
 811 
 812 /*
 813  * caam_assurance - Assurance Controller View
 814  * base + 0x6000 padded out to 0x1000
 815  */
 816 
 817 struct rtic_element {
 818         u64 address;
 819         u32 rsvd;
 820         u32 length;
 821 };
 822 
 823 struct rtic_block {
 824         struct rtic_element element[2];
 825 };
 826 
 827 struct rtic_memhash {
 828         u32 memhash_be[32];
 829         u32 memhash_le[32];
 830 };
 831 
 832 struct caam_assurance {
 833     /* Status/Command/Watchdog */
 834         u32 rsvd1;
 835         u32 status;             /* RSTA - Status */
 836         u32 rsvd2;
 837         u32 cmd;                /* RCMD - Command */
 838         u32 rsvd3;
 839         u32 ctrl;               /* RCTL - Control */
 840         u32 rsvd4;
 841         u32 throttle;   /* RTHR - Throttle */
 842         u32 rsvd5[2];
 843         u64 watchdog;   /* RWDOG - Watchdog Timer */
 844         u32 rsvd6;
 845         u32 rend;               /* REND - Endian corrections */
 846         u32 rsvd7[50];
 847 
 848         /* Block access/configuration @ 100/110/120/130 */
 849         struct rtic_block memblk[4];    /* Memory Blocks A-D */
 850         u32 rsvd8[32];
 851 
 852         /* Block hashes @ 200/300/400/500 */
 853         struct rtic_memhash hash[4];    /* Block hash values A-D */
 854         u32 rsvd_3[640];
 855 };
 856 
 857 /*
 858  * caam_queue_if - QI configuration and control
 859  * starts base + 0x7000, padded out to 0x1000 long
 860  */
 861 
 862 struct caam_queue_if {
 863         u32 qi_control_hi;      /* QICTL  - QI Control */
 864         u32 qi_control_lo;
 865         u32 rsvd1;
 866         u32 qi_status;  /* QISTA  - QI Status */
 867         u32 qi_deq_cfg_hi;      /* QIDQC  - QI Dequeue Configuration */
 868         u32 qi_deq_cfg_lo;
 869         u32 qi_enq_cfg_hi;      /* QISEQC - QI Enqueue Command     */
 870         u32 qi_enq_cfg_lo;
 871         u32 rsvd2[1016];
 872 };
 873 
 874 /* QI control bits - low word */
 875 #define QICTL_DQEN      0x01              /* Enable frame pop          */
 876 #define QICTL_STOP      0x02              /* Stop dequeue/enqueue      */
 877 #define QICTL_SOE       0x04              /* Stop on error             */
 878 
 879 /* QI control bits - high word */
 880 #define QICTL_MBSI      0x01
 881 #define QICTL_MHWSI     0x02
 882 #define QICTL_MWSI      0x04
 883 #define QICTL_MDWSI     0x08
 884 #define QICTL_CBSI      0x10            /* CtrlDataByteSwapInput     */
 885 #define QICTL_CHWSI     0x20            /* CtrlDataHalfSwapInput     */
 886 #define QICTL_CWSI      0x40            /* CtrlDataWordSwapInput     */
 887 #define QICTL_CDWSI     0x80            /* CtrlDataDWordSwapInput    */
 888 #define QICTL_MBSO      0x0100
 889 #define QICTL_MHWSO     0x0200
 890 #define QICTL_MWSO      0x0400
 891 #define QICTL_MDWSO     0x0800
 892 #define QICTL_CBSO      0x1000          /* CtrlDataByteSwapOutput    */
 893 #define QICTL_CHWSO     0x2000          /* CtrlDataHalfSwapOutput    */
 894 #define QICTL_CWSO      0x4000          /* CtrlDataWordSwapOutput    */
 895 #define QICTL_CDWSO     0x8000          /* CtrlDataDWordSwapOutput   */
 896 #define QICTL_DMBS      0x010000
 897 #define QICTL_EPO       0x020000
 898 
 899 /* QI status bits */
 900 #define QISTA_PHRDERR   0x01              /* PreHeader Read Error      */
 901 #define QISTA_CFRDERR   0x02              /* Compound Frame Read Error */
 902 #define QISTA_OFWRERR   0x04              /* Output Frame Read Error   */
 903 #define QISTA_BPDERR    0x08              /* Buffer Pool Depleted      */
 904 #define QISTA_BTSERR    0x10              /* Buffer Undersize          */
 905 #define QISTA_CFWRERR   0x20              /* Compound Frame Write Err  */
 906 #define QISTA_STOPD     0x80000000        /* QI Stopped (see QICTL)    */
 907 
 908 /* deco_sg_table - DECO view of scatter/gather table */
 909 struct deco_sg_table {
 910         u64 addr;               /* Segment Address */
 911         u32 elen;               /* E, F bits + 30-bit length */
 912         u32 bpid_offset;        /* Buffer Pool ID + 16-bit length */
 913 };
 914 
 915 /*
 916  * caam_deco - descriptor controller - CHA cluster block
 917  *
 918  * Only accessible when direct DECO access is turned on
 919  * (done in DECORR, via MID programmed in DECOxMID
 920  *
 921  * 5 typical, base + 0x8000/9000/a000/b000
 922  * Padded out to 0x1000 long
 923  */
 924 struct caam_deco {
 925         u32 rsvd1;
 926         u32 cls1_mode;  /* CxC1MR -  Class 1 Mode */
 927         u32 rsvd2;
 928         u32 cls1_keysize;       /* CxC1KSR - Class 1 Key Size */
 929         u32 cls1_datasize_hi;   /* CxC1DSR - Class 1 Data Size */
 930         u32 cls1_datasize_lo;
 931         u32 rsvd3;
 932         u32 cls1_icvsize;       /* CxC1ICVSR - Class 1 ICV size */
 933         u32 rsvd4[5];
 934         u32 cha_ctrl;   /* CCTLR - CHA control */
 935         u32 rsvd5;
 936         u32 irq_crtl;   /* CxCIRQ - CCB interrupt done/error/clear */
 937         u32 rsvd6;
 938         u32 clr_written;        /* CxCWR - Clear-Written */
 939         u32 ccb_status_hi;      /* CxCSTA - CCB Status/Error */
 940         u32 ccb_status_lo;
 941         u32 rsvd7[3];
 942         u32 aad_size;   /* CxAADSZR - Current AAD Size */
 943         u32 rsvd8;
 944         u32 cls1_iv_size;       /* CxC1IVSZR - Current Class 1 IV Size */
 945         u32 rsvd9[7];
 946         u32 pkha_a_size;        /* PKASZRx - Size of PKHA A */
 947         u32 rsvd10;
 948         u32 pkha_b_size;        /* PKBSZRx - Size of PKHA B */
 949         u32 rsvd11;
 950         u32 pkha_n_size;        /* PKNSZRx - Size of PKHA N */
 951         u32 rsvd12;
 952         u32 pkha_e_size;        /* PKESZRx - Size of PKHA E */
 953         u32 rsvd13[24];
 954         u32 cls1_ctx[16];       /* CxC1CTXR - Class 1 Context @100 */
 955         u32 rsvd14[48];
 956         u32 cls1_key[8];        /* CxC1KEYR - Class 1 Key @200 */
 957         u32 rsvd15[121];
 958         u32 cls2_mode;  /* CxC2MR - Class 2 Mode */
 959         u32 rsvd16;
 960         u32 cls2_keysize;       /* CxX2KSR - Class 2 Key Size */
 961         u32 cls2_datasize_hi;   /* CxC2DSR - Class 2 Data Size */
 962         u32 cls2_datasize_lo;
 963         u32 rsvd17;
 964         u32 cls2_icvsize;       /* CxC2ICVSZR - Class 2 ICV Size */
 965         u32 rsvd18[56];
 966         u32 cls2_ctx[18];       /* CxC2CTXR - Class 2 Context @500 */
 967         u32 rsvd19[46];
 968         u32 cls2_key[32];       /* CxC2KEYR - Class2 Key @600 */
 969         u32 rsvd20[84];
 970         u32 inp_infofifo_hi;    /* CxIFIFO - Input Info FIFO @7d0 */
 971         u32 inp_infofifo_lo;
 972         u32 rsvd21[2];
 973         u64 inp_datafifo;       /* CxDFIFO - Input Data FIFO */
 974         u32 rsvd22[2];
 975         u64 out_datafifo;       /* CxOFIFO - Output Data FIFO */
 976         u32 rsvd23[2];
 977         u32 jr_ctl_hi;  /* CxJRR - JobR Control Register      @800 */
 978         u32 jr_ctl_lo;
 979         u64 jr_descaddr;        /* CxDADR - JobR Descriptor Address */
 980 #define DECO_OP_STATUS_HI_ERR_MASK 0xF00000FF
 981         u32 op_status_hi;       /* DxOPSTA - DECO Operation Status */
 982         u32 op_status_lo;
 983         u32 rsvd24[2];
 984         u32 liodn;              /* DxLSR - DECO LIODN Status - non-seq */
 985         u32 td_liodn;   /* DxLSR - DECO LIODN Status - trustdesc */
 986         u32 rsvd26[6];
 987         u64 math[4];            /* DxMTH - Math register */
 988         u32 rsvd27[8];
 989         struct deco_sg_table gthr_tbl[4];       /* DxGTR - Gather Tables */
 990         u32 rsvd28[16];
 991         struct deco_sg_table sctr_tbl[4];       /* DxSTR - Scatter Tables */
 992         u32 rsvd29[48];
 993         u32 descbuf[64];        /* DxDESB - Descriptor buffer */
 994         u32 rscvd30[193];
 995 #define DESC_DBG_DECO_STAT_VALID        0x80000000
 996 #define DESC_DBG_DECO_STAT_MASK         0x00F00000
 997 #define DESC_DBG_DECO_STAT_SHIFT        20
 998         u32 desc_dbg;           /* DxDDR - DECO Debug Register */
 999         u32 rsvd31[13];
1000 #define DESC_DER_DECO_STAT_MASK         0x000F0000
1001 #define DESC_DER_DECO_STAT_SHIFT        16
1002         u32 dbg_exec;           /* DxDER - DECO Debug Exec Register */
1003         u32 rsvd32[112];
1004 };
1005 
1006 #define DECO_STAT_HOST_ERR      0xD
1007 
1008 #define DECO_JQCR_WHL           0x20000000
1009 #define DECO_JQCR_FOUR          0x10000000
1010 
1011 #define JR_BLOCK_NUMBER         1
1012 #define ASSURE_BLOCK_NUMBER     6
1013 #define QI_BLOCK_NUMBER         7
1014 #define DECO_BLOCK_NUMBER       8
1015 #define PG_SIZE_4K              0x1000
1016 #define PG_SIZE_64K             0x10000
1017 #endif /* REGS_H */