drivers/crypto/caam/ctrl.c

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This source file includes following definitions.
build_instantiation_desc
build_deinstantiation_desc
run_descriptor_deco0
instantiate_rng
deinstantiate_rng
caam_remove
kick_trng
caam_get_era_from_hw
caam_get_era
handle_imx6_err005766
disable_clocks
init_clocks
caam_probe
   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* * CAAM control-plane driver backend
   3  * Controller-level driver, kernel property detection, initialization
   4  *
   5  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   6  * Copyright 2018-2019 NXP
   7  */
   8 
   9 #include <linux/device.h>
  10 #include <linux/of_address.h>
  11 #include <linux/of_irq.h>
  12 #include <linux/sys_soc.h>
  13 
  14 #include "compat.h"
  15 #include "regs.h"
  16 #include "intern.h"
  17 #include "jr.h"
  18 #include "desc_constr.h"
  19 #include "ctrl.h"
  20 
  21 bool caam_dpaa2;
  22 EXPORT_SYMBOL(caam_dpaa2);
  23 
  24 #ifdef CONFIG_CAAM_QI
  25 #include "qi.h"
  26 #endif
  27 
  28 /*
  29  * Descriptor to instantiate RNG State Handle 0 in normal mode and
  30  * load the JDKEK, TDKEK and TDSK registers
  31  */
  32 static void build_instantiation_desc(u32 *desc, int handle, int do_sk)
  33 {
  34         u32 *jump_cmd, op_flags;
  35 
  36         init_job_desc(desc, 0);
  37 
  38         op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
  39                         (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT;
  40 
  41         /* INIT RNG in non-test mode */
  42         append_operation(desc, op_flags);
  43 
  44         if (!handle && do_sk) {
  45                 /*
  46                  * For SH0, Secure Keys must be generated as well
  47                  */
  48 
  49                 /* wait for done */
  50                 jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
  51                 set_jump_tgt_here(desc, jump_cmd);
  52 
  53                 /*
  54                  * load 1 to clear written reg:
  55                  * resets the done interrrupt and returns the RNG to idle.
  56                  */
  57                 append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);
  58 
  59                 /* Initialize State Handle  */
  60                 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
  61                                  OP_ALG_AAI_RNG4_SK);
  62         }
  63 
  64         append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
  65 }
  66 
  67 /* Descriptor for deinstantiation of State Handle 0 of the RNG block. */
  68 static void build_deinstantiation_desc(u32 *desc, int handle)
  69 {
  70         init_job_desc(desc, 0);
  71 
  72         /* Uninstantiate State Handle 0 */
  73         append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
  74                          (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL);
  75 
  76         append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
  77 }
  78 
  79 /*
  80  * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of
  81  *                        the software (no JR/QI used).
  82  * @ctrldev - pointer to device
  83  * @status - descriptor status, after being run
  84  *
  85  * Return: - 0 if no error occurred
  86  *         - -ENODEV if the DECO couldn't be acquired
  87  *         - -EAGAIN if an error occurred while executing the descriptor
  88  */
  89 static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
  90                                         u32 *status)
  91 {
  92         struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
  93         struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
  94         struct caam_deco __iomem *deco = ctrlpriv->deco;
  95         unsigned int timeout = 100000;
  96         u32 deco_dbg_reg, deco_state, flags;
  97         int i;
  98 
  99 
 100         if (ctrlpriv->virt_en == 1 ||
 101             /*
 102              * Apparently on i.MX8MQ it doesn't matter if virt_en == 1
 103              * and the following steps should be performed regardless
 104              */
 105             of_machine_is_compatible("fsl,imx8mq")) {
 106                 clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0);
 107 
 108                 while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) &&
 109                        --timeout)
 110                         cpu_relax();
 111 
 112                 timeout = 100000;
 113         }
 114 
 115         clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE);
 116 
 117         while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) &&
 118                                                                  --timeout)
 119                 cpu_relax();
 120 
 121         if (!timeout) {
 122                 dev_err(ctrldev, "failed to acquire DECO 0\n");
 123                 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
 124                 return -ENODEV;
 125         }
 126 
 127         for (i = 0; i < desc_len(desc); i++)
 128                 wr_reg32(&deco->descbuf[i], caam32_to_cpu(*(desc + i)));
 129 
 130         flags = DECO_JQCR_WHL;
 131         /*
 132          * If the descriptor length is longer than 4 words, then the
 133          * FOUR bit in JRCTRL register must be set.
 134          */
 135         if (desc_len(desc) >= 4)
 136                 flags |= DECO_JQCR_FOUR;
 137 
 138         /* Instruct the DECO to execute it */
 139         clrsetbits_32(&deco->jr_ctl_hi, 0, flags);
 140 
 141         timeout = 10000000;
 142         do {
 143                 deco_dbg_reg = rd_reg32(&deco->desc_dbg);
 144 
 145                 if (ctrlpriv->era < 10)
 146                         deco_state = (deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) >>
 147                                      DESC_DBG_DECO_STAT_SHIFT;
 148                 else
 149                         deco_state = (rd_reg32(&deco->dbg_exec) &
 150                                       DESC_DER_DECO_STAT_MASK) >>
 151                                      DESC_DER_DECO_STAT_SHIFT;
 152 
 153                 /*
 154                  * If an error occured in the descriptor, then
 155                  * the DECO status field will be set to 0x0D
 156                  */
 157                 if (deco_state == DECO_STAT_HOST_ERR)
 158                         break;
 159 
 160                 cpu_relax();
 161         } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout);
 162 
 163         *status = rd_reg32(&deco->op_status_hi) &
 164                   DECO_OP_STATUS_HI_ERR_MASK;
 165 
 166         if (ctrlpriv->virt_en == 1)
 167                 clrsetbits_32(&ctrl->deco_rsr, DECORSR_JR0, 0);
 168 
 169         /* Mark the DECO as free */
 170         clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
 171 
 172         if (!timeout)
 173                 return -EAGAIN;
 174 
 175         return 0;
 176 }
 177 
 178 /*
 179  * instantiate_rng - builds and executes a descriptor on DECO0,
 180  *                   which initializes the RNG block.
 181  * @ctrldev - pointer to device
 182  * @state_handle_mask - bitmask containing the instantiation status
 183  *                      for the RNG4 state handles which exist in
 184  *                      the RNG4 block: 1 if it's been instantiated
 185  *                      by an external entry, 0 otherwise.
 186  * @gen_sk  - generate data to be loaded into the JDKEK, TDKEK and TDSK;
 187  *            Caution: this can be done only once; if the keys need to be
 188  *            regenerated, a POR is required
 189  *
 190  * Return: - 0 if no error occurred
 191  *         - -ENOMEM if there isn't enough memory to allocate the descriptor
 192  *         - -ENODEV if DECO0 couldn't be acquired
 193  *         - -EAGAIN if an error occurred when executing the descriptor
 194  *            f.i. there was a RNG hardware error due to not "good enough"
 195  *            entropy being aquired.
 196  */
 197 static int instantiate_rng(struct device *ctrldev, int state_handle_mask,
 198                            int gen_sk)
 199 {
 200         struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
 201         struct caam_ctrl __iomem *ctrl;
 202         u32 *desc, status = 0, rdsta_val;
 203         int ret = 0, sh_idx;
 204 
 205         ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
 206         desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL);
 207         if (!desc)
 208                 return -ENOMEM;
 209 
 210         for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
 211                 /*
 212                  * If the corresponding bit is set, this state handle
 213                  * was initialized by somebody else, so it's left alone.
 214                  */
 215                 if ((1 << sh_idx) & state_handle_mask)
 216                         continue;
 217 
 218                 /* Create the descriptor for instantiating RNG State Handle */
 219                 build_instantiation_desc(desc, sh_idx, gen_sk);
 220 
 221                 /* Try to run it through DECO0 */
 222                 ret = run_descriptor_deco0(ctrldev, desc, &status);
 223 
 224                 /*
 225                  * If ret is not 0, or descriptor status is not 0, then
 226                  * something went wrong. No need to try the next state
 227                  * handle (if available), bail out here.
 228                  * Also, if for some reason, the State Handle didn't get
 229                  * instantiated although the descriptor has finished
 230                  * without any error (HW optimizations for later
 231                  * CAAM eras), then try again.
 232                  */
 233                 if (ret)
 234                         break;
 235 
 236                 rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
 237                 if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) ||
 238                     !(rdsta_val & (1 << sh_idx))) {
 239                         ret = -EAGAIN;
 240                         break;
 241                 }
 242 
 243                 dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);
 244                 /* Clear the contents before recreating the descriptor */
 245                 memset(desc, 0x00, CAAM_CMD_SZ * 7);
 246         }
 247 
 248         kfree(desc);
 249 
 250         return ret;
 251 }
 252 
 253 /*
 254  * deinstantiate_rng - builds and executes a descriptor on DECO0,
 255  *                     which deinitializes the RNG block.
 256  * @ctrldev - pointer to device
 257  * @state_handle_mask - bitmask containing the instantiation status
 258  *                      for the RNG4 state handles which exist in
 259  *                      the RNG4 block: 1 if it's been instantiated
 260  *
 261  * Return: - 0 if no error occurred
 262  *         - -ENOMEM if there isn't enough memory to allocate the descriptor
 263  *         - -ENODEV if DECO0 couldn't be acquired
 264  *         - -EAGAIN if an error occurred when executing the descriptor
 265  */
 266 static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask)
 267 {
 268         u32 *desc, status;
 269         int sh_idx, ret = 0;
 270 
 271         desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL);
 272         if (!desc)
 273                 return -ENOMEM;
 274 
 275         for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
 276                 /*
 277                  * If the corresponding bit is set, then it means the state
 278                  * handle was initialized by us, and thus it needs to be
 279                  * deinitialized as well
 280                  */
 281                 if ((1 << sh_idx) & state_handle_mask) {
 282                         /*
 283                          * Create the descriptor for deinstantating this state
 284                          * handle
 285                          */
 286                         build_deinstantiation_desc(desc, sh_idx);
 287 
 288                         /* Try to run it through DECO0 */
 289                         ret = run_descriptor_deco0(ctrldev, desc, &status);
 290 
 291                         if (ret ||
 292                             (status && status != JRSTA_SSRC_JUMP_HALT_CC)) {
 293                                 dev_err(ctrldev,
 294                                         "Failed to deinstantiate RNG4 SH%d\n",
 295                                         sh_idx);
 296                                 break;
 297                         }
 298                         dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx);
 299                 }
 300         }
 301 
 302         kfree(desc);
 303 
 304         return ret;
 305 }
 306 
 307 static int caam_remove(struct platform_device *pdev)
 308 {
 309         struct device *ctrldev;
 310         struct caam_drv_private *ctrlpriv;
 311         struct caam_ctrl __iomem *ctrl;
 312 
 313         ctrldev = &pdev->dev;
 314         ctrlpriv = dev_get_drvdata(ctrldev);
 315         ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
 316 
 317         /* Remove platform devices under the crypto node */
 318         of_platform_depopulate(ctrldev);
 319 
 320 #ifdef CONFIG_CAAM_QI
 321         if (ctrlpriv->qi_init)
 322                 caam_qi_shutdown(ctrldev);
 323 #endif
 324 
 325         /*
 326          * De-initialize RNG state handles initialized by this driver.
 327          * In case of SoCs with Management Complex, RNG is managed by MC f/w.
 328          */
 329         if (!ctrlpriv->mc_en && ctrlpriv->rng4_sh_init)
 330                 deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init);
 331 
 332         /* Shut down debug views */
 333 #ifdef CONFIG_DEBUG_FS
 334         debugfs_remove_recursive(ctrlpriv->dfs_root);
 335 #endif
 336 
 337         /* Unmap controller region */
 338         iounmap(ctrl);
 339 
 340         return 0;
 341 }
 342 
 343 /*
 344  * kick_trng - sets the various parameters for enabling the initialization
 345  *             of the RNG4 block in CAAM
 346  * @pdev - pointer to the platform device
 347  * @ent_delay - Defines the length (in system clocks) of each entropy sample.
 348  */
 349 static void kick_trng(struct platform_device *pdev, int ent_delay)
 350 {
 351         struct device *ctrldev = &pdev->dev;
 352         struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
 353         struct caam_ctrl __iomem *ctrl;
 354         struct rng4tst __iomem *r4tst;
 355         u32 val;
 356 
 357         ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
 358         r4tst = &ctrl->r4tst[0];
 359 
 360         /* put RNG4 into program mode */
 361         clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM);
 362 
 363         /*
 364          * Performance-wise, it does not make sense to
 365          * set the delay to a value that is lower
 366          * than the last one that worked (i.e. the state handles
 367          * were instantiated properly. Thus, instead of wasting
 368          * time trying to set the values controlling the sample
 369          * frequency, the function simply returns.
 370          */
 371         val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK)
 372               >> RTSDCTL_ENT_DLY_SHIFT;
 373         if (ent_delay <= val)
 374                 goto start_rng;
 375 
 376         val = rd_reg32(&r4tst->rtsdctl);
 377         val = (val & ~RTSDCTL_ENT_DLY_MASK) |
 378               (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
 379         wr_reg32(&r4tst->rtsdctl, val);
 380         /* min. freq. count, equal to 1/4 of the entropy sample length */
 381         wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2);
 382         /* disable maximum frequency count */
 383         wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);
 384         /* read the control register */
 385         val = rd_reg32(&r4tst->rtmctl);
 386 start_rng:
 387         /*
 388          * select raw sampling in both entropy shifter
 389          * and statistical checker; ; put RNG4 into run mode
 390          */
 391         clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM, RTMCTL_SAMP_MODE_RAW_ES_SC);
 392 }
 393 
 394 static int caam_get_era_from_hw(struct caam_ctrl __iomem *ctrl)
 395 {
 396         static const struct {
 397                 u16 ip_id;
 398                 u8 maj_rev;
 399                 u8 era;
 400         } id[] = {
 401                 {0x0A10, 1, 1},
 402                 {0x0A10, 2, 2},
 403                 {0x0A12, 1, 3},
 404                 {0x0A14, 1, 3},
 405                 {0x0A14, 2, 4},
 406                 {0x0A16, 1, 4},
 407                 {0x0A10, 3, 4},
 408                 {0x0A11, 1, 4},
 409                 {0x0A18, 1, 4},
 410                 {0x0A11, 2, 5},
 411                 {0x0A12, 2, 5},
 412                 {0x0A13, 1, 5},
 413                 {0x0A1C, 1, 5}
 414         };
 415         u32 ccbvid, id_ms;
 416         u8 maj_rev, era;
 417         u16 ip_id;
 418         int i;
 419 
 420         ccbvid = rd_reg32(&ctrl->perfmon.ccb_id);
 421         era = (ccbvid & CCBVID_ERA_MASK) >> CCBVID_ERA_SHIFT;
 422         if (era)        /* This is '0' prior to CAAM ERA-6 */
 423                 return era;
 424 
 425         id_ms = rd_reg32(&ctrl->perfmon.caam_id_ms);
 426         ip_id = (id_ms & SECVID_MS_IPID_MASK) >> SECVID_MS_IPID_SHIFT;
 427         maj_rev = (id_ms & SECVID_MS_MAJ_REV_MASK) >> SECVID_MS_MAJ_REV_SHIFT;
 428 
 429         for (i = 0; i < ARRAY_SIZE(id); i++)
 430                 if (id[i].ip_id == ip_id && id[i].maj_rev == maj_rev)
 431                         return id[i].era;
 432 
 433         return -ENOTSUPP;
 434 }
 435 
 436 /**
 437  * caam_get_era() - Return the ERA of the SEC on SoC, based
 438  * on "sec-era" optional property in the DTS. This property is updated
 439  * by u-boot.
 440  * In case this property is not passed an attempt to retrieve the CAAM
 441  * era via register reads will be made.
 442  **/
 443 static int caam_get_era(struct caam_ctrl __iomem *ctrl)
 444 {
 445         struct device_node *caam_node;
 446         int ret;
 447         u32 prop;
 448 
 449         caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
 450         ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop);
 451         of_node_put(caam_node);
 452 
 453         if (!ret)
 454                 return prop;
 455         else
 456                 return caam_get_era_from_hw(ctrl);
 457 }
 458 
 459 /*
 460  * ERRATA: imx6 devices (imx6D, imx6Q, imx6DL, imx6S, imx6DP and imx6QP)
 461  * have an issue wherein AXI bus transactions may not occur in the correct
 462  * order. This isn't a problem running single descriptors, but can be if
 463  * running multiple concurrent descriptors. Reworking the driver to throttle
 464  * to single requests is impractical, thus the workaround is to limit the AXI
 465  * pipeline to a depth of 1 (from it's default of 4) to preclude this situation
 466  * from occurring.
 467  */
 468 static void handle_imx6_err005766(u32 *mcr)
 469 {
 470         if (of_machine_is_compatible("fsl,imx6q") ||
 471             of_machine_is_compatible("fsl,imx6dl") ||
 472             of_machine_is_compatible("fsl,imx6qp"))
 473                 clrsetbits_32(mcr, MCFGR_AXIPIPE_MASK,
 474                               1 << MCFGR_AXIPIPE_SHIFT);
 475 }
 476 
 477 static const struct of_device_id caam_match[] = {
 478         {
 479                 .compatible = "fsl,sec-v4.0",
 480         },
 481         {
 482                 .compatible = "fsl,sec4.0",
 483         },
 484         {},
 485 };
 486 MODULE_DEVICE_TABLE(of, caam_match);
 487 
 488 struct caam_imx_data {
 489         const struct clk_bulk_data *clks;
 490         int num_clks;
 491 };
 492 
 493 static const struct clk_bulk_data caam_imx6_clks[] = {
 494         { .id = "ipg" },
 495         { .id = "mem" },
 496         { .id = "aclk" },
 497         { .id = "emi_slow" },
 498 };
 499 
 500 static const struct caam_imx_data caam_imx6_data = {
 501         .clks = caam_imx6_clks,
 502         .num_clks = ARRAY_SIZE(caam_imx6_clks),
 503 };
 504 
 505 static const struct clk_bulk_data caam_imx7_clks[] = {
 506         { .id = "ipg" },
 507         { .id = "aclk" },
 508 };
 509 
 510 static const struct caam_imx_data caam_imx7_data = {
 511         .clks = caam_imx7_clks,
 512         .num_clks = ARRAY_SIZE(caam_imx7_clks),
 513 };
 514 
 515 static const struct clk_bulk_data caam_imx6ul_clks[] = {
 516         { .id = "ipg" },
 517         { .id = "mem" },
 518         { .id = "aclk" },
 519 };
 520 
 521 static const struct caam_imx_data caam_imx6ul_data = {
 522         .clks = caam_imx6ul_clks,
 523         .num_clks = ARRAY_SIZE(caam_imx6ul_clks),
 524 };
 525 
 526 static const struct soc_device_attribute caam_imx_soc_table[] = {
 527         { .soc_id = "i.MX6UL", .data = &caam_imx6ul_data },
 528         { .soc_id = "i.MX6*",  .data = &caam_imx6_data },
 529         { .soc_id = "i.MX7*",  .data = &caam_imx7_data },
 530         { .soc_id = "i.MX8MQ", .data = &caam_imx7_data },
 531         { .family = "Freescale i.MX" },
 532         { /* sentinel */ }
 533 };
 534 
 535 static void disable_clocks(void *data)
 536 {
 537         struct caam_drv_private *ctrlpriv = data;
 538 
 539         clk_bulk_disable_unprepare(ctrlpriv->num_clks, ctrlpriv->clks);
 540 }
 541 
 542 static int init_clocks(struct device *dev, const struct caam_imx_data *data)
 543 {
 544         struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
 545         int ret;
 546 
 547         ctrlpriv->num_clks = data->num_clks;
 548         ctrlpriv->clks = devm_kmemdup(dev, data->clks,
 549                                       data->num_clks * sizeof(data->clks[0]),
 550                                       GFP_KERNEL);
 551         if (!ctrlpriv->clks)
 552                 return -ENOMEM;
 553 
 554         ret = devm_clk_bulk_get(dev, ctrlpriv->num_clks, ctrlpriv->clks);
 555         if (ret) {
 556                 dev_err(dev,
 557                         "Failed to request all necessary clocks\n");
 558                 return ret;
 559         }
 560 
 561         ret = clk_bulk_prepare_enable(ctrlpriv->num_clks, ctrlpriv->clks);
 562         if (ret) {
 563                 dev_err(dev,
 564                         "Failed to prepare/enable all necessary clocks\n");
 565                 return ret;
 566         }
 567 
 568         return devm_add_action_or_reset(dev, disable_clocks, ctrlpriv);
 569 }
 570 
 571 /* Probe routine for CAAM top (controller) level */
 572 static int caam_probe(struct platform_device *pdev)
 573 {
 574         int ret, ring, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
 575         u64 caam_id;
 576         const struct soc_device_attribute *imx_soc_match;
 577         struct device *dev;
 578         struct device_node *nprop, *np;
 579         struct caam_ctrl __iomem *ctrl;
 580         struct caam_drv_private *ctrlpriv;
 581 #ifdef CONFIG_DEBUG_FS
 582         struct caam_perfmon *perfmon;
 583 #endif
 584         u32 scfgr, comp_params;
 585         u8 rng_vid;
 586         int pg_size;
 587         int BLOCK_OFFSET = 0;
 588 
 589         ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL);
 590         if (!ctrlpriv)
 591                 return -ENOMEM;
 592 
 593         dev = &pdev->dev;
 594         dev_set_drvdata(dev, ctrlpriv);
 595         nprop = pdev->dev.of_node;
 596 
 597         imx_soc_match = soc_device_match(caam_imx_soc_table);
 598         caam_imx = (bool)imx_soc_match;
 599 
 600         if (imx_soc_match) {
 601                 if (!imx_soc_match->data) {
 602                         dev_err(dev, "No clock data provided for i.MX SoC");
 603                         return -EINVAL;
 604                 }
 605 
 606                 ret = init_clocks(dev, imx_soc_match->data);
 607                 if (ret)
 608                         return ret;
 609         }
 610 
 611 
 612         /* Get configuration properties from device tree */
 613         /* First, get register page */
 614         ctrl = of_iomap(nprop, 0);
 615         if (!ctrl) {
 616                 dev_err(dev, "caam: of_iomap() failed\n");
 617                 return -ENOMEM;
 618         }
 619 
 620         caam_little_end = !(bool)(rd_reg32(&ctrl->perfmon.status) &
 621                                   (CSTA_PLEND | CSTA_ALT_PLEND));
 622         comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms);
 623         if (comp_params & CTPR_MS_PS && rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR)
 624                 caam_ptr_sz = sizeof(u64);
 625         else
 626                 caam_ptr_sz = sizeof(u32);
 627         caam_dpaa2 = !!(comp_params & CTPR_MS_DPAA2);
 628         ctrlpriv->qi_present = !!(comp_params & CTPR_MS_QI_MASK);
 629 
 630 #ifdef CONFIG_CAAM_QI
 631         /* If (DPAA 1.x) QI present, check whether dependencies are available */
 632         if (ctrlpriv->qi_present && !caam_dpaa2) {
 633                 ret = qman_is_probed();
 634                 if (!ret) {
 635                         ret = -EPROBE_DEFER;
 636                         goto iounmap_ctrl;
 637                 } else if (ret < 0) {
 638                         dev_err(dev, "failing probe due to qman probe error\n");
 639                         ret = -ENODEV;
 640                         goto iounmap_ctrl;
 641                 }
 642 
 643                 ret = qman_portals_probed();
 644                 if (!ret) {
 645                         ret = -EPROBE_DEFER;
 646                         goto iounmap_ctrl;
 647                 } else if (ret < 0) {
 648                         dev_err(dev, "failing probe due to qman portals probe error\n");
 649                         ret = -ENODEV;
 650                         goto iounmap_ctrl;
 651                 }
 652         }
 653 #endif
 654 
 655         /* Allocating the BLOCK_OFFSET based on the supported page size on
 656          * the platform
 657          */
 658         pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT;
 659         if (pg_size == 0)
 660                 BLOCK_OFFSET = PG_SIZE_4K;
 661         else
 662                 BLOCK_OFFSET = PG_SIZE_64K;
 663 
 664         ctrlpriv->ctrl = (struct caam_ctrl __iomem __force *)ctrl;
 665         ctrlpriv->assure = (struct caam_assurance __iomem __force *)
 666                            ((__force uint8_t *)ctrl +
 667                             BLOCK_OFFSET * ASSURE_BLOCK_NUMBER
 668                            );
 669         ctrlpriv->deco = (struct caam_deco __iomem __force *)
 670                          ((__force uint8_t *)ctrl +
 671                          BLOCK_OFFSET * DECO_BLOCK_NUMBER
 672                          );
 673 
 674         /* Get the IRQ of the controller (for security violations only) */
 675         ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
 676 
 677         /*
 678          * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
 679          * long pointers in master configuration register.
 680          * In case of SoCs with Management Complex, MC f/w performs
 681          * the configuration.
 682          */
 683         np = of_find_compatible_node(NULL, NULL, "fsl,qoriq-mc");
 684         ctrlpriv->mc_en = !!np;
 685         of_node_put(np);
 686 
 687         if (!ctrlpriv->mc_en)
 688                 clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK,
 689                               MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF |
 690                               MCFGR_WDENABLE | MCFGR_LARGE_BURST);
 691 
 692         handle_imx6_err005766(&ctrl->mcr);
 693 
 694         /*
 695          *  Read the Compile Time paramters and SCFGR to determine
 696          * if Virtualization is enabled for this platform
 697          */
 698         scfgr = rd_reg32(&ctrl->scfgr);
 699 
 700         ctrlpriv->virt_en = 0;
 701         if (comp_params & CTPR_MS_VIRT_EN_INCL) {
 702                 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
 703                  * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1
 704                  */
 705                 if ((comp_params & CTPR_MS_VIRT_EN_POR) ||
 706                     (!(comp_params & CTPR_MS_VIRT_EN_POR) &&
 707                        (scfgr & SCFGR_VIRT_EN)))
 708                                 ctrlpriv->virt_en = 1;
 709         } else {
 710                 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
 711                 if (comp_params & CTPR_MS_VIRT_EN_POR)
 712                                 ctrlpriv->virt_en = 1;
 713         }
 714 
 715         if (ctrlpriv->virt_en == 1)
 716                 clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START |
 717                               JRSTART_JR1_START | JRSTART_JR2_START |
 718                               JRSTART_JR3_START);
 719 
 720         ret = dma_set_mask_and_coherent(dev, caam_get_dma_mask(dev));
 721         if (ret) {
 722                 dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret);
 723                 goto iounmap_ctrl;
 724         }
 725 
 726         ctrlpriv->era = caam_get_era(ctrl);
 727         ctrlpriv->domain = iommu_get_domain_for_dev(dev);
 728 
 729 #ifdef CONFIG_DEBUG_FS
 730         /*
 731          * FIXME: needs better naming distinction, as some amalgamation of
 732          * "caam" and nprop->full_name. The OF name isn't distinctive,
 733          * but does separate instances
 734          */
 735         perfmon = (struct caam_perfmon __force *)&ctrl->perfmon;
 736 
 737         ctrlpriv->dfs_root = debugfs_create_dir(dev_name(dev), NULL);
 738         ctrlpriv->ctl = debugfs_create_dir("ctl", ctrlpriv->dfs_root);
 739 #endif
 740 
 741         /* Check to see if (DPAA 1.x) QI present. If so, enable */
 742         if (ctrlpriv->qi_present && !caam_dpaa2) {
 743                 ctrlpriv->qi = (struct caam_queue_if __iomem __force *)
 744                                ((__force uint8_t *)ctrl +
 745                                  BLOCK_OFFSET * QI_BLOCK_NUMBER
 746                                );
 747                 /* This is all that's required to physically enable QI */
 748                 wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN);
 749 
 750                 /* If QMAN driver is present, init CAAM-QI backend */
 751 #ifdef CONFIG_CAAM_QI
 752                 ret = caam_qi_init(pdev);
 753                 if (ret)
 754                         dev_err(dev, "caam qi i/f init failed: %d\n", ret);
 755 #endif
 756         }
 757 
 758         ret = of_platform_populate(nprop, caam_match, NULL, dev);
 759         if (ret) {
 760                 dev_err(dev, "JR platform devices creation error\n");
 761                 goto shutdown_qi;
 762         }
 763 
 764         ring = 0;
 765         for_each_available_child_of_node(nprop, np)
 766                 if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
 767                     of_device_is_compatible(np, "fsl,sec4.0-job-ring")) {
 768                         ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *)
 769                                              ((__force uint8_t *)ctrl +
 770                                              (ring + JR_BLOCK_NUMBER) *
 771                                               BLOCK_OFFSET
 772                                              );
 773                         ctrlpriv->total_jobrs++;
 774                         ring++;
 775                 }
 776 
 777         /* If no QI and no rings specified, quit and go home */
 778         if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) {
 779                 dev_err(dev, "no queues configured, terminating\n");
 780                 ret = -ENOMEM;
 781                 goto caam_remove;
 782         }
 783 
 784         if (ctrlpriv->era < 10)
 785                 rng_vid = (rd_reg32(&ctrl->perfmon.cha_id_ls) &
 786                            CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT;
 787         else
 788                 rng_vid = (rd_reg32(&ctrl->vreg.rng) & CHA_VER_VID_MASK) >>
 789                            CHA_VER_VID_SHIFT;
 790 
 791         /*
 792          * If SEC has RNG version >= 4 and RNG state handle has not been
 793          * already instantiated, do RNG instantiation
 794          * In case of SoCs with Management Complex, RNG is managed by MC f/w.
 795          */
 796         if (!ctrlpriv->mc_en && rng_vid >= 4) {
 797                 ctrlpriv->rng4_sh_init =
 798                         rd_reg32(&ctrl->r4tst[0].rdsta);
 799                 /*
 800                  * If the secure keys (TDKEK, JDKEK, TDSK), were already
 801                  * generated, signal this to the function that is instantiating
 802                  * the state handles. An error would occur if RNG4 attempts
 803                  * to regenerate these keys before the next POR.
 804                  */
 805                 gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1;
 806                 ctrlpriv->rng4_sh_init &= RDSTA_IFMASK;
 807                 do {
 808                         int inst_handles =
 809                                 rd_reg32(&ctrl->r4tst[0].rdsta) &
 810                                                                 RDSTA_IFMASK;
 811                         /*
 812                          * If either SH were instantiated by somebody else
 813                          * (e.g. u-boot) then it is assumed that the entropy
 814                          * parameters are properly set and thus the function
 815                          * setting these (kick_trng(...)) is skipped.
 816                          * Also, if a handle was instantiated, do not change
 817                          * the TRNG parameters.
 818                          */
 819                         if (!(ctrlpriv->rng4_sh_init || inst_handles)) {
 820                                 dev_info(dev,
 821                                          "Entropy delay = %u\n",
 822                                          ent_delay);
 823                                 kick_trng(pdev, ent_delay);
 824                                 ent_delay += 400;
 825                         }
 826                         /*
 827                          * if instantiate_rng(...) fails, the loop will rerun
 828                          * and the kick_trng(...) function will modfiy the
 829                          * upper and lower limits of the entropy sampling
 830                          * interval, leading to a sucessful initialization of
 831                          * the RNG.
 832                          */
 833                         ret = instantiate_rng(dev, inst_handles,
 834                                               gen_sk);
 835                         if (ret == -EAGAIN)
 836                                 /*
 837                                  * if here, the loop will rerun,
 838                                  * so don't hog the CPU
 839                                  */
 840                                 cpu_relax();
 841                 } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
 842                 if (ret) {
 843                         dev_err(dev, "failed to instantiate RNG");
 844                         goto caam_remove;
 845                 }
 846                 /*
 847                  * Set handles init'ed by this module as the complement of the
 848                  * already initialized ones
 849                  */
 850                 ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK;
 851 
 852                 /* Enable RDB bit so that RNG works faster */
 853                 clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE);
 854         }
 855 
 856         /* NOTE: RTIC detection ought to go here, around Si time */
 857 
 858         caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 |
 859                   (u64)rd_reg32(&ctrl->perfmon.caam_id_ls);
 860 
 861         /* Report "alive" for developer to see */
 862         dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
 863                  ctrlpriv->era);
 864         dev_info(dev, "job rings = %d, qi = %d\n",
 865                  ctrlpriv->total_jobrs, ctrlpriv->qi_present);
 866 
 867 #ifdef CONFIG_DEBUG_FS
 868         debugfs_create_file("rq_dequeued", S_IRUSR | S_IRGRP | S_IROTH,
 869                             ctrlpriv->ctl, &perfmon->req_dequeued,
 870                             &caam_fops_u64_ro);
 871         debugfs_create_file("ob_rq_encrypted", S_IRUSR | S_IRGRP | S_IROTH,
 872                             ctrlpriv->ctl, &perfmon->ob_enc_req,
 873                             &caam_fops_u64_ro);
 874         debugfs_create_file("ib_rq_decrypted", S_IRUSR | S_IRGRP | S_IROTH,
 875                             ctrlpriv->ctl, &perfmon->ib_dec_req,
 876                             &caam_fops_u64_ro);
 877         debugfs_create_file("ob_bytes_encrypted", S_IRUSR | S_IRGRP | S_IROTH,
 878                             ctrlpriv->ctl, &perfmon->ob_enc_bytes,
 879                             &caam_fops_u64_ro);
 880         debugfs_create_file("ob_bytes_protected", S_IRUSR | S_IRGRP | S_IROTH,
 881                             ctrlpriv->ctl, &perfmon->ob_prot_bytes,
 882                             &caam_fops_u64_ro);
 883         debugfs_create_file("ib_bytes_decrypted", S_IRUSR | S_IRGRP | S_IROTH,
 884                             ctrlpriv->ctl, &perfmon->ib_dec_bytes,
 885                             &caam_fops_u64_ro);
 886         debugfs_create_file("ib_bytes_validated", S_IRUSR | S_IRGRP | S_IROTH,
 887                             ctrlpriv->ctl, &perfmon->ib_valid_bytes,
 888                             &caam_fops_u64_ro);
 889 
 890         /* Controller level - global status values */
 891         debugfs_create_file("fault_addr", S_IRUSR | S_IRGRP | S_IROTH,
 892                             ctrlpriv->ctl, &perfmon->faultaddr,
 893                             &caam_fops_u32_ro);
 894         debugfs_create_file("fault_detail", S_IRUSR | S_IRGRP | S_IROTH,
 895                             ctrlpriv->ctl, &perfmon->faultdetail,
 896                             &caam_fops_u32_ro);
 897         debugfs_create_file("fault_status", S_IRUSR | S_IRGRP | S_IROTH,
 898                             ctrlpriv->ctl, &perfmon->status,
 899                             &caam_fops_u32_ro);
 900 
 901         /* Internal covering keys (useful in non-secure mode only) */
 902         ctrlpriv->ctl_kek_wrap.data = (__force void *)&ctrlpriv->ctrl->kek[0];
 903         ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
 904         debugfs_create_blob("kek", S_IRUSR | S_IRGRP | S_IROTH, ctrlpriv->ctl,
 905                             &ctrlpriv->ctl_kek_wrap);
 906 
 907         ctrlpriv->ctl_tkek_wrap.data = (__force void *)&ctrlpriv->ctrl->tkek[0];
 908         ctrlpriv->ctl_tkek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
 909         debugfs_create_blob("tkek", S_IRUSR | S_IRGRP | S_IROTH, ctrlpriv->ctl,
 910                             &ctrlpriv->ctl_tkek_wrap);
 911 
 912         ctrlpriv->ctl_tdsk_wrap.data = (__force void *)&ctrlpriv->ctrl->tdsk[0];
 913         ctrlpriv->ctl_tdsk_wrap.size = KEK_KEY_SIZE * sizeof(u32);
 914         debugfs_create_blob("tdsk", S_IRUSR | S_IRGRP | S_IROTH, ctrlpriv->ctl,
 915                             &ctrlpriv->ctl_tdsk_wrap);
 916 #endif
 917         return 0;
 918 
 919 caam_remove:
 920         caam_remove(pdev);
 921         return ret;
 922 
 923 shutdown_qi:
 924 #ifdef CONFIG_CAAM_QI
 925         if (ctrlpriv->qi_init)
 926                 caam_qi_shutdown(dev);
 927 #endif
 928 iounmap_ctrl:
 929         iounmap(ctrl);
 930         return ret;
 931 }
 932 
 933 static struct platform_driver caam_driver = {
 934         .driver = {
 935                 .name = "caam",
 936                 .of_match_table = caam_match,
 937         },
 938         .probe       = caam_probe,
 939         .remove      = caam_remove,
 940 };
 941 
 942 module_platform_driver(caam_driver);
 943 
 944 MODULE_LICENSE("GPL");
 945 MODULE_DESCRIPTION("FSL CAAM request backend");
 946 MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/crypto/caam/ctrl.c

DEFINITIONS
