This source file includes following definitions.
- mxs_dcp_start_dma
- mxs_dcp_run_aes
- mxs_dcp_aes_block_crypt
- dcp_chan_thread_aes
- mxs_dcp_block_fallback
- mxs_dcp_aes_enqueue
- mxs_dcp_aes_ecb_decrypt
- mxs_dcp_aes_ecb_encrypt
- mxs_dcp_aes_cbc_decrypt
- mxs_dcp_aes_cbc_encrypt
- mxs_dcp_aes_setkey
- mxs_dcp_aes_fallback_init
- mxs_dcp_aes_fallback_exit
- mxs_dcp_run_sha
- dcp_sha_req_to_buf
- dcp_chan_thread_sha
- dcp_sha_init
- dcp_sha_update_fx
- dcp_sha_update
- dcp_sha_final
- dcp_sha_finup
- dcp_sha_digest
- dcp_sha_import
- dcp_sha_export
- dcp_sha_cra_init
- dcp_sha_cra_exit
- mxs_dcp_irq
- mxs_dcp_probe
- mxs_dcp_remove
1
2
3
4
5
6
7
8 #include <linux/dma-mapping.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/kernel.h>
12 #include <linux/kthread.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/platform_device.h>
16 #include <linux/stmp_device.h>
17 #include <linux/clk.h>
18
19 #include <crypto/aes.h>
20 #include <crypto/sha.h>
21 #include <crypto/internal/hash.h>
22 #include <crypto/internal/skcipher.h>
23 #include <crypto/scatterwalk.h>
24
25 #define DCP_MAX_CHANS 4
26 #define DCP_BUF_SZ PAGE_SIZE
27 #define DCP_SHA_PAY_SZ 64
28
29 #define DCP_ALIGNMENT 64
30
31
32
33
34
35 static const uint8_t sha1_null_hash[] =
36 "\x09\x07\xd8\xaf\x90\x18\x60\x95\xef\xbf"
37 "\x55\x32\x0d\x4b\x6b\x5e\xee\xa3\x39\xda";
38
39 static const uint8_t sha256_null_hash[] =
40 "\x55\xb8\x52\x78\x1b\x99\x95\xa4"
41 "\x4c\x93\x9b\x64\xe4\x41\xae\x27"
42 "\x24\xb9\x6f\x99\xc8\xf4\xfb\x9a"
43 "\x14\x1c\xfc\x98\x42\xc4\xb0\xe3";
44
45
46 struct dcp_dma_desc {
47 uint32_t next_cmd_addr;
48 uint32_t control0;
49 uint32_t control1;
50 uint32_t source;
51 uint32_t destination;
52 uint32_t size;
53 uint32_t payload;
54 uint32_t status;
55 };
56
57
58 struct dcp_coherent_block {
59 uint8_t aes_in_buf[DCP_BUF_SZ];
60 uint8_t aes_out_buf[DCP_BUF_SZ];
61 uint8_t sha_in_buf[DCP_BUF_SZ];
62 uint8_t sha_out_buf[DCP_SHA_PAY_SZ];
63
64 uint8_t aes_key[2 * AES_KEYSIZE_128];
65
66 struct dcp_dma_desc desc[DCP_MAX_CHANS];
67 };
68
69 struct dcp {
70 struct device *dev;
71 void __iomem *base;
72
73 uint32_t caps;
74
75 struct dcp_coherent_block *coh;
76
77 struct completion completion[DCP_MAX_CHANS];
78 spinlock_t lock[DCP_MAX_CHANS];
79 struct task_struct *thread[DCP_MAX_CHANS];
80 struct crypto_queue queue[DCP_MAX_CHANS];
81 struct clk *dcp_clk;
82 };
83
84 enum dcp_chan {
85 DCP_CHAN_HASH_SHA = 0,
86 DCP_CHAN_CRYPTO = 2,
87 };
88
89 struct dcp_async_ctx {
90
91 enum dcp_chan chan;
92 uint32_t fill;
93
94
95 struct mutex mutex;
96 uint32_t alg;
97 unsigned int hot:1;
98
99
100 struct crypto_sync_skcipher *fallback;
101 unsigned int key_len;
102 uint8_t key[AES_KEYSIZE_128];
103 };
104
105 struct dcp_aes_req_ctx {
106 unsigned int enc:1;
107 unsigned int ecb:1;
108 };
109
110 struct dcp_sha_req_ctx {
111 unsigned int init:1;
112 unsigned int fini:1;
113 };
114
115 struct dcp_export_state {
116 struct dcp_sha_req_ctx req_ctx;
117 struct dcp_async_ctx async_ctx;
118 };
119
120
121
122
123
124 static struct dcp *global_sdcp;
125
126
127 #define MXS_DCP_CTRL 0x00
128 #define MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES (1 << 23)
129 #define MXS_DCP_CTRL_ENABLE_CONTEXT_CACHING (1 << 22)
130
131 #define MXS_DCP_STAT 0x10
132 #define MXS_DCP_STAT_CLR 0x18
133 #define MXS_DCP_STAT_IRQ_MASK 0xf
134
135 #define MXS_DCP_CHANNELCTRL 0x20
136 #define MXS_DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK 0xff
137
138 #define MXS_DCP_CAPABILITY1 0x40
139 #define MXS_DCP_CAPABILITY1_SHA256 (4 << 16)
140 #define MXS_DCP_CAPABILITY1_SHA1 (1 << 16)
141 #define MXS_DCP_CAPABILITY1_AES128 (1 << 0)
142
143 #define MXS_DCP_CONTEXT 0x50
144
145 #define MXS_DCP_CH_N_CMDPTR(n) (0x100 + ((n) * 0x40))
146
147 #define MXS_DCP_CH_N_SEMA(n) (0x110 + ((n) * 0x40))
148
149 #define MXS_DCP_CH_N_STAT(n) (0x120 + ((n) * 0x40))
150 #define MXS_DCP_CH_N_STAT_CLR(n) (0x128 + ((n) * 0x40))
151
152
153 #define MXS_DCP_CONTROL0_HASH_TERM (1 << 13)
154 #define MXS_DCP_CONTROL0_HASH_INIT (1 << 12)
155 #define MXS_DCP_CONTROL0_PAYLOAD_KEY (1 << 11)
156 #define MXS_DCP_CONTROL0_CIPHER_ENCRYPT (1 << 8)
157 #define MXS_DCP_CONTROL0_CIPHER_INIT (1 << 9)
158 #define MXS_DCP_CONTROL0_ENABLE_HASH (1 << 6)
159 #define MXS_DCP_CONTROL0_ENABLE_CIPHER (1 << 5)
160 #define MXS_DCP_CONTROL0_DECR_SEMAPHORE (1 << 1)
161 #define MXS_DCP_CONTROL0_INTERRUPT (1 << 0)
162
163 #define MXS_DCP_CONTROL1_HASH_SELECT_SHA256 (2 << 16)
164 #define MXS_DCP_CONTROL1_HASH_SELECT_SHA1 (0 << 16)
165 #define MXS_DCP_CONTROL1_CIPHER_MODE_CBC (1 << 4)
166 #define MXS_DCP_CONTROL1_CIPHER_MODE_ECB (0 << 4)
167 #define MXS_DCP_CONTROL1_CIPHER_SELECT_AES128 (0 << 0)
168
169 static int mxs_dcp_start_dma(struct dcp_async_ctx *actx)
170 {
171 struct dcp *sdcp = global_sdcp;
172 const int chan = actx->chan;
173 uint32_t stat;
174 unsigned long ret;
175 struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan];
176
177 dma_addr_t desc_phys = dma_map_single(sdcp->dev, desc, sizeof(*desc),
178 DMA_TO_DEVICE);
179
180 reinit_completion(&sdcp->completion[chan]);
181
182
183 writel(0xffffffff, sdcp->base + MXS_DCP_CH_N_STAT_CLR(chan));
184
185
186 writel(desc_phys, sdcp->base + MXS_DCP_CH_N_CMDPTR(chan));
187
188
189 writel(1, sdcp->base + MXS_DCP_CH_N_SEMA(chan));
190
191 ret = wait_for_completion_timeout(&sdcp->completion[chan],
192 msecs_to_jiffies(1000));
193 if (!ret) {
194 dev_err(sdcp->dev, "Channel %i timeout (DCP_STAT=0x%08x)\n",
195 chan, readl(sdcp->base + MXS_DCP_STAT));
196 return -ETIMEDOUT;
197 }
198
199 stat = readl(sdcp->base + MXS_DCP_CH_N_STAT(chan));
200 if (stat & 0xff) {
201 dev_err(sdcp->dev, "Channel %i error (CH_STAT=0x%08x)\n",
202 chan, stat);
203 return -EINVAL;
204 }
205
206 dma_unmap_single(sdcp->dev, desc_phys, sizeof(*desc), DMA_TO_DEVICE);
207
208 return 0;
209 }
210
211
212
213
214 static int mxs_dcp_run_aes(struct dcp_async_ctx *actx,
215 struct ablkcipher_request *req, int init)
216 {
217 struct dcp *sdcp = global_sdcp;
218 struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan];
219 struct dcp_aes_req_ctx *rctx = ablkcipher_request_ctx(req);
220 int ret;
221
222 dma_addr_t key_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_key,
223 2 * AES_KEYSIZE_128,
224 DMA_TO_DEVICE);
225 dma_addr_t src_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_in_buf,
226 DCP_BUF_SZ, DMA_TO_DEVICE);
227 dma_addr_t dst_phys = dma_map_single(sdcp->dev, sdcp->coh->aes_out_buf,
228 DCP_BUF_SZ, DMA_FROM_DEVICE);
229
230 if (actx->fill % AES_BLOCK_SIZE) {
231 dev_err(sdcp->dev, "Invalid block size!\n");
232 ret = -EINVAL;
233 goto aes_done_run;
234 }
235
236
237 desc->control0 = MXS_DCP_CONTROL0_DECR_SEMAPHORE |
238 MXS_DCP_CONTROL0_INTERRUPT |
239 MXS_DCP_CONTROL0_ENABLE_CIPHER;
240
241
242 desc->control0 |= MXS_DCP_CONTROL0_PAYLOAD_KEY;
243
244 if (rctx->enc)
245 desc->control0 |= MXS_DCP_CONTROL0_CIPHER_ENCRYPT;
246 if (init)
247 desc->control0 |= MXS_DCP_CONTROL0_CIPHER_INIT;
248
249 desc->control1 = MXS_DCP_CONTROL1_CIPHER_SELECT_AES128;
250
251 if (rctx->ecb)
252 desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_ECB;
253 else
254 desc->control1 |= MXS_DCP_CONTROL1_CIPHER_MODE_CBC;
255
256 desc->next_cmd_addr = 0;
257 desc->source = src_phys;
258 desc->destination = dst_phys;
259 desc->size = actx->fill;
260 desc->payload = key_phys;
261 desc->status = 0;
262
263 ret = mxs_dcp_start_dma(actx);
264
265 aes_done_run:
266 dma_unmap_single(sdcp->dev, key_phys, 2 * AES_KEYSIZE_128,
267 DMA_TO_DEVICE);
268 dma_unmap_single(sdcp->dev, src_phys, DCP_BUF_SZ, DMA_TO_DEVICE);
269 dma_unmap_single(sdcp->dev, dst_phys, DCP_BUF_SZ, DMA_FROM_DEVICE);
270
271 return ret;
272 }
273
274 static int mxs_dcp_aes_block_crypt(struct crypto_async_request *arq)
275 {
276 struct dcp *sdcp = global_sdcp;
277
278 struct ablkcipher_request *req = ablkcipher_request_cast(arq);
279 struct dcp_async_ctx *actx = crypto_tfm_ctx(arq->tfm);
280 struct dcp_aes_req_ctx *rctx = ablkcipher_request_ctx(req);
281
282 struct scatterlist *dst = req->dst;
283 struct scatterlist *src = req->src;
284 const int nents = sg_nents(req->src);
285
286 const int out_off = DCP_BUF_SZ;
287 uint8_t *in_buf = sdcp->coh->aes_in_buf;
288 uint8_t *out_buf = sdcp->coh->aes_out_buf;
289
290 uint8_t *out_tmp, *src_buf, *dst_buf = NULL;
291 uint32_t dst_off = 0;
292 uint32_t last_out_len = 0;
293
294 uint8_t *key = sdcp->coh->aes_key;
295
296 int ret = 0;
297 int split = 0;
298 unsigned int i, len, clen, rem = 0, tlen = 0;
299 int init = 0;
300 bool limit_hit = false;
301
302 actx->fill = 0;
303
304
305 memcpy(key, actx->key, actx->key_len);
306
307 if (!rctx->ecb) {
308
309 memcpy(key + AES_KEYSIZE_128, req->info, AES_KEYSIZE_128);
310
311 init = 1;
312 } else {
313 memset(key + AES_KEYSIZE_128, 0, AES_KEYSIZE_128);
314 }
315
316 for_each_sg(req->src, src, nents, i) {
317 src_buf = sg_virt(src);
318 len = sg_dma_len(src);
319 tlen += len;
320 limit_hit = tlen > req->nbytes;
321
322 if (limit_hit)
323 len = req->nbytes - (tlen - len);
324
325 do {
326 if (actx->fill + len > out_off)
327 clen = out_off - actx->fill;
328 else
329 clen = len;
330
331 memcpy(in_buf + actx->fill, src_buf, clen);
332 len -= clen;
333 src_buf += clen;
334 actx->fill += clen;
335
336
337
338
339
340 if (actx->fill == out_off || sg_is_last(src) ||
341 limit_hit) {
342 ret = mxs_dcp_run_aes(actx, req, init);
343 if (ret)
344 return ret;
345 init = 0;
346
347 out_tmp = out_buf;
348 last_out_len = actx->fill;
349 while (dst && actx->fill) {
350 if (!split) {
351 dst_buf = sg_virt(dst);
352 dst_off = 0;
353 }
354 rem = min(sg_dma_len(dst) - dst_off,
355 actx->fill);
356
357 memcpy(dst_buf + dst_off, out_tmp, rem);
358 out_tmp += rem;
359 dst_off += rem;
360 actx->fill -= rem;
361
362 if (dst_off == sg_dma_len(dst)) {
363 dst = sg_next(dst);
364 split = 0;
365 } else {
366 split = 1;
367 }
368 }
369 }
370 } while (len);
371
372 if (limit_hit)
373 break;
374 }
375
376
377 if (!rctx->ecb) {
378 if (rctx->enc)
379 memcpy(req->info, out_buf+(last_out_len-AES_BLOCK_SIZE),
380 AES_BLOCK_SIZE);
381 else
382 memcpy(req->info, in_buf+(last_out_len-AES_BLOCK_SIZE),
383 AES_BLOCK_SIZE);
384 }
385
386 return ret;
387 }
388
389 static int dcp_chan_thread_aes(void *data)
390 {
391 struct dcp *sdcp = global_sdcp;
392 const int chan = DCP_CHAN_CRYPTO;
393
394 struct crypto_async_request *backlog;
395 struct crypto_async_request *arq;
396
397 int ret;
398
399 while (!kthread_should_stop()) {
400 set_current_state(TASK_INTERRUPTIBLE);
401
402 spin_lock(&sdcp->lock[chan]);
403 backlog = crypto_get_backlog(&sdcp->queue[chan]);
404 arq = crypto_dequeue_request(&sdcp->queue[chan]);
405 spin_unlock(&sdcp->lock[chan]);
406
407 if (!backlog && !arq) {
408 schedule();
409 continue;
410 }
411
412 set_current_state(TASK_RUNNING);
413
414 if (backlog)
415 backlog->complete(backlog, -EINPROGRESS);
416
417 if (arq) {
418 ret = mxs_dcp_aes_block_crypt(arq);
419 arq->complete(arq, ret);
420 }
421 }
422
423 return 0;
424 }
425
426 static int mxs_dcp_block_fallback(struct ablkcipher_request *req, int enc)
427 {
428 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
429 struct dcp_async_ctx *ctx = crypto_ablkcipher_ctx(tfm);
430 SYNC_SKCIPHER_REQUEST_ON_STACK(subreq, ctx->fallback);
431 int ret;
432
433 skcipher_request_set_sync_tfm(subreq, ctx->fallback);
434 skcipher_request_set_callback(subreq, req->base.flags, NULL, NULL);
435 skcipher_request_set_crypt(subreq, req->src, req->dst,
436 req->nbytes, req->info);
437
438 if (enc)
439 ret = crypto_skcipher_encrypt(subreq);
440 else
441 ret = crypto_skcipher_decrypt(subreq);
442
443 skcipher_request_zero(subreq);
444
445 return ret;
446 }
447
448 static int mxs_dcp_aes_enqueue(struct ablkcipher_request *req, int enc, int ecb)
449 {
450 struct dcp *sdcp = global_sdcp;
451 struct crypto_async_request *arq = &req->base;
452 struct dcp_async_ctx *actx = crypto_tfm_ctx(arq->tfm);
453 struct dcp_aes_req_ctx *rctx = ablkcipher_request_ctx(req);
454 int ret;
455
456 if (unlikely(actx->key_len != AES_KEYSIZE_128))
457 return mxs_dcp_block_fallback(req, enc);
458
459 rctx->enc = enc;
460 rctx->ecb = ecb;
461 actx->chan = DCP_CHAN_CRYPTO;
462
463 spin_lock(&sdcp->lock[actx->chan]);
464 ret = crypto_enqueue_request(&sdcp->queue[actx->chan], &req->base);
465 spin_unlock(&sdcp->lock[actx->chan]);
466
467 wake_up_process(sdcp->thread[actx->chan]);
468
469 return ret;
470 }
471
472 static int mxs_dcp_aes_ecb_decrypt(struct ablkcipher_request *req)
473 {
474 return mxs_dcp_aes_enqueue(req, 0, 1);
475 }
476
477 static int mxs_dcp_aes_ecb_encrypt(struct ablkcipher_request *req)
478 {
479 return mxs_dcp_aes_enqueue(req, 1, 1);
480 }
481
482 static int mxs_dcp_aes_cbc_decrypt(struct ablkcipher_request *req)
483 {
484 return mxs_dcp_aes_enqueue(req, 0, 0);
485 }
486
487 static int mxs_dcp_aes_cbc_encrypt(struct ablkcipher_request *req)
488 {
489 return mxs_dcp_aes_enqueue(req, 1, 0);
490 }
491
492 static int mxs_dcp_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
493 unsigned int len)
494 {
495 struct dcp_async_ctx *actx = crypto_ablkcipher_ctx(tfm);
496 unsigned int ret;
497
498
499
500
501
502
503 actx->key_len = len;
504 if (len == AES_KEYSIZE_128) {
505 memcpy(actx->key, key, len);
506 return 0;
507 }
508
509
510
511
512
513
514 crypto_sync_skcipher_clear_flags(actx->fallback, CRYPTO_TFM_REQ_MASK);
515 crypto_sync_skcipher_set_flags(actx->fallback,
516 tfm->base.crt_flags & CRYPTO_TFM_REQ_MASK);
517
518 ret = crypto_sync_skcipher_setkey(actx->fallback, key, len);
519 if (!ret)
520 return 0;
521
522 tfm->base.crt_flags &= ~CRYPTO_TFM_RES_MASK;
523 tfm->base.crt_flags |= crypto_sync_skcipher_get_flags(actx->fallback) &
524 CRYPTO_TFM_RES_MASK;
525
526 return ret;
527 }
528
529 static int mxs_dcp_aes_fallback_init(struct crypto_tfm *tfm)
530 {
531 const char *name = crypto_tfm_alg_name(tfm);
532 struct dcp_async_ctx *actx = crypto_tfm_ctx(tfm);
533 struct crypto_sync_skcipher *blk;
534
535 blk = crypto_alloc_sync_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK);
536 if (IS_ERR(blk))
537 return PTR_ERR(blk);
538
539 actx->fallback = blk;
540 tfm->crt_ablkcipher.reqsize = sizeof(struct dcp_aes_req_ctx);
541 return 0;
542 }
543
544 static void mxs_dcp_aes_fallback_exit(struct crypto_tfm *tfm)
545 {
546 struct dcp_async_ctx *actx = crypto_tfm_ctx(tfm);
547
548 crypto_free_sync_skcipher(actx->fallback);
549 }
550
551
552
553
554 static int mxs_dcp_run_sha(struct ahash_request *req)
555 {
556 struct dcp *sdcp = global_sdcp;
557 int ret;
558
559 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
560 struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
561 struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req);
562 struct dcp_dma_desc *desc = &sdcp->coh->desc[actx->chan];
563
564 dma_addr_t digest_phys = 0;
565 dma_addr_t buf_phys = dma_map_single(sdcp->dev, sdcp->coh->sha_in_buf,
566 DCP_BUF_SZ, DMA_TO_DEVICE);
567
568
569 desc->control0 = MXS_DCP_CONTROL0_DECR_SEMAPHORE |
570 MXS_DCP_CONTROL0_INTERRUPT |
571 MXS_DCP_CONTROL0_ENABLE_HASH;
572 if (rctx->init)
573 desc->control0 |= MXS_DCP_CONTROL0_HASH_INIT;
574
575 desc->control1 = actx->alg;
576 desc->next_cmd_addr = 0;
577 desc->source = buf_phys;
578 desc->destination = 0;
579 desc->size = actx->fill;
580 desc->payload = 0;
581 desc->status = 0;
582
583
584
585
586 if (rctx->init && rctx->fini && desc->size == 0) {
587 struct hash_alg_common *halg = crypto_hash_alg_common(tfm);
588 const uint8_t *sha_buf =
589 (actx->alg == MXS_DCP_CONTROL1_HASH_SELECT_SHA1) ?
590 sha1_null_hash : sha256_null_hash;
591 memcpy(sdcp->coh->sha_out_buf, sha_buf, halg->digestsize);
592 ret = 0;
593 goto done_run;
594 }
595
596
597 if (rctx->fini) {
598 digest_phys = dma_map_single(sdcp->dev, sdcp->coh->sha_out_buf,
599 DCP_SHA_PAY_SZ, DMA_FROM_DEVICE);
600 desc->control0 |= MXS_DCP_CONTROL0_HASH_TERM;
601 desc->payload = digest_phys;
602 }
603
604 ret = mxs_dcp_start_dma(actx);
605
606 if (rctx->fini)
607 dma_unmap_single(sdcp->dev, digest_phys, DCP_SHA_PAY_SZ,
608 DMA_FROM_DEVICE);
609
610 done_run:
611 dma_unmap_single(sdcp->dev, buf_phys, DCP_BUF_SZ, DMA_TO_DEVICE);
612
613 return ret;
614 }
615
616 static int dcp_sha_req_to_buf(struct crypto_async_request *arq)
617 {
618 struct dcp *sdcp = global_sdcp;
619
620 struct ahash_request *req = ahash_request_cast(arq);
621 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
622 struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
623 struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req);
624 struct hash_alg_common *halg = crypto_hash_alg_common(tfm);
625
626 uint8_t *in_buf = sdcp->coh->sha_in_buf;
627 uint8_t *out_buf = sdcp->coh->sha_out_buf;
628
629 struct scatterlist *src;
630
631 unsigned int i, len, clen, oft = 0;
632 int ret;
633
634 int fin = rctx->fini;
635 if (fin)
636 rctx->fini = 0;
637
638 src = req->src;
639 len = req->nbytes;
640
641 while (len) {
642 if (actx->fill + len > DCP_BUF_SZ)
643 clen = DCP_BUF_SZ - actx->fill;
644 else
645 clen = len;
646
647 scatterwalk_map_and_copy(in_buf + actx->fill, src, oft, clen,
648 0);
649
650 len -= clen;
651 oft += clen;
652 actx->fill += clen;
653
654
655
656
657
658 if (len && actx->fill == DCP_BUF_SZ) {
659 ret = mxs_dcp_run_sha(req);
660 if (ret)
661 return ret;
662 actx->fill = 0;
663 rctx->init = 0;
664 }
665 }
666
667 if (fin) {
668 rctx->fini = 1;
669
670
671 if (!req->result)
672 return -EINVAL;
673
674 ret = mxs_dcp_run_sha(req);
675 if (ret)
676 return ret;
677
678 actx->fill = 0;
679
680
681 for (i = 0; i < halg->digestsize; i++)
682 req->result[i] = out_buf[halg->digestsize - i - 1];
683 }
684
685 return 0;
686 }
687
688 static int dcp_chan_thread_sha(void *data)
689 {
690 struct dcp *sdcp = global_sdcp;
691 const int chan = DCP_CHAN_HASH_SHA;
692
693 struct crypto_async_request *backlog;
694 struct crypto_async_request *arq;
695 int ret;
696
697 while (!kthread_should_stop()) {
698 set_current_state(TASK_INTERRUPTIBLE);
699
700 spin_lock(&sdcp->lock[chan]);
701 backlog = crypto_get_backlog(&sdcp->queue[chan]);
702 arq = crypto_dequeue_request(&sdcp->queue[chan]);
703 spin_unlock(&sdcp->lock[chan]);
704
705 if (!backlog && !arq) {
706 schedule();
707 continue;
708 }
709
710 set_current_state(TASK_RUNNING);
711
712 if (backlog)
713 backlog->complete(backlog, -EINPROGRESS);
714
715 if (arq) {
716 ret = dcp_sha_req_to_buf(arq);
717 arq->complete(arq, ret);
718 }
719 }
720
721 return 0;
722 }
723
724 static int dcp_sha_init(struct ahash_request *req)
725 {
726 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
727 struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
728
729 struct hash_alg_common *halg = crypto_hash_alg_common(tfm);
730
731
732
733
734
735 memset(actx, 0, sizeof(*actx));
736
737 if (strcmp(halg->base.cra_name, "sha1") == 0)
738 actx->alg = MXS_DCP_CONTROL1_HASH_SELECT_SHA1;
739 else
740 actx->alg = MXS_DCP_CONTROL1_HASH_SELECT_SHA256;
741
742 actx->fill = 0;
743 actx->hot = 0;
744 actx->chan = DCP_CHAN_HASH_SHA;
745
746 mutex_init(&actx->mutex);
747
748 return 0;
749 }
750
751 static int dcp_sha_update_fx(struct ahash_request *req, int fini)
752 {
753 struct dcp *sdcp = global_sdcp;
754
755 struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req);
756 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
757 struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
758
759 int ret;
760
761
762
763
764
765 if (!req->nbytes && !fini)
766 return 0;
767
768 mutex_lock(&actx->mutex);
769
770 rctx->fini = fini;
771
772 if (!actx->hot) {
773 actx->hot = 1;
774 rctx->init = 1;
775 }
776
777 spin_lock(&sdcp->lock[actx->chan]);
778 ret = crypto_enqueue_request(&sdcp->queue[actx->chan], &req->base);
779 spin_unlock(&sdcp->lock[actx->chan]);
780
781 wake_up_process(sdcp->thread[actx->chan]);
782 mutex_unlock(&actx->mutex);
783
784 return ret;
785 }
786
787 static int dcp_sha_update(struct ahash_request *req)
788 {
789 return dcp_sha_update_fx(req, 0);
790 }
791
792 static int dcp_sha_final(struct ahash_request *req)
793 {
794 ahash_request_set_crypt(req, NULL, req->result, 0);
795 req->nbytes = 0;
796 return dcp_sha_update_fx(req, 1);
797 }
798
799 static int dcp_sha_finup(struct ahash_request *req)
800 {
801 return dcp_sha_update_fx(req, 1);
802 }
803
804 static int dcp_sha_digest(struct ahash_request *req)
805 {
806 int ret;
807
808 ret = dcp_sha_init(req);
809 if (ret)
810 return ret;
811
812 return dcp_sha_finup(req);
813 }
814
815 static int dcp_sha_import(struct ahash_request *req, const void *in)
816 {
817 struct dcp_sha_req_ctx *rctx = ahash_request_ctx(req);
818 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
819 struct dcp_async_ctx *actx = crypto_ahash_ctx(tfm);
820 const struct dcp_export_state *export = in;
821
822 memset(rctx, 0, sizeof(struct dcp_sha_req_ctx));
823 memset(actx, 0, sizeof(struct dcp_async_ctx));
824 memcpy(rctx, &export->req_ctx, sizeof(struct dcp_sha_req_ctx));
825 memcpy(actx, &export->async_ctx, sizeof(struct dcp_async_ctx));
826
827 return 0;
828 }
829
830 static int dcp_sha_export(struct ahash_request *req, void *out)
831 {
832 struct dcp_sha_req_ctx *rctx_state = ahash_request_ctx(req);
833 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
834 struct dcp_async_ctx *actx_state = crypto_ahash_ctx(tfm);
835 struct dcp_export_state *export = out;
836
837 memcpy(&export->req_ctx, rctx_state, sizeof(struct dcp_sha_req_ctx));
838 memcpy(&export->async_ctx, actx_state, sizeof(struct dcp_async_ctx));
839
840 return 0;
841 }
842
843 static int dcp_sha_cra_init(struct crypto_tfm *tfm)
844 {
845 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
846 sizeof(struct dcp_sha_req_ctx));
847 return 0;
848 }
849
850 static void dcp_sha_cra_exit(struct crypto_tfm *tfm)
851 {
852 }
853
854
855 static struct crypto_alg dcp_aes_algs[] = {
856 {
857 .cra_name = "ecb(aes)",
858 .cra_driver_name = "ecb-aes-dcp",
859 .cra_priority = 400,
860 .cra_alignmask = 15,
861 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
862 CRYPTO_ALG_ASYNC |
863 CRYPTO_ALG_NEED_FALLBACK,
864 .cra_init = mxs_dcp_aes_fallback_init,
865 .cra_exit = mxs_dcp_aes_fallback_exit,
866 .cra_blocksize = AES_BLOCK_SIZE,
867 .cra_ctxsize = sizeof(struct dcp_async_ctx),
868 .cra_type = &crypto_ablkcipher_type,
869 .cra_module = THIS_MODULE,
870 .cra_u = {
871 .ablkcipher = {
872 .min_keysize = AES_MIN_KEY_SIZE,
873 .max_keysize = AES_MAX_KEY_SIZE,
874 .setkey = mxs_dcp_aes_setkey,
875 .encrypt = mxs_dcp_aes_ecb_encrypt,
876 .decrypt = mxs_dcp_aes_ecb_decrypt
877 },
878 },
879 }, {
880 .cra_name = "cbc(aes)",
881 .cra_driver_name = "cbc-aes-dcp",
882 .cra_priority = 400,
883 .cra_alignmask = 15,
884 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
885 CRYPTO_ALG_ASYNC |
886 CRYPTO_ALG_NEED_FALLBACK,
887 .cra_init = mxs_dcp_aes_fallback_init,
888 .cra_exit = mxs_dcp_aes_fallback_exit,
889 .cra_blocksize = AES_BLOCK_SIZE,
890 .cra_ctxsize = sizeof(struct dcp_async_ctx),
891 .cra_type = &crypto_ablkcipher_type,
892 .cra_module = THIS_MODULE,
893 .cra_u = {
894 .ablkcipher = {
895 .min_keysize = AES_MIN_KEY_SIZE,
896 .max_keysize = AES_MAX_KEY_SIZE,
897 .setkey = mxs_dcp_aes_setkey,
898 .encrypt = mxs_dcp_aes_cbc_encrypt,
899 .decrypt = mxs_dcp_aes_cbc_decrypt,
900 .ivsize = AES_BLOCK_SIZE,
901 },
902 },
903 },
904 };
905
906
907 static struct ahash_alg dcp_sha1_alg = {
908 .init = dcp_sha_init,
909 .update = dcp_sha_update,
910 .final = dcp_sha_final,
911 .finup = dcp_sha_finup,
912 .digest = dcp_sha_digest,
913 .import = dcp_sha_import,
914 .export = dcp_sha_export,
915 .halg = {
916 .digestsize = SHA1_DIGEST_SIZE,
917 .statesize = sizeof(struct dcp_export_state),
918 .base = {
919 .cra_name = "sha1",
920 .cra_driver_name = "sha1-dcp",
921 .cra_priority = 400,
922 .cra_alignmask = 63,
923 .cra_flags = CRYPTO_ALG_ASYNC,
924 .cra_blocksize = SHA1_BLOCK_SIZE,
925 .cra_ctxsize = sizeof(struct dcp_async_ctx),
926 .cra_module = THIS_MODULE,
927 .cra_init = dcp_sha_cra_init,
928 .cra_exit = dcp_sha_cra_exit,
929 },
930 },
931 };
932
933
934 static struct ahash_alg dcp_sha256_alg = {
935 .init = dcp_sha_init,
936 .update = dcp_sha_update,
937 .final = dcp_sha_final,
938 .finup = dcp_sha_finup,
939 .digest = dcp_sha_digest,
940 .import = dcp_sha_import,
941 .export = dcp_sha_export,
942 .halg = {
943 .digestsize = SHA256_DIGEST_SIZE,
944 .statesize = sizeof(struct dcp_export_state),
945 .base = {
946 .cra_name = "sha256",
947 .cra_driver_name = "sha256-dcp",
948 .cra_priority = 400,
949 .cra_alignmask = 63,
950 .cra_flags = CRYPTO_ALG_ASYNC,
951 .cra_blocksize = SHA256_BLOCK_SIZE,
952 .cra_ctxsize = sizeof(struct dcp_async_ctx),
953 .cra_module = THIS_MODULE,
954 .cra_init = dcp_sha_cra_init,
955 .cra_exit = dcp_sha_cra_exit,
956 },
957 },
958 };
959
960 static irqreturn_t mxs_dcp_irq(int irq, void *context)
961 {
962 struct dcp *sdcp = context;
963 uint32_t stat;
964 int i;
965
966 stat = readl(sdcp->base + MXS_DCP_STAT);
967 stat &= MXS_DCP_STAT_IRQ_MASK;
968 if (!stat)
969 return IRQ_NONE;
970
971
972 writel(stat, sdcp->base + MXS_DCP_STAT_CLR);
973
974
975 for (i = 0; i < DCP_MAX_CHANS; i++)
976 if (stat & (1 << i))
977 complete(&sdcp->completion[i]);
978
979 return IRQ_HANDLED;
980 }
981
982 static int mxs_dcp_probe(struct platform_device *pdev)
983 {
984 struct device *dev = &pdev->dev;
985 struct dcp *sdcp = NULL;
986 int i, ret;
987 int dcp_vmi_irq, dcp_irq;
988
989 if (global_sdcp) {
990 dev_err(dev, "Only one DCP instance allowed!\n");
991 return -ENODEV;
992 }
993
994 dcp_vmi_irq = platform_get_irq(pdev, 0);
995 if (dcp_vmi_irq < 0)
996 return dcp_vmi_irq;
997
998 dcp_irq = platform_get_irq(pdev, 1);
999 if (dcp_irq < 0)
1000 return dcp_irq;
1001
1002 sdcp = devm_kzalloc(dev, sizeof(*sdcp), GFP_KERNEL);
1003 if (!sdcp)
1004 return -ENOMEM;
1005
1006 sdcp->dev = dev;
1007 sdcp->base = devm_platform_ioremap_resource(pdev, 0);
1008 if (IS_ERR(sdcp->base))
1009 return PTR_ERR(sdcp->base);
1010
1011
1012 ret = devm_request_irq(dev, dcp_vmi_irq, mxs_dcp_irq, 0,
1013 "dcp-vmi-irq", sdcp);
1014 if (ret) {
1015 dev_err(dev, "Failed to claim DCP VMI IRQ!\n");
1016 return ret;
1017 }
1018
1019 ret = devm_request_irq(dev, dcp_irq, mxs_dcp_irq, 0,
1020 "dcp-irq", sdcp);
1021 if (ret) {
1022 dev_err(dev, "Failed to claim DCP IRQ!\n");
1023 return ret;
1024 }
1025
1026
1027 sdcp->coh = devm_kzalloc(dev, sizeof(*sdcp->coh) + DCP_ALIGNMENT,
1028 GFP_KERNEL);
1029 if (!sdcp->coh)
1030 return -ENOMEM;
1031
1032
1033 sdcp->coh = PTR_ALIGN(sdcp->coh, DCP_ALIGNMENT);
1034
1035
1036 sdcp->dcp_clk = devm_clk_get(dev, "dcp");
1037 if (IS_ERR(sdcp->dcp_clk)) {
1038 if (sdcp->dcp_clk != ERR_PTR(-ENOENT))
1039 return PTR_ERR(sdcp->dcp_clk);
1040 sdcp->dcp_clk = NULL;
1041 }
1042 ret = clk_prepare_enable(sdcp->dcp_clk);
1043 if (ret)
1044 return ret;
1045
1046
1047 ret = stmp_reset_block(sdcp->base);
1048 if (ret) {
1049 dev_err(dev, "Failed reset\n");
1050 goto err_disable_unprepare_clk;
1051 }
1052
1053
1054 writel(MXS_DCP_CTRL_GATHER_RESIDUAL_WRITES |
1055 MXS_DCP_CTRL_ENABLE_CONTEXT_CACHING | 0xf,
1056 sdcp->base + MXS_DCP_CTRL);
1057
1058
1059 writel(MXS_DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK,
1060 sdcp->base + MXS_DCP_CHANNELCTRL);
1061
1062
1063
1064
1065
1066
1067
1068
1069 writel(0xffff0000, sdcp->base + MXS_DCP_CONTEXT);
1070 for (i = 0; i < DCP_MAX_CHANS; i++)
1071 writel(0xffffffff, sdcp->base + MXS_DCP_CH_N_STAT_CLR(i));
1072 writel(0xffffffff, sdcp->base + MXS_DCP_STAT_CLR);
1073
1074 global_sdcp = sdcp;
1075
1076 platform_set_drvdata(pdev, sdcp);
1077
1078 for (i = 0; i < DCP_MAX_CHANS; i++) {
1079 spin_lock_init(&sdcp->lock[i]);
1080 init_completion(&sdcp->completion[i]);
1081 crypto_init_queue(&sdcp->queue[i], 50);
1082 }
1083
1084
1085 sdcp->thread[DCP_CHAN_HASH_SHA] = kthread_run(dcp_chan_thread_sha,
1086 NULL, "mxs_dcp_chan/sha");
1087 if (IS_ERR(sdcp->thread[DCP_CHAN_HASH_SHA])) {
1088 dev_err(dev, "Error starting SHA thread!\n");
1089 ret = PTR_ERR(sdcp->thread[DCP_CHAN_HASH_SHA]);
1090 goto err_disable_unprepare_clk;
1091 }
1092
1093 sdcp->thread[DCP_CHAN_CRYPTO] = kthread_run(dcp_chan_thread_aes,
1094 NULL, "mxs_dcp_chan/aes");
1095 if (IS_ERR(sdcp->thread[DCP_CHAN_CRYPTO])) {
1096 dev_err(dev, "Error starting SHA thread!\n");
1097 ret = PTR_ERR(sdcp->thread[DCP_CHAN_CRYPTO]);
1098 goto err_destroy_sha_thread;
1099 }
1100
1101
1102 sdcp->caps = readl(sdcp->base + MXS_DCP_CAPABILITY1);
1103
1104 if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128) {
1105 ret = crypto_register_algs(dcp_aes_algs,
1106 ARRAY_SIZE(dcp_aes_algs));
1107 if (ret) {
1108
1109 dev_err(dev, "Failed to register AES crypto!\n");
1110 goto err_destroy_aes_thread;
1111 }
1112 }
1113
1114 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1) {
1115 ret = crypto_register_ahash(&dcp_sha1_alg);
1116 if (ret) {
1117 dev_err(dev, "Failed to register %s hash!\n",
1118 dcp_sha1_alg.halg.base.cra_name);
1119 goto err_unregister_aes;
1120 }
1121 }
1122
1123 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA256) {
1124 ret = crypto_register_ahash(&dcp_sha256_alg);
1125 if (ret) {
1126 dev_err(dev, "Failed to register %s hash!\n",
1127 dcp_sha256_alg.halg.base.cra_name);
1128 goto err_unregister_sha1;
1129 }
1130 }
1131
1132 return 0;
1133
1134 err_unregister_sha1:
1135 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1)
1136 crypto_unregister_ahash(&dcp_sha1_alg);
1137
1138 err_unregister_aes:
1139 if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128)
1140 crypto_unregister_algs(dcp_aes_algs, ARRAY_SIZE(dcp_aes_algs));
1141
1142 err_destroy_aes_thread:
1143 kthread_stop(sdcp->thread[DCP_CHAN_CRYPTO]);
1144
1145 err_destroy_sha_thread:
1146 kthread_stop(sdcp->thread[DCP_CHAN_HASH_SHA]);
1147
1148 err_disable_unprepare_clk:
1149 clk_disable_unprepare(sdcp->dcp_clk);
1150
1151 return ret;
1152 }
1153
1154 static int mxs_dcp_remove(struct platform_device *pdev)
1155 {
1156 struct dcp *sdcp = platform_get_drvdata(pdev);
1157
1158 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA256)
1159 crypto_unregister_ahash(&dcp_sha256_alg);
1160
1161 if (sdcp->caps & MXS_DCP_CAPABILITY1_SHA1)
1162 crypto_unregister_ahash(&dcp_sha1_alg);
1163
1164 if (sdcp->caps & MXS_DCP_CAPABILITY1_AES128)
1165 crypto_unregister_algs(dcp_aes_algs, ARRAY_SIZE(dcp_aes_algs));
1166
1167 kthread_stop(sdcp->thread[DCP_CHAN_HASH_SHA]);
1168 kthread_stop(sdcp->thread[DCP_CHAN_CRYPTO]);
1169
1170 clk_disable_unprepare(sdcp->dcp_clk);
1171
1172 platform_set_drvdata(pdev, NULL);
1173
1174 global_sdcp = NULL;
1175
1176 return 0;
1177 }
1178
1179 static const struct of_device_id mxs_dcp_dt_ids[] = {
1180 { .compatible = "fsl,imx23-dcp", .data = NULL, },
1181 { .compatible = "fsl,imx28-dcp", .data = NULL, },
1182 { }
1183 };
1184
1185 MODULE_DEVICE_TABLE(of, mxs_dcp_dt_ids);
1186
1187 static struct platform_driver mxs_dcp_driver = {
1188 .probe = mxs_dcp_probe,
1189 .remove = mxs_dcp_remove,
1190 .driver = {
1191 .name = "mxs-dcp",
1192 .of_match_table = mxs_dcp_dt_ids,
1193 },
1194 };
1195
1196 module_platform_driver(mxs_dcp_driver);
1197
1198 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
1199 MODULE_DESCRIPTION("Freescale MXS DCP Driver");
1200 MODULE_LICENSE("GPL");
1201 MODULE_ALIAS("platform:mxs-dcp");