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6 #ifndef _REGS_V5_H_
7 #define _REGS_V5_H_
8
9 #include <linux/bitops.h>
10
11 #define REG_VERSION 0x000
12 #define REG_STATUS 0x100
13 #define REG_STATUS2 0x104
14 #define REG_ENGINES_AVAIL 0x108
15 #define REG_FIFO_SIZES 0x10c
16 #define REG_SEG_SIZE 0x110
17 #define REG_GOPROC 0x120
18 #define REG_ENCR_SEG_CFG 0x200
19 #define REG_ENCR_SEG_SIZE 0x204
20 #define REG_ENCR_SEG_START 0x208
21 #define REG_CNTR0_IV0 0x20c
22 #define REG_CNTR1_IV1 0x210
23 #define REG_CNTR2_IV2 0x214
24 #define REG_CNTR3_IV3 0x218
25 #define REG_CNTR_MASK 0x21C
26 #define REG_ENCR_CCM_INT_CNTR0 0x220
27 #define REG_ENCR_CCM_INT_CNTR1 0x224
28 #define REG_ENCR_CCM_INT_CNTR2 0x228
29 #define REG_ENCR_CCM_INT_CNTR3 0x22c
30 #define REG_ENCR_XTS_DU_SIZE 0x230
31 #define REG_CNTR_MASK2 0x234
32 #define REG_CNTR_MASK1 0x238
33 #define REG_CNTR_MASK0 0x23c
34 #define REG_AUTH_SEG_CFG 0x300
35 #define REG_AUTH_SEG_SIZE 0x304
36 #define REG_AUTH_SEG_START 0x308
37 #define REG_AUTH_IV0 0x310
38 #define REG_AUTH_IV1 0x314
39 #define REG_AUTH_IV2 0x318
40 #define REG_AUTH_IV3 0x31c
41 #define REG_AUTH_IV4 0x320
42 #define REG_AUTH_IV5 0x324
43 #define REG_AUTH_IV6 0x328
44 #define REG_AUTH_IV7 0x32c
45 #define REG_AUTH_IV8 0x330
46 #define REG_AUTH_IV9 0x334
47 #define REG_AUTH_IV10 0x338
48 #define REG_AUTH_IV11 0x33c
49 #define REG_AUTH_IV12 0x340
50 #define REG_AUTH_IV13 0x344
51 #define REG_AUTH_IV14 0x348
52 #define REG_AUTH_IV15 0x34c
53 #define REG_AUTH_INFO_NONCE0 0x350
54 #define REG_AUTH_INFO_NONCE1 0x354
55 #define REG_AUTH_INFO_NONCE2 0x358
56 #define REG_AUTH_INFO_NONCE3 0x35c
57 #define REG_AUTH_BYTECNT0 0x390
58 #define REG_AUTH_BYTECNT1 0x394
59 #define REG_AUTH_BYTECNT2 0x398
60 #define REG_AUTH_BYTECNT3 0x39c
61 #define REG_AUTH_EXP_MAC0 0x3a0
62 #define REG_AUTH_EXP_MAC1 0x3a4
63 #define REG_AUTH_EXP_MAC2 0x3a8
64 #define REG_AUTH_EXP_MAC3 0x3ac
65 #define REG_AUTH_EXP_MAC4 0x3b0
66 #define REG_AUTH_EXP_MAC5 0x3b4
67 #define REG_AUTH_EXP_MAC6 0x3b8
68 #define REG_AUTH_EXP_MAC7 0x3bc
69 #define REG_CONFIG 0x400
70 #define REG_GOPROC_QC_KEY 0x1000
71 #define REG_GOPROC_OEM_KEY 0x2000
72 #define REG_ENCR_KEY0 0x3000
73 #define REG_ENCR_KEY1 0x3004
74 #define REG_ENCR_KEY2 0x3008
75 #define REG_ENCR_KEY3 0x300c
76 #define REG_ENCR_KEY4 0x3010
77 #define REG_ENCR_KEY5 0x3014
78 #define REG_ENCR_KEY6 0x3018
79 #define REG_ENCR_KEY7 0x301c
80 #define REG_ENCR_XTS_KEY0 0x3020
81 #define REG_ENCR_XTS_KEY1 0x3024
82 #define REG_ENCR_XTS_KEY2 0x3028
83 #define REG_ENCR_XTS_KEY3 0x302c
84 #define REG_ENCR_XTS_KEY4 0x3030
85 #define REG_ENCR_XTS_KEY5 0x3034
86 #define REG_ENCR_XTS_KEY6 0x3038
87 #define REG_ENCR_XTS_KEY7 0x303c
88 #define REG_AUTH_KEY0 0x3040
89 #define REG_AUTH_KEY1 0x3044
90 #define REG_AUTH_KEY2 0x3048
91 #define REG_AUTH_KEY3 0x304c
92 #define REG_AUTH_KEY4 0x3050
93 #define REG_AUTH_KEY5 0x3054
94 #define REG_AUTH_KEY6 0x3058
95 #define REG_AUTH_KEY7 0x305c
96 #define REG_AUTH_KEY8 0x3060
97 #define REG_AUTH_KEY9 0x3064
98 #define REG_AUTH_KEY10 0x3068
99 #define REG_AUTH_KEY11 0x306c
100 #define REG_AUTH_KEY12 0x3070
101 #define REG_AUTH_KEY13 0x3074
102 #define REG_AUTH_KEY14 0x3078
103 #define REG_AUTH_KEY15 0x307c
104
105
106 #define CORE_STEP_REV_SHIFT 0
107 #define CORE_STEP_REV_MASK GENMASK(15, 0)
108 #define CORE_MINOR_REV_SHIFT 16
109 #define CORE_MINOR_REV_MASK GENMASK(23, 16)
110 #define CORE_MAJOR_REV_SHIFT 24
111 #define CORE_MAJOR_REV_MASK GENMASK(31, 24)
112
113
114 #define MAC_FAILED_SHIFT 31
115 #define DOUT_SIZE_AVAIL_SHIFT 26
116 #define DOUT_SIZE_AVAIL_MASK GENMASK(30, 26)
117 #define DIN_SIZE_AVAIL_SHIFT 21
118 #define DIN_SIZE_AVAIL_MASK GENMASK(25, 21)
119 #define HSD_ERR_SHIFT 20
120 #define ACCESS_VIOL_SHIFT 19
121 #define PIPE_ACTIVE_ERR_SHIFT 18
122 #define CFG_CHNG_ERR_SHIFT 17
123 #define DOUT_ERR_SHIFT 16
124 #define DIN_ERR_SHIFT 15
125 #define AXI_ERR_SHIFT 14
126 #define CRYPTO_STATE_SHIFT 10
127 #define CRYPTO_STATE_MASK GENMASK(13, 10)
128 #define ENCR_BUSY_SHIFT 9
129 #define AUTH_BUSY_SHIFT 8
130 #define DOUT_INTR_SHIFT 7
131 #define DIN_INTR_SHIFT 6
132 #define OP_DONE_INTR_SHIFT 5
133 #define ERR_INTR_SHIFT 4
134 #define DOUT_RDY_SHIFT 3
135 #define DIN_RDY_SHIFT 2
136 #define OPERATION_DONE_SHIFT 1
137 #define SW_ERR_SHIFT 0
138
139
140 #define AXI_EXTRA_SHIFT 1
141 #define LOCKED_SHIFT 2
142
143
144 #define REQ_SIZE_SHIFT 17
145 #define REQ_SIZE_MASK GENMASK(20, 17)
146 #define REQ_SIZE_ENUM_1_BEAT 0
147 #define REQ_SIZE_ENUM_2_BEAT 1
148 #define REQ_SIZE_ENUM_3_BEAT 2
149 #define REQ_SIZE_ENUM_4_BEAT 3
150 #define REQ_SIZE_ENUM_5_BEAT 4
151 #define REQ_SIZE_ENUM_6_BEAT 5
152 #define REQ_SIZE_ENUM_7_BEAT 6
153 #define REQ_SIZE_ENUM_8_BEAT 7
154 #define REQ_SIZE_ENUM_9_BEAT 8
155 #define REQ_SIZE_ENUM_10_BEAT 9
156 #define REQ_SIZE_ENUM_11_BEAT 10
157 #define REQ_SIZE_ENUM_12_BEAT 11
158 #define REQ_SIZE_ENUM_13_BEAT 12
159 #define REQ_SIZE_ENUM_14_BEAT 13
160 #define REQ_SIZE_ENUM_15_BEAT 14
161 #define REQ_SIZE_ENUM_16_BEAT 15
162
163 #define MAX_QUEUED_REQ_SHIFT 14
164 #define MAX_QUEUED_REQ_MASK GENMASK(24, 16)
165 #define ENUM_1_QUEUED_REQS 0
166 #define ENUM_2_QUEUED_REQS 1
167 #define ENUM_3_QUEUED_REQS 2
168
169 #define IRQ_ENABLES_SHIFT 10
170 #define IRQ_ENABLES_MASK GENMASK(13, 10)
171
172 #define LITTLE_ENDIAN_MODE_SHIFT 9
173 #define PIPE_SET_SELECT_SHIFT 5
174 #define PIPE_SET_SELECT_MASK GENMASK(8, 5)
175
176 #define HIGH_SPD_EN_N_SHIFT 4
177 #define MASK_DOUT_INTR_SHIFT 3
178 #define MASK_DIN_INTR_SHIFT 2
179 #define MASK_OP_DONE_INTR_SHIFT 1
180 #define MASK_ERR_INTR_SHIFT 0
181
182
183 #define COMP_EXP_MAC_SHIFT 24
184 #define COMP_EXP_MAC_DISABLED 0
185 #define COMP_EXP_MAC_ENABLED 1
186
187 #define F9_DIRECTION_SHIFT 23
188 #define F9_DIRECTION_UPLINK 0
189 #define F9_DIRECTION_DOWNLINK 1
190
191 #define AUTH_NONCE_NUM_WORDS_SHIFT 20
192 #define AUTH_NONCE_NUM_WORDS_MASK GENMASK(22, 20)
193
194 #define USE_PIPE_KEY_AUTH_SHIFT 19
195 #define USE_HW_KEY_AUTH_SHIFT 18
196 #define AUTH_FIRST_SHIFT 17
197 #define AUTH_LAST_SHIFT 16
198
199 #define AUTH_POS_SHIFT 14
200 #define AUTH_POS_MASK GENMASK(15, 14)
201 #define AUTH_POS_BEFORE 0
202 #define AUTH_POS_AFTER 1
203
204 #define AUTH_SIZE_SHIFT 9
205 #define AUTH_SIZE_MASK GENMASK(13, 9)
206 #define AUTH_SIZE_SHA1 0
207 #define AUTH_SIZE_SHA256 1
208 #define AUTH_SIZE_ENUM_1_BYTES 0
209 #define AUTH_SIZE_ENUM_2_BYTES 1
210 #define AUTH_SIZE_ENUM_3_BYTES 2
211 #define AUTH_SIZE_ENUM_4_BYTES 3
212 #define AUTH_SIZE_ENUM_5_BYTES 4
213 #define AUTH_SIZE_ENUM_6_BYTES 5
214 #define AUTH_SIZE_ENUM_7_BYTES 6
215 #define AUTH_SIZE_ENUM_8_BYTES 7
216 #define AUTH_SIZE_ENUM_9_BYTES 8
217 #define AUTH_SIZE_ENUM_10_BYTES 9
218 #define AUTH_SIZE_ENUM_11_BYTES 10
219 #define AUTH_SIZE_ENUM_12_BYTES 11
220 #define AUTH_SIZE_ENUM_13_BYTES 12
221 #define AUTH_SIZE_ENUM_14_BYTES 13
222 #define AUTH_SIZE_ENUM_15_BYTES 14
223 #define AUTH_SIZE_ENUM_16_BYTES 15
224
225 #define AUTH_MODE_SHIFT 6
226 #define AUTH_MODE_MASK GENMASK(8, 6)
227 #define AUTH_MODE_HASH 0
228 #define AUTH_MODE_HMAC 1
229 #define AUTH_MODE_CCM 0
230 #define AUTH_MODE_CMAC 1
231
232 #define AUTH_KEY_SIZE_SHIFT 3
233 #define AUTH_KEY_SIZE_MASK GENMASK(5, 3)
234 #define AUTH_KEY_SZ_AES128 0
235 #define AUTH_KEY_SZ_AES256 2
236
237 #define AUTH_ALG_SHIFT 0
238 #define AUTH_ALG_MASK GENMASK(2, 0)
239 #define AUTH_ALG_NONE 0
240 #define AUTH_ALG_SHA 1
241 #define AUTH_ALG_AES 2
242 #define AUTH_ALG_KASUMI 3
243 #define AUTH_ALG_SNOW3G 4
244 #define AUTH_ALG_ZUC 5
245
246
247 #define ENCR_XTS_DU_SIZE_SHIFT 0
248 #define ENCR_XTS_DU_SIZE_MASK GENMASK(19, 0)
249
250
251 #define F8_KEYSTREAM_ENABLE_SHIFT 17
252 #define F8_KEYSTREAM_DISABLED 0
253 #define F8_KEYSTREAM_ENABLED 1
254
255 #define F8_DIRECTION_SHIFT 16
256 #define F8_DIRECTION_UPLINK 0
257 #define F8_DIRECTION_DOWNLINK 1
258
259 #define USE_PIPE_KEY_ENCR_SHIFT 15
260 #define USE_PIPE_KEY_ENCR_ENABLED 1
261 #define USE_KEY_REGISTERS 0
262
263 #define USE_HW_KEY_ENCR_SHIFT 14
264 #define USE_KEY_REG 0
265 #define USE_HW_KEY 1
266
267 #define LAST_CCM_SHIFT 13
268 #define LAST_CCM_XFR 1
269 #define INTERM_CCM_XFR 0
270
271 #define CNTR_ALG_SHIFT 11
272 #define CNTR_ALG_MASK GENMASK(12, 11)
273 #define CNTR_ALG_NIST 0
274
275 #define ENCODE_SHIFT 10
276
277 #define ENCR_MODE_SHIFT 6
278 #define ENCR_MODE_MASK GENMASK(9, 6)
279 #define ENCR_MODE_ECB 0
280 #define ENCR_MODE_CBC 1
281 #define ENCR_MODE_CTR 2
282 #define ENCR_MODE_XTS 3
283 #define ENCR_MODE_CCM 4
284
285 #define ENCR_KEY_SZ_SHIFT 3
286 #define ENCR_KEY_SZ_MASK GENMASK(5, 3)
287 #define ENCR_KEY_SZ_DES 0
288 #define ENCR_KEY_SZ_3DES 1
289 #define ENCR_KEY_SZ_AES128 0
290 #define ENCR_KEY_SZ_AES256 2
291
292 #define ENCR_ALG_SHIFT 0
293 #define ENCR_ALG_MASK GENMASK(2, 0)
294 #define ENCR_ALG_NONE 0
295 #define ENCR_ALG_DES 1
296 #define ENCR_ALG_AES 2
297 #define ENCR_ALG_KASUMI 4
298 #define ENCR_ALG_SNOW_3G 5
299 #define ENCR_ALG_ZUC 6
300
301
302 #define GO_SHIFT 0
303 #define CLR_CNTXT_SHIFT 1
304 #define RESULTS_DUMP_SHIFT 2
305
306
307 #define ENCR_AES_SEL_SHIFT 0
308 #define DES_SEL_SHIFT 1
309 #define ENCR_SNOW3G_SEL_SHIFT 2
310 #define ENCR_KASUMI_SEL_SHIFT 3
311 #define SHA_SEL_SHIFT 4
312 #define SHA512_SEL_SHIFT 5
313 #define AUTH_AES_SEL_SHIFT 6
314 #define AUTH_SNOW3G_SEL_SHIFT 7
315 #define AUTH_KASUMI_SEL_SHIFT 8
316 #define BAM_PIPE_SETS_SHIFT 9
317 #define BAM_PIPE_SETS_MASK GENMASK(12, 9)
318 #define AXI_WR_BEATS_SHIFT 13
319 #define AXI_WR_BEATS_MASK GENMASK(18, 13)
320 #define AXI_RD_BEATS_SHIFT 19
321 #define AXI_RD_BEATS_MASK GENMASK(24, 19)
322 #define ENCR_ZUC_SEL_SHIFT 26
323 #define AUTH_ZUC_SEL_SHIFT 27
324 #define ZUC_ENABLE_SHIFT 28
325
326 #endif