root/drivers/crypto/qat/qat_common/icp_qat_hal.h

INCLUDED FROM

   1 /*
   2   This file is provided under a dual BSD/GPLv2 license.  When using or
   3   redistributing this file, you may do so under either license.
   4 
   5   GPL LICENSE SUMMARY
   6   Copyright(c) 2014 Intel Corporation.
   7   This program is free software; you can redistribute it and/or modify
   8   it under the terms of version 2 of the GNU General Public License as
   9   published by the Free Software Foundation.
  10 
  11   This program is distributed in the hope that it will be useful, but
  12   WITHOUT ANY WARRANTY; without even the implied warranty of
  13   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14   General Public License for more details.
  15 
  16   Contact Information:
  17   qat-linux@intel.com
  18 
  19   BSD LICENSE
  20   Copyright(c) 2014 Intel Corporation.
  21   Redistribution and use in source and binary forms, with or without
  22   modification, are permitted provided that the following conditions
  23   are met:
  24 
  25     * Redistributions of source code must retain the above copyright
  26       notice, this list of conditions and the following disclaimer.
  27     * Redistributions in binary form must reproduce the above copyright
  28       notice, this list of conditions and the following disclaimer in
  29       the documentation and/or other materials provided with the
  30       distribution.
  31     * Neither the name of Intel Corporation nor the names of its
  32       contributors may be used to endorse or promote products derived
  33       from this software without specific prior written permission.
  34 
  35   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  36   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  37   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  38   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  39   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  40   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  41   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  42   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  43   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  44   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  45   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  46 */
  47 #ifndef __ICP_QAT_HAL_H
  48 #define __ICP_QAT_HAL_H
  49 #include "icp_qat_fw_loader_handle.h"
  50 
  51 enum hal_global_csr {
  52         MISC_CONTROL = 0x04,
  53         ICP_RESET = 0x0c,
  54         ICP_GLOBAL_CLK_ENABLE = 0x50
  55 };
  56 
  57 enum hal_ae_csr {
  58         USTORE_ADDRESS = 0x000,
  59         USTORE_DATA_LOWER = 0x004,
  60         USTORE_DATA_UPPER = 0x008,
  61         ALU_OUT = 0x010,
  62         CTX_ARB_CNTL = 0x014,
  63         CTX_ENABLES = 0x018,
  64         CC_ENABLE = 0x01c,
  65         CSR_CTX_POINTER = 0x020,
  66         CTX_STS_INDIRECT = 0x040,
  67         ACTIVE_CTX_STATUS = 0x044,
  68         CTX_SIG_EVENTS_INDIRECT = 0x048,
  69         CTX_SIG_EVENTS_ACTIVE = 0x04c,
  70         CTX_WAKEUP_EVENTS_INDIRECT = 0x050,
  71         LM_ADDR_0_INDIRECT = 0x060,
  72         LM_ADDR_1_INDIRECT = 0x068,
  73         INDIRECT_LM_ADDR_0_BYTE_INDEX = 0x0e0,
  74         INDIRECT_LM_ADDR_1_BYTE_INDEX = 0x0e8,
  75         FUTURE_COUNT_SIGNAL_INDIRECT = 0x078,
  76         TIMESTAMP_LOW = 0x0c0,
  77         TIMESTAMP_HIGH = 0x0c4,
  78         PROFILE_COUNT = 0x144,
  79         SIGNATURE_ENABLE = 0x150,
  80         AE_MISC_CONTROL = 0x160,
  81         LOCAL_CSR_STATUS = 0x180,
  82 };
  83 
  84 enum fcu_csr {
  85         FCU_CONTROL           = 0x8c0,
  86         FCU_STATUS            = 0x8c4,
  87         FCU_STATUS1           = 0x8c8,
  88         FCU_DRAM_ADDR_LO      = 0x8cc,
  89         FCU_DRAM_ADDR_HI      = 0x8d0,
  90         FCU_RAMBASE_ADDR_HI   = 0x8d4,
  91         FCU_RAMBASE_ADDR_LO   = 0x8d8
  92 };
  93 
  94 enum fcu_cmd {
  95         FCU_CTRL_CMD_NOOP  = 0,
  96         FCU_CTRL_CMD_AUTH  = 1,
  97         FCU_CTRL_CMD_LOAD  = 2,
  98         FCU_CTRL_CMD_START = 3
  99 };
 100 
 101 enum fcu_sts {
 102         FCU_STS_NO_STS    = 0,
 103         FCU_STS_VERI_DONE = 1,
 104         FCU_STS_LOAD_DONE = 2,
 105         FCU_STS_VERI_FAIL = 3,
 106         FCU_STS_LOAD_FAIL = 4,
 107         FCU_STS_BUSY      = 5
 108 };
 109 #define UA_ECS                      (0x1 << 31)
 110 #define ACS_ABO_BITPOS              31
 111 #define ACS_ACNO                    0x7
 112 #define CE_ENABLE_BITPOS            0x8
 113 #define CE_LMADDR_0_GLOBAL_BITPOS   16
 114 #define CE_LMADDR_1_GLOBAL_BITPOS   17
 115 #define CE_NN_MODE_BITPOS           20
 116 #define CE_REG_PAR_ERR_BITPOS       25
 117 #define CE_BREAKPOINT_BITPOS        27
 118 #define CE_CNTL_STORE_PARITY_ERROR_BITPOS 29
 119 #define CE_INUSE_CONTEXTS_BITPOS    31
 120 #define CE_NN_MODE                  (0x1 << CE_NN_MODE_BITPOS)
 121 #define CE_INUSE_CONTEXTS           (0x1 << CE_INUSE_CONTEXTS_BITPOS)
 122 #define XCWE_VOLUNTARY              (0x1)
 123 #define LCS_STATUS          (0x1)
 124 #define MMC_SHARE_CS_BITPOS         2
 125 #define GLOBAL_CSR                0xA00
 126 #define FCU_CTRL_AE_POS     0x8
 127 #define FCU_AUTH_STS_MASK   0x7
 128 #define FCU_STS_DONE_POS    0x9
 129 #define FCU_STS_AUTHFWLD_POS 0X8
 130 #define FCU_LOADED_AE_POS   0x16
 131 #define FW_AUTH_WAIT_PERIOD 10
 132 #define FW_AUTH_MAX_RETRY   300
 133 
 134 #define SET_CAP_CSR(handle, csr, val) \
 135         ADF_CSR_WR(handle->hal_cap_g_ctl_csr_addr_v, csr, val)
 136 #define GET_CAP_CSR(handle, csr) \
 137         ADF_CSR_RD(handle->hal_cap_g_ctl_csr_addr_v, csr)
 138 #define SET_GLB_CSR(handle, csr, val) SET_CAP_CSR(handle, csr + GLOBAL_CSR, val)
 139 #define GET_GLB_CSR(handle, csr) GET_CAP_CSR(handle, GLOBAL_CSR + csr)
 140 #define AE_CSR(handle, ae) \
 141         ((char __iomem *)handle->hal_cap_ae_local_csr_addr_v + \
 142         ((ae & handle->hal_handle->ae_mask) << 12))
 143 #define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & csr))
 144 #define SET_AE_CSR(handle, ae, csr, val) \
 145         ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val)
 146 #define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0)
 147 #define AE_XFER(handle, ae) \
 148         ((char __iomem *)handle->hal_cap_ae_xfer_csr_addr_v + \
 149         ((ae & handle->hal_handle->ae_mask) << 12))
 150 #define AE_XFER_ADDR(handle, ae, reg) (AE_XFER(handle, ae) + \
 151         ((reg & 0xff) << 2))
 152 #define SET_AE_XFER(handle, ae, reg, val) \
 153         ADF_CSR_WR(AE_XFER_ADDR(handle, ae, reg), 0, val)
 154 #define SRAM_WRITE(handle, addr, val) \
 155         ADF_CSR_WR(handle->hal_sram_addr_v, addr, val)
 156 #endif