root/drivers/crypto/qat/qat_common/icp_qat_hw.h

INCLUDED FROM

   1 /*
   2   This file is provided under a dual BSD/GPLv2 license.  When using or
   3   redistributing this file, you may do so under either license.
   4 
   5   GPL LICENSE SUMMARY
   6   Copyright(c) 2014 Intel Corporation.
   7   This program is free software; you can redistribute it and/or modify
   8   it under the terms of version 2 of the GNU General Public License as
   9   published by the Free Software Foundation.
  10 
  11   This program is distributed in the hope that it will be useful, but
  12   WITHOUT ANY WARRANTY; without even the implied warranty of
  13   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14   General Public License for more details.
  15 
  16   Contact Information:
  17   qat-linux@intel.com
  18 
  19   BSD LICENSE
  20   Copyright(c) 2014 Intel Corporation.
  21   Redistribution and use in source and binary forms, with or without
  22   modification, are permitted provided that the following conditions
  23   are met:
  24 
  25     * Redistributions of source code must retain the above copyright
  26       notice, this list of conditions and the following disclaimer.
  27     * Redistributions in binary form must reproduce the above copyright
  28       notice, this list of conditions and the following disclaimer in
  29       the documentation and/or other materials provided with the
  30       distribution.
  31     * Neither the name of Intel Corporation nor the names of its
  32       contributors may be used to endorse or promote products derived
  33       from this software without specific prior written permission.
  34 
  35   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  36   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  37   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  38   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  39   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  40   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  41   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  42   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  43   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  44   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  45   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  46 */
  47 #ifndef _ICP_QAT_HW_H_
  48 #define _ICP_QAT_HW_H_
  49 
  50 enum icp_qat_hw_ae_id {
  51         ICP_QAT_HW_AE_0 = 0,
  52         ICP_QAT_HW_AE_1 = 1,
  53         ICP_QAT_HW_AE_2 = 2,
  54         ICP_QAT_HW_AE_3 = 3,
  55         ICP_QAT_HW_AE_4 = 4,
  56         ICP_QAT_HW_AE_5 = 5,
  57         ICP_QAT_HW_AE_6 = 6,
  58         ICP_QAT_HW_AE_7 = 7,
  59         ICP_QAT_HW_AE_8 = 8,
  60         ICP_QAT_HW_AE_9 = 9,
  61         ICP_QAT_HW_AE_10 = 10,
  62         ICP_QAT_HW_AE_11 = 11,
  63         ICP_QAT_HW_AE_DELIMITER = 12
  64 };
  65 
  66 enum icp_qat_hw_qat_id {
  67         ICP_QAT_HW_QAT_0 = 0,
  68         ICP_QAT_HW_QAT_1 = 1,
  69         ICP_QAT_HW_QAT_2 = 2,
  70         ICP_QAT_HW_QAT_3 = 3,
  71         ICP_QAT_HW_QAT_4 = 4,
  72         ICP_QAT_HW_QAT_5 = 5,
  73         ICP_QAT_HW_QAT_DELIMITER = 6
  74 };
  75 
  76 enum icp_qat_hw_auth_algo {
  77         ICP_QAT_HW_AUTH_ALGO_NULL = 0,
  78         ICP_QAT_HW_AUTH_ALGO_SHA1 = 1,
  79         ICP_QAT_HW_AUTH_ALGO_MD5 = 2,
  80         ICP_QAT_HW_AUTH_ALGO_SHA224 = 3,
  81         ICP_QAT_HW_AUTH_ALGO_SHA256 = 4,
  82         ICP_QAT_HW_AUTH_ALGO_SHA384 = 5,
  83         ICP_QAT_HW_AUTH_ALGO_SHA512 = 6,
  84         ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC = 7,
  85         ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC = 8,
  86         ICP_QAT_HW_AUTH_ALGO_AES_F9 = 9,
  87         ICP_QAT_HW_AUTH_ALGO_GALOIS_128 = 10,
  88         ICP_QAT_HW_AUTH_ALGO_GALOIS_64 = 11,
  89         ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 = 12,
  90         ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 = 13,
  91         ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 = 14,
  92         ICP_QAT_HW_AUTH_RESERVED_1 = 15,
  93         ICP_QAT_HW_AUTH_RESERVED_2 = 16,
  94         ICP_QAT_HW_AUTH_ALGO_SHA3_256 = 17,
  95         ICP_QAT_HW_AUTH_RESERVED_3 = 18,
  96         ICP_QAT_HW_AUTH_ALGO_SHA3_512 = 19,
  97         ICP_QAT_HW_AUTH_ALGO_DELIMITER = 20
  98 };
  99 
 100 enum icp_qat_hw_auth_mode {
 101         ICP_QAT_HW_AUTH_MODE0 = 0,
 102         ICP_QAT_HW_AUTH_MODE1 = 1,
 103         ICP_QAT_HW_AUTH_MODE2 = 2,
 104         ICP_QAT_HW_AUTH_MODE_DELIMITER = 3
 105 };
 106 
 107 struct icp_qat_hw_auth_config {
 108         uint32_t config;
 109         uint32_t reserved;
 110 };
 111 
 112 #define QAT_AUTH_MODE_BITPOS 4
 113 #define QAT_AUTH_MODE_MASK 0xF
 114 #define QAT_AUTH_ALGO_BITPOS 0
 115 #define QAT_AUTH_ALGO_MASK 0xF
 116 #define QAT_AUTH_CMP_BITPOS 8
 117 #define QAT_AUTH_CMP_MASK 0x7F
 118 #define QAT_AUTH_SHA3_PADDING_BITPOS 16
 119 #define QAT_AUTH_SHA3_PADDING_MASK 0x1
 120 #define QAT_AUTH_ALGO_SHA3_BITPOS 22
 121 #define QAT_AUTH_ALGO_SHA3_MASK 0x3
 122 #define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \
 123         (((mode & QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) | \
 124         ((algo & QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) | \
 125         (((algo >> 4) & QAT_AUTH_ALGO_SHA3_MASK) << \
 126          QAT_AUTH_ALGO_SHA3_BITPOS) | \
 127          (((((algo == ICP_QAT_HW_AUTH_ALGO_SHA3_256) || \
 128         (algo == ICP_QAT_HW_AUTH_ALGO_SHA3_512)) ? 1 : 0) \
 129         & QAT_AUTH_SHA3_PADDING_MASK) << QAT_AUTH_SHA3_PADDING_BITPOS) | \
 130         ((cmp_len & QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS))
 131 
 132 struct icp_qat_hw_auth_counter {
 133         __be32 counter;
 134         uint32_t reserved;
 135 };
 136 
 137 #define QAT_AUTH_COUNT_MASK 0xFFFFFFFF
 138 #define QAT_AUTH_COUNT_BITPOS 0
 139 #define ICP_QAT_HW_AUTH_COUNT_BUILD(val) \
 140         (((val) & QAT_AUTH_COUNT_MASK) << QAT_AUTH_COUNT_BITPOS)
 141 
 142 struct icp_qat_hw_auth_setup {
 143         struct icp_qat_hw_auth_config auth_config;
 144         struct icp_qat_hw_auth_counter auth_counter;
 145 };
 146 
 147 #define QAT_HW_DEFAULT_ALIGNMENT 8
 148 #define QAT_HW_ROUND_UP(val, n) (((val) + ((n) - 1)) & (~(n - 1)))
 149 #define ICP_QAT_HW_NULL_STATE1_SZ 32
 150 #define ICP_QAT_HW_MD5_STATE1_SZ 16
 151 #define ICP_QAT_HW_SHA1_STATE1_SZ 20
 152 #define ICP_QAT_HW_SHA224_STATE1_SZ 32
 153 #define ICP_QAT_HW_SHA256_STATE1_SZ 32
 154 #define ICP_QAT_HW_SHA3_256_STATE1_SZ 32
 155 #define ICP_QAT_HW_SHA384_STATE1_SZ 64
 156 #define ICP_QAT_HW_SHA512_STATE1_SZ 64
 157 #define ICP_QAT_HW_SHA3_512_STATE1_SZ 64
 158 #define ICP_QAT_HW_SHA3_224_STATE1_SZ 28
 159 #define ICP_QAT_HW_SHA3_384_STATE1_SZ 48
 160 #define ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ 16
 161 #define ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ 16
 162 #define ICP_QAT_HW_AES_F9_STATE1_SZ 32
 163 #define ICP_QAT_HW_KASUMI_F9_STATE1_SZ 16
 164 #define ICP_QAT_HW_GALOIS_128_STATE1_SZ 16
 165 #define ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ 8
 166 #define ICP_QAT_HW_ZUC_3G_EIA3_STATE1_SZ 8
 167 #define ICP_QAT_HW_NULL_STATE2_SZ 32
 168 #define ICP_QAT_HW_MD5_STATE2_SZ 16
 169 #define ICP_QAT_HW_SHA1_STATE2_SZ 20
 170 #define ICP_QAT_HW_SHA224_STATE2_SZ 32
 171 #define ICP_QAT_HW_SHA256_STATE2_SZ 32
 172 #define ICP_QAT_HW_SHA3_256_STATE2_SZ 0
 173 #define ICP_QAT_HW_SHA384_STATE2_SZ 64
 174 #define ICP_QAT_HW_SHA512_STATE2_SZ 64
 175 #define ICP_QAT_HW_SHA3_512_STATE2_SZ 0
 176 #define ICP_QAT_HW_SHA3_224_STATE2_SZ 0
 177 #define ICP_QAT_HW_SHA3_384_STATE2_SZ 0
 178 #define ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ 16
 179 #define ICP_QAT_HW_AES_CBC_MAC_KEY_SZ 16
 180 #define ICP_QAT_HW_AES_CCM_CBC_E_CTR0_SZ 16
 181 #define ICP_QAT_HW_F9_IK_SZ 16
 182 #define ICP_QAT_HW_F9_FK_SZ 16
 183 #define ICP_QAT_HW_KASUMI_F9_STATE2_SZ (ICP_QAT_HW_F9_IK_SZ + \
 184         ICP_QAT_HW_F9_FK_SZ)
 185 #define ICP_QAT_HW_AES_F9_STATE2_SZ ICP_QAT_HW_KASUMI_F9_STATE2_SZ
 186 #define ICP_QAT_HW_SNOW_3G_UIA2_STATE2_SZ 24
 187 #define ICP_QAT_HW_ZUC_3G_EIA3_STATE2_SZ 32
 188 #define ICP_QAT_HW_GALOIS_H_SZ 16
 189 #define ICP_QAT_HW_GALOIS_LEN_A_SZ 8
 190 #define ICP_QAT_HW_GALOIS_E_CTR0_SZ 16
 191 
 192 struct icp_qat_hw_auth_sha512 {
 193         struct icp_qat_hw_auth_setup inner_setup;
 194         uint8_t state1[ICP_QAT_HW_SHA512_STATE1_SZ];
 195         struct icp_qat_hw_auth_setup outer_setup;
 196         uint8_t state2[ICP_QAT_HW_SHA512_STATE2_SZ];
 197 };
 198 
 199 struct icp_qat_hw_auth_algo_blk {
 200         struct icp_qat_hw_auth_sha512 sha;
 201 };
 202 
 203 #define ICP_QAT_HW_GALOIS_LEN_A_BITPOS 0
 204 #define ICP_QAT_HW_GALOIS_LEN_A_MASK 0xFFFFFFFF
 205 
 206 enum icp_qat_hw_cipher_algo {
 207         ICP_QAT_HW_CIPHER_ALGO_NULL = 0,
 208         ICP_QAT_HW_CIPHER_ALGO_DES = 1,
 209         ICP_QAT_HW_CIPHER_ALGO_3DES = 2,
 210         ICP_QAT_HW_CIPHER_ALGO_AES128 = 3,
 211         ICP_QAT_HW_CIPHER_ALGO_AES192 = 4,
 212         ICP_QAT_HW_CIPHER_ALGO_AES256 = 5,
 213         ICP_QAT_HW_CIPHER_ALGO_ARC4 = 6,
 214         ICP_QAT_HW_CIPHER_ALGO_KASUMI = 7,
 215         ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 = 8,
 216         ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3 = 9,
 217         ICP_QAT_HW_CIPHER_DELIMITER = 10
 218 };
 219 
 220 enum icp_qat_hw_cipher_mode {
 221         ICP_QAT_HW_CIPHER_ECB_MODE = 0,
 222         ICP_QAT_HW_CIPHER_CBC_MODE = 1,
 223         ICP_QAT_HW_CIPHER_CTR_MODE = 2,
 224         ICP_QAT_HW_CIPHER_F8_MODE = 3,
 225         ICP_QAT_HW_CIPHER_XTS_MODE = 6,
 226         ICP_QAT_HW_CIPHER_MODE_DELIMITER = 7
 227 };
 228 
 229 struct icp_qat_hw_cipher_config {
 230         uint32_t val;
 231         uint32_t reserved;
 232 };
 233 
 234 enum icp_qat_hw_cipher_dir {
 235         ICP_QAT_HW_CIPHER_ENCRYPT = 0,
 236         ICP_QAT_HW_CIPHER_DECRYPT = 1,
 237 };
 238 
 239 enum icp_qat_hw_cipher_convert {
 240         ICP_QAT_HW_CIPHER_NO_CONVERT = 0,
 241         ICP_QAT_HW_CIPHER_KEY_CONVERT = 1,
 242 };
 243 
 244 #define QAT_CIPHER_MODE_BITPOS 4
 245 #define QAT_CIPHER_MODE_MASK 0xF
 246 #define QAT_CIPHER_ALGO_BITPOS 0
 247 #define QAT_CIPHER_ALGO_MASK 0xF
 248 #define QAT_CIPHER_CONVERT_BITPOS 9
 249 #define QAT_CIPHER_CONVERT_MASK 0x1
 250 #define QAT_CIPHER_DIR_BITPOS 8
 251 #define QAT_CIPHER_DIR_MASK 0x1
 252 #define QAT_CIPHER_MODE_F8_KEY_SZ_MULT 2
 253 #define QAT_CIPHER_MODE_XTS_KEY_SZ_MULT 2
 254 #define ICP_QAT_HW_CIPHER_CONFIG_BUILD(mode, algo, convert, dir) \
 255         (((mode & QAT_CIPHER_MODE_MASK) << QAT_CIPHER_MODE_BITPOS) | \
 256         ((algo & QAT_CIPHER_ALGO_MASK) << QAT_CIPHER_ALGO_BITPOS) | \
 257         ((convert & QAT_CIPHER_CONVERT_MASK) << QAT_CIPHER_CONVERT_BITPOS) | \
 258         ((dir & QAT_CIPHER_DIR_MASK) << QAT_CIPHER_DIR_BITPOS))
 259 #define ICP_QAT_HW_DES_BLK_SZ 8
 260 #define ICP_QAT_HW_3DES_BLK_SZ 8
 261 #define ICP_QAT_HW_NULL_BLK_SZ 8
 262 #define ICP_QAT_HW_AES_BLK_SZ 16
 263 #define ICP_QAT_HW_KASUMI_BLK_SZ 8
 264 #define ICP_QAT_HW_SNOW_3G_BLK_SZ 8
 265 #define ICP_QAT_HW_ZUC_3G_BLK_SZ 8
 266 #define ICP_QAT_HW_NULL_KEY_SZ 256
 267 #define ICP_QAT_HW_DES_KEY_SZ 8
 268 #define ICP_QAT_HW_3DES_KEY_SZ 24
 269 #define ICP_QAT_HW_AES_128_KEY_SZ 16
 270 #define ICP_QAT_HW_AES_192_KEY_SZ 24
 271 #define ICP_QAT_HW_AES_256_KEY_SZ 32
 272 #define ICP_QAT_HW_AES_128_F8_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \
 273         QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
 274 #define ICP_QAT_HW_AES_192_F8_KEY_SZ (ICP_QAT_HW_AES_192_KEY_SZ * \
 275         QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
 276 #define ICP_QAT_HW_AES_256_F8_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \
 277         QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
 278 #define ICP_QAT_HW_AES_128_XTS_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \
 279         QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
 280 #define ICP_QAT_HW_AES_256_XTS_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \
 281         QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
 282 #define ICP_QAT_HW_KASUMI_KEY_SZ 16
 283 #define ICP_QAT_HW_KASUMI_F8_KEY_SZ (ICP_QAT_HW_KASUMI_KEY_SZ * \
 284         QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
 285 #define ICP_QAT_HW_AES_128_XTS_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \
 286         QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
 287 #define ICP_QAT_HW_AES_256_XTS_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \
 288         QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
 289 #define ICP_QAT_HW_ARC4_KEY_SZ 256
 290 #define ICP_QAT_HW_SNOW_3G_UEA2_KEY_SZ 16
 291 #define ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ 16
 292 #define ICP_QAT_HW_ZUC_3G_EEA3_KEY_SZ 16
 293 #define ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ 16
 294 #define ICP_QAT_HW_MODE_F8_NUM_REG_TO_CLEAR 2
 295 #define INIT_SHRAM_CONSTANTS_TABLE_SZ 1024
 296 
 297 struct icp_qat_hw_cipher_aes256_f8 {
 298         struct icp_qat_hw_cipher_config cipher_config;
 299         uint8_t key[ICP_QAT_HW_AES_256_F8_KEY_SZ];
 300 };
 301 
 302 struct icp_qat_hw_cipher_algo_blk {
 303         struct icp_qat_hw_cipher_aes256_f8 aes;
 304 } __aligned(64);
 305 #endif