This source file includes following definitions.
- get_accel_mask
- get_ae_mask
- get_num_accels
- get_num_aes
- get_misc_bar_id
- get_etr_bar_id
- get_sku
- get_pf2vf_offset
- get_vintmsk_offset
- adf_vf_int_noop
- adf_vf_void_noop
- adf_init_hw_data_c3xxxiov
- adf_clean_hw_data_c3xxxiov
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47 #include <adf_accel_devices.h>
48 #include <adf_pf2vf_msg.h>
49 #include <adf_common_drv.h>
50 #include "adf_c3xxxvf_hw_data.h"
51
52 static struct adf_hw_device_class c3xxxiov_class = {
53 .name = ADF_C3XXXVF_DEVICE_NAME,
54 .type = DEV_C3XXXVF,
55 .instances = 0
56 };
57
58 static u32 get_accel_mask(u32 fuse)
59 {
60 return ADF_C3XXXIOV_ACCELERATORS_MASK;
61 }
62
63 static u32 get_ae_mask(u32 fuse)
64 {
65 return ADF_C3XXXIOV_ACCELENGINES_MASK;
66 }
67
68 static u32 get_num_accels(struct adf_hw_device_data *self)
69 {
70 return ADF_C3XXXIOV_MAX_ACCELERATORS;
71 }
72
73 static u32 get_num_aes(struct adf_hw_device_data *self)
74 {
75 return ADF_C3XXXIOV_MAX_ACCELENGINES;
76 }
77
78 static u32 get_misc_bar_id(struct adf_hw_device_data *self)
79 {
80 return ADF_C3XXXIOV_PMISC_BAR;
81 }
82
83 static u32 get_etr_bar_id(struct adf_hw_device_data *self)
84 {
85 return ADF_C3XXXIOV_ETR_BAR;
86 }
87
88 static enum dev_sku_info get_sku(struct adf_hw_device_data *self)
89 {
90 return DEV_SKU_VF;
91 }
92
93 static u32 get_pf2vf_offset(u32 i)
94 {
95 return ADF_C3XXXIOV_PF2VF_OFFSET;
96 }
97
98 static u32 get_vintmsk_offset(u32 i)
99 {
100 return ADF_C3XXXIOV_VINTMSK_OFFSET;
101 }
102
103 static int adf_vf_int_noop(struct adf_accel_dev *accel_dev)
104 {
105 return 0;
106 }
107
108 static void adf_vf_void_noop(struct adf_accel_dev *accel_dev)
109 {
110 }
111
112 void adf_init_hw_data_c3xxxiov(struct adf_hw_device_data *hw_data)
113 {
114 hw_data->dev_class = &c3xxxiov_class;
115 hw_data->num_banks = ADF_C3XXXIOV_ETR_MAX_BANKS;
116 hw_data->num_accel = ADF_C3XXXIOV_MAX_ACCELERATORS;
117 hw_data->num_logical_accel = 1;
118 hw_data->num_engines = ADF_C3XXXIOV_MAX_ACCELENGINES;
119 hw_data->tx_rx_gap = ADF_C3XXXIOV_RX_RINGS_OFFSET;
120 hw_data->tx_rings_mask = ADF_C3XXXIOV_TX_RINGS_MASK;
121 hw_data->alloc_irq = adf_vf_isr_resource_alloc;
122 hw_data->free_irq = adf_vf_isr_resource_free;
123 hw_data->enable_error_correction = adf_vf_void_noop;
124 hw_data->init_admin_comms = adf_vf_int_noop;
125 hw_data->exit_admin_comms = adf_vf_void_noop;
126 hw_data->send_admin_init = adf_vf2pf_init;
127 hw_data->init_arb = adf_vf_int_noop;
128 hw_data->exit_arb = adf_vf_void_noop;
129 hw_data->disable_iov = adf_vf2pf_shutdown;
130 hw_data->get_accel_mask = get_accel_mask;
131 hw_data->get_ae_mask = get_ae_mask;
132 hw_data->get_num_accels = get_num_accels;
133 hw_data->get_num_aes = get_num_aes;
134 hw_data->get_etr_bar_id = get_etr_bar_id;
135 hw_data->get_misc_bar_id = get_misc_bar_id;
136 hw_data->get_pf2vf_offset = get_pf2vf_offset;
137 hw_data->get_vintmsk_offset = get_vintmsk_offset;
138 hw_data->get_sku = get_sku;
139 hw_data->enable_ints = adf_vf_void_noop;
140 hw_data->enable_vf2pf_comms = adf_enable_vf2pf_comms;
141 hw_data->min_iov_compat_ver = ADF_PFVF_COMPATIBILITY_VERSION;
142 hw_data->dev_class->instances++;
143 adf_devmgr_update_class_index(hw_data);
144 }
145
146 void adf_clean_hw_data_c3xxxiov(struct adf_hw_device_data *hw_data)
147 {
148 hw_data->dev_class->instances--;
149 adf_devmgr_update_class_index(hw_data);
150 }