root/drivers/crypto/atmel-aes-regs.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __ATMEL_AES_REGS_H__
   3 #define __ATMEL_AES_REGS_H__
   4 
   5 #define AES_CR                  0x00
   6 #define AES_CR_START            (1 << 0)
   7 #define AES_CR_SWRST            (1 << 8)
   8 #define AES_CR_LOADSEED         (1 << 16)
   9 
  10 #define AES_MR                  0x04
  11 #define AES_MR_CYPHER_DEC               (0 << 0)
  12 #define AES_MR_CYPHER_ENC               (1 << 0)
  13 #define AES_MR_GTAGEN                   (1 << 1)
  14 #define AES_MR_DUALBUFF                 (1 << 3)
  15 #define AES_MR_PROCDLY_MASK             (0xF << 4)
  16 #define AES_MR_PROCDLY_OFFSET   4
  17 #define AES_MR_SMOD_MASK                (0x3 << 8)
  18 #define AES_MR_SMOD_MANUAL              (0x0 << 8)
  19 #define AES_MR_SMOD_AUTO                (0x1 << 8)
  20 #define AES_MR_SMOD_IDATAR0             (0x2 << 8)
  21 #define AES_MR_KEYSIZE_MASK             (0x3 << 10)
  22 #define AES_MR_KEYSIZE_128              (0x0 << 10)
  23 #define AES_MR_KEYSIZE_192              (0x1 << 10)
  24 #define AES_MR_KEYSIZE_256              (0x2 << 10)
  25 #define AES_MR_OPMOD_MASK               (0x7 << 12)
  26 #define AES_MR_OPMOD_ECB                (0x0 << 12)
  27 #define AES_MR_OPMOD_CBC                (0x1 << 12)
  28 #define AES_MR_OPMOD_OFB                (0x2 << 12)
  29 #define AES_MR_OPMOD_CFB                (0x3 << 12)
  30 #define AES_MR_OPMOD_CTR                (0x4 << 12)
  31 #define AES_MR_OPMOD_GCM                (0x5 << 12)
  32 #define AES_MR_OPMOD_XTS                (0x6 << 12)
  33 #define AES_MR_LOD                              (0x1 << 15)
  34 #define AES_MR_CFBS_MASK                (0x7 << 16)
  35 #define AES_MR_CFBS_128b                (0x0 << 16)
  36 #define AES_MR_CFBS_64b                 (0x1 << 16)
  37 #define AES_MR_CFBS_32b                 (0x2 << 16)
  38 #define AES_MR_CFBS_16b                 (0x3 << 16)
  39 #define AES_MR_CFBS_8b                  (0x4 << 16)
  40 #define AES_MR_CKEY_MASK                (0xF << 20)
  41 #define AES_MR_CKEY_OFFSET              20
  42 #define AES_MR_CMTYP_MASK               (0x1F << 24)
  43 #define AES_MR_CMTYP_OFFSET             24
  44 
  45 #define AES_IER         0x10
  46 #define AES_IDR         0x14
  47 #define AES_IMR         0x18
  48 #define AES_ISR         0x1C
  49 #define AES_INT_DATARDY         (1 << 0)
  50 #define AES_INT_URAD            (1 << 8)
  51 #define AES_INT_TAGRDY          (1 << 16)
  52 #define AES_ISR_URAT_MASK       (0xF << 12)
  53 #define AES_ISR_URAT_IDR_WR_PROC        (0x0 << 12)
  54 #define AES_ISR_URAT_ODR_RD_PROC        (0x1 << 12)
  55 #define AES_ISR_URAT_MR_WR_PROC         (0x2 << 12)
  56 #define AES_ISR_URAT_ODR_RD_SUBK        (0x3 << 12)
  57 #define AES_ISR_URAT_MR_WR_SUBK         (0x4 << 12)
  58 #define AES_ISR_URAT_WOR_RD                     (0x5 << 12)
  59 
  60 #define AES_KEYWR(x)    (0x20 + ((x) * 0x04))
  61 #define AES_IDATAR(x)   (0x40 + ((x) * 0x04))
  62 #define AES_ODATAR(x)   (0x50 + ((x) * 0x04))
  63 #define AES_IVR(x)              (0x60 + ((x) * 0x04))
  64 
  65 #define AES_AADLENR     0x70
  66 #define AES_CLENR       0x74
  67 #define AES_GHASHR(x)   (0x78 + ((x) * 0x04))
  68 #define AES_TAGR(x)     (0x88 + ((x) * 0x04))
  69 #define AES_CTRR        0x98
  70 #define AES_GCMHR(x)    (0x9c + ((x) * 0x04))
  71 
  72 #define AES_EMR         0xb0
  73 #define AES_EMR_APEN            BIT(0)  /* Auto Padding Enable */
  74 #define AES_EMR_APM             BIT(1)  /* Auto Padding Mode */
  75 #define AES_EMR_APM_IPSEC       0x0
  76 #define AES_EMR_APM_SSL         BIT(1)
  77 #define AES_EMR_PLIPEN          BIT(4)  /* PLIP Enable */
  78 #define AES_EMR_PLIPD           BIT(5)  /* PLIP Decipher */
  79 #define AES_EMR_PADLEN_MASK     (0xFu << 8)
  80 #define AES_EMR_PADLEN_OFFSET   8
  81 #define AES_EMR_PADLEN(padlen)  (((padlen) << AES_EMR_PADLEN_OFFSET) &\
  82                                  AES_EMR_PADLEN_MASK)
  83 #define AES_EMR_NHEAD_MASK      (0xFu << 16)
  84 #define AES_EMR_NHEAD_OFFSET    16
  85 #define AES_EMR_NHEAD(nhead)    (((nhead) << AES_EMR_NHEAD_OFFSET) &\
  86                                  AES_EMR_NHEAD_MASK)
  87 
  88 #define AES_TWR(x)      (0xc0 + ((x) * 0x04))
  89 #define AES_ALPHAR(x)   (0xd0 + ((x) * 0x04))
  90 
  91 #define AES_HW_VERSION  0xFC
  92 
  93 #endif /* __ATMEL_AES_REGS_H__ */