This source file includes following definitions.
- wait_for_tpm_stat_cond
- wait_for_tpm_stat
- wait_startup
- check_locality
- locality_inactive
- release_locality
- request_locality
- tpm_tis_status
- tpm_tis_ready
- get_burstcount
- recv_data
- tpm_tis_recv
- tpm_tis_send_data
- disable_interrupts
- tpm_tis_send_main
- tpm_tis_send
- tpm_tis_update_timeouts
- probe_itpm
- tpm_tis_req_canceled
- tis_int_handler
- tpm_tis_gen_interrupt
- tpm_tis_probe_irq_single
- tpm_tis_probe_irq
- tpm_tis_remove
- tpm_tis_clkrun_enable
- tpm_tis_core_init
- tpm_tis_reenable_interrupts
- tpm_tis_resume
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18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/pnp.h>
22 #include <linux/slab.h>
23 #include <linux/interrupt.h>
24 #include <linux/wait.h>
25 #include <linux/acpi.h>
26 #include <linux/freezer.h>
27 #include "tpm.h"
28 #include "tpm_tis_core.h"
29
30 static void tpm_tis_clkrun_enable(struct tpm_chip *chip, bool value);
31
32 static bool wait_for_tpm_stat_cond(struct tpm_chip *chip, u8 mask,
33 bool check_cancel, bool *canceled)
34 {
35 u8 status = chip->ops->status(chip);
36
37 *canceled = false;
38 if ((status & mask) == mask)
39 return true;
40 if (check_cancel && chip->ops->req_canceled(chip, status)) {
41 *canceled = true;
42 return true;
43 }
44 return false;
45 }
46
47 static int wait_for_tpm_stat(struct tpm_chip *chip, u8 mask,
48 unsigned long timeout, wait_queue_head_t *queue,
49 bool check_cancel)
50 {
51 unsigned long stop;
52 long rc;
53 u8 status;
54 bool canceled = false;
55
56
57 status = chip->ops->status(chip);
58 if ((status & mask) == mask)
59 return 0;
60
61 stop = jiffies + timeout;
62
63 if (chip->flags & TPM_CHIP_FLAG_IRQ) {
64 again:
65 timeout = stop - jiffies;
66 if ((long)timeout <= 0)
67 return -ETIME;
68 rc = wait_event_interruptible_timeout(*queue,
69 wait_for_tpm_stat_cond(chip, mask, check_cancel,
70 &canceled),
71 timeout);
72 if (rc > 0) {
73 if (canceled)
74 return -ECANCELED;
75 return 0;
76 }
77 if (rc == -ERESTARTSYS && freezing(current)) {
78 clear_thread_flag(TIF_SIGPENDING);
79 goto again;
80 }
81 } else {
82 do {
83 usleep_range(TPM_TIMEOUT_USECS_MIN,
84 TPM_TIMEOUT_USECS_MAX);
85 status = chip->ops->status(chip);
86 if ((status & mask) == mask)
87 return 0;
88 } while (time_before(jiffies, stop));
89 }
90 return -ETIME;
91 }
92
93
94
95
96
97
98 static int wait_startup(struct tpm_chip *chip, int l)
99 {
100 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
101 unsigned long stop = jiffies + chip->timeout_a;
102
103 do {
104 int rc;
105 u8 access;
106
107 rc = tpm_tis_read8(priv, TPM_ACCESS(l), &access);
108 if (rc < 0)
109 return rc;
110
111 if (access & TPM_ACCESS_VALID)
112 return 0;
113 tpm_msleep(TPM_TIMEOUT);
114 } while (time_before(jiffies, stop));
115 return -1;
116 }
117
118 static bool check_locality(struct tpm_chip *chip, int l)
119 {
120 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
121 int rc;
122 u8 access;
123
124 rc = tpm_tis_read8(priv, TPM_ACCESS(l), &access);
125 if (rc < 0)
126 return false;
127
128 if ((access & (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) ==
129 (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) {
130 priv->locality = l;
131 return true;
132 }
133
134 return false;
135 }
136
137 static bool locality_inactive(struct tpm_chip *chip, int l)
138 {
139 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
140 int rc;
141 u8 access;
142
143 rc = tpm_tis_read8(priv, TPM_ACCESS(l), &access);
144 if (rc < 0)
145 return false;
146
147 if ((access & (TPM_ACCESS_VALID | TPM_ACCESS_ACTIVE_LOCALITY))
148 == TPM_ACCESS_VALID)
149 return true;
150
151 return false;
152 }
153
154 static int release_locality(struct tpm_chip *chip, int l)
155 {
156 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
157 unsigned long stop, timeout;
158 long rc;
159
160 tpm_tis_write8(priv, TPM_ACCESS(l), TPM_ACCESS_ACTIVE_LOCALITY);
161
162 stop = jiffies + chip->timeout_a;
163
164 if (chip->flags & TPM_CHIP_FLAG_IRQ) {
165 again:
166 timeout = stop - jiffies;
167 if ((long)timeout <= 0)
168 return -1;
169
170 rc = wait_event_interruptible_timeout(priv->int_queue,
171 (locality_inactive(chip, l)),
172 timeout);
173
174 if (rc > 0)
175 return 0;
176
177 if (rc == -ERESTARTSYS && freezing(current)) {
178 clear_thread_flag(TIF_SIGPENDING);
179 goto again;
180 }
181 } else {
182 do {
183 if (locality_inactive(chip, l))
184 return 0;
185 tpm_msleep(TPM_TIMEOUT);
186 } while (time_before(jiffies, stop));
187 }
188 return -1;
189 }
190
191 static int request_locality(struct tpm_chip *chip, int l)
192 {
193 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
194 unsigned long stop, timeout;
195 long rc;
196
197 if (check_locality(chip, l))
198 return l;
199
200 rc = tpm_tis_write8(priv, TPM_ACCESS(l), TPM_ACCESS_REQUEST_USE);
201 if (rc < 0)
202 return rc;
203
204 stop = jiffies + chip->timeout_a;
205
206 if (chip->flags & TPM_CHIP_FLAG_IRQ) {
207 again:
208 timeout = stop - jiffies;
209 if ((long)timeout <= 0)
210 return -1;
211 rc = wait_event_interruptible_timeout(priv->int_queue,
212 (check_locality
213 (chip, l)),
214 timeout);
215 if (rc > 0)
216 return l;
217 if (rc == -ERESTARTSYS && freezing(current)) {
218 clear_thread_flag(TIF_SIGPENDING);
219 goto again;
220 }
221 } else {
222
223 do {
224 if (check_locality(chip, l))
225 return l;
226 tpm_msleep(TPM_TIMEOUT);
227 } while (time_before(jiffies, stop));
228 }
229 return -1;
230 }
231
232 static u8 tpm_tis_status(struct tpm_chip *chip)
233 {
234 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
235 int rc;
236 u8 status;
237
238 rc = tpm_tis_read8(priv, TPM_STS(priv->locality), &status);
239 if (rc < 0)
240 return 0;
241
242 return status;
243 }
244
245 static void tpm_tis_ready(struct tpm_chip *chip)
246 {
247 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
248
249
250 tpm_tis_write8(priv, TPM_STS(priv->locality), TPM_STS_COMMAND_READY);
251 }
252
253 static int get_burstcount(struct tpm_chip *chip)
254 {
255 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
256 unsigned long stop;
257 int burstcnt, rc;
258 u32 value;
259
260
261 if (chip->flags & TPM_CHIP_FLAG_TPM2)
262 stop = jiffies + chip->timeout_a;
263 else
264 stop = jiffies + chip->timeout_d;
265 do {
266 rc = tpm_tis_read32(priv, TPM_STS(priv->locality), &value);
267 if (rc < 0)
268 return rc;
269
270 burstcnt = (value >> 8) & 0xFFFF;
271 if (burstcnt)
272 return burstcnt;
273 usleep_range(TPM_TIMEOUT_USECS_MIN, TPM_TIMEOUT_USECS_MAX);
274 } while (time_before(jiffies, stop));
275 return -EBUSY;
276 }
277
278 static int recv_data(struct tpm_chip *chip, u8 *buf, size_t count)
279 {
280 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
281 int size = 0, burstcnt, rc;
282
283 while (size < count) {
284 rc = wait_for_tpm_stat(chip,
285 TPM_STS_DATA_AVAIL | TPM_STS_VALID,
286 chip->timeout_c,
287 &priv->read_queue, true);
288 if (rc < 0)
289 return rc;
290 burstcnt = get_burstcount(chip);
291 if (burstcnt < 0) {
292 dev_err(&chip->dev, "Unable to read burstcount\n");
293 return burstcnt;
294 }
295 burstcnt = min_t(int, burstcnt, count - size);
296
297 rc = tpm_tis_read_bytes(priv, TPM_DATA_FIFO(priv->locality),
298 burstcnt, buf + size);
299 if (rc < 0)
300 return rc;
301
302 size += burstcnt;
303 }
304 return size;
305 }
306
307 static int tpm_tis_recv(struct tpm_chip *chip, u8 *buf, size_t count)
308 {
309 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
310 int size = 0;
311 int status;
312 u32 expected;
313
314 if (count < TPM_HEADER_SIZE) {
315 size = -EIO;
316 goto out;
317 }
318
319 size = recv_data(chip, buf, TPM_HEADER_SIZE);
320
321 if (size < TPM_HEADER_SIZE) {
322 dev_err(&chip->dev, "Unable to read header\n");
323 goto out;
324 }
325
326 expected = be32_to_cpu(*(__be32 *) (buf + 2));
327 if (expected > count || expected < TPM_HEADER_SIZE) {
328 size = -EIO;
329 goto out;
330 }
331
332 size += recv_data(chip, &buf[TPM_HEADER_SIZE],
333 expected - TPM_HEADER_SIZE);
334 if (size < expected) {
335 dev_err(&chip->dev, "Unable to read remainder of result\n");
336 size = -ETIME;
337 goto out;
338 }
339
340 if (wait_for_tpm_stat(chip, TPM_STS_VALID, chip->timeout_c,
341 &priv->int_queue, false) < 0) {
342 size = -ETIME;
343 goto out;
344 }
345 status = tpm_tis_status(chip);
346 if (status & TPM_STS_DATA_AVAIL) {
347 dev_err(&chip->dev, "Error left over data\n");
348 size = -EIO;
349 goto out;
350 }
351
352 out:
353 tpm_tis_ready(chip);
354 return size;
355 }
356
357
358
359
360
361
362 static int tpm_tis_send_data(struct tpm_chip *chip, const u8 *buf, size_t len)
363 {
364 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
365 int rc, status, burstcnt;
366 size_t count = 0;
367 bool itpm = priv->flags & TPM_TIS_ITPM_WORKAROUND;
368
369 status = tpm_tis_status(chip);
370 if ((status & TPM_STS_COMMAND_READY) == 0) {
371 tpm_tis_ready(chip);
372 if (wait_for_tpm_stat
373 (chip, TPM_STS_COMMAND_READY, chip->timeout_b,
374 &priv->int_queue, false) < 0) {
375 rc = -ETIME;
376 goto out_err;
377 }
378 }
379
380 while (count < len - 1) {
381 burstcnt = get_burstcount(chip);
382 if (burstcnt < 0) {
383 dev_err(&chip->dev, "Unable to read burstcount\n");
384 rc = burstcnt;
385 goto out_err;
386 }
387 burstcnt = min_t(int, burstcnt, len - count - 1);
388 rc = tpm_tis_write_bytes(priv, TPM_DATA_FIFO(priv->locality),
389 burstcnt, buf + count);
390 if (rc < 0)
391 goto out_err;
392
393 count += burstcnt;
394
395 if (wait_for_tpm_stat(chip, TPM_STS_VALID, chip->timeout_c,
396 &priv->int_queue, false) < 0) {
397 rc = -ETIME;
398 goto out_err;
399 }
400 status = tpm_tis_status(chip);
401 if (!itpm && (status & TPM_STS_DATA_EXPECT) == 0) {
402 rc = -EIO;
403 goto out_err;
404 }
405 }
406
407
408 rc = tpm_tis_write8(priv, TPM_DATA_FIFO(priv->locality), buf[count]);
409 if (rc < 0)
410 goto out_err;
411
412 if (wait_for_tpm_stat(chip, TPM_STS_VALID, chip->timeout_c,
413 &priv->int_queue, false) < 0) {
414 rc = -ETIME;
415 goto out_err;
416 }
417 status = tpm_tis_status(chip);
418 if (!itpm && (status & TPM_STS_DATA_EXPECT) != 0) {
419 rc = -EIO;
420 goto out_err;
421 }
422
423 return 0;
424
425 out_err:
426 tpm_tis_ready(chip);
427 return rc;
428 }
429
430 static void disable_interrupts(struct tpm_chip *chip)
431 {
432 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
433 u32 intmask;
434 int rc;
435
436 if (priv->irq == 0)
437 return;
438
439 rc = tpm_tis_read32(priv, TPM_INT_ENABLE(priv->locality), &intmask);
440 if (rc < 0)
441 intmask = 0;
442
443 intmask &= ~TPM_GLOBAL_INT_ENABLE;
444 rc = tpm_tis_write32(priv, TPM_INT_ENABLE(priv->locality), intmask);
445
446 devm_free_irq(chip->dev.parent, priv->irq, chip);
447 priv->irq = 0;
448 chip->flags &= ~TPM_CHIP_FLAG_IRQ;
449 }
450
451
452
453
454
455
456 static int tpm_tis_send_main(struct tpm_chip *chip, const u8 *buf, size_t len)
457 {
458 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
459 int rc;
460 u32 ordinal;
461 unsigned long dur;
462
463 rc = tpm_tis_send_data(chip, buf, len);
464 if (rc < 0)
465 return rc;
466
467
468 rc = tpm_tis_write8(priv, TPM_STS(priv->locality), TPM_STS_GO);
469 if (rc < 0)
470 goto out_err;
471
472 if (chip->flags & TPM_CHIP_FLAG_IRQ) {
473 ordinal = be32_to_cpu(*((__be32 *) (buf + 6)));
474
475 dur = tpm_calc_ordinal_duration(chip, ordinal);
476 if (wait_for_tpm_stat
477 (chip, TPM_STS_DATA_AVAIL | TPM_STS_VALID, dur,
478 &priv->read_queue, false) < 0) {
479 rc = -ETIME;
480 goto out_err;
481 }
482 }
483 return 0;
484 out_err:
485 tpm_tis_ready(chip);
486 return rc;
487 }
488
489 static int tpm_tis_send(struct tpm_chip *chip, u8 *buf, size_t len)
490 {
491 int rc, irq;
492 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
493
494 if (!(chip->flags & TPM_CHIP_FLAG_IRQ) || priv->irq_tested)
495 return tpm_tis_send_main(chip, buf, len);
496
497
498 irq = priv->irq;
499 priv->irq = 0;
500 chip->flags &= ~TPM_CHIP_FLAG_IRQ;
501 rc = tpm_tis_send_main(chip, buf, len);
502 priv->irq = irq;
503 chip->flags |= TPM_CHIP_FLAG_IRQ;
504 if (!priv->irq_tested)
505 tpm_msleep(1);
506 if (!priv->irq_tested)
507 disable_interrupts(chip);
508 priv->irq_tested = true;
509 return rc;
510 }
511
512 struct tis_vendor_timeout_override {
513 u32 did_vid;
514 unsigned long timeout_us[4];
515 };
516
517 static const struct tis_vendor_timeout_override vendor_timeout_overrides[] = {
518
519 { 0x32041114, { (TIS_SHORT_TIMEOUT*1000), (TIS_LONG_TIMEOUT*1000),
520 (TIS_SHORT_TIMEOUT*1000), (TIS_SHORT_TIMEOUT*1000) } },
521 };
522
523 static void tpm_tis_update_timeouts(struct tpm_chip *chip,
524 unsigned long *timeout_cap)
525 {
526 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
527 int i, rc;
528 u32 did_vid;
529
530 chip->timeout_adjusted = false;
531
532 if (chip->ops->clk_enable != NULL)
533 chip->ops->clk_enable(chip, true);
534
535 rc = tpm_tis_read32(priv, TPM_DID_VID(0), &did_vid);
536 if (rc < 0) {
537 dev_warn(&chip->dev, "%s: failed to read did_vid: %d\n",
538 __func__, rc);
539 goto out;
540 }
541
542 for (i = 0; i != ARRAY_SIZE(vendor_timeout_overrides); i++) {
543 if (vendor_timeout_overrides[i].did_vid != did_vid)
544 continue;
545 memcpy(timeout_cap, vendor_timeout_overrides[i].timeout_us,
546 sizeof(vendor_timeout_overrides[i].timeout_us));
547 chip->timeout_adjusted = true;
548 }
549
550 out:
551 if (chip->ops->clk_enable != NULL)
552 chip->ops->clk_enable(chip, false);
553
554 return;
555 }
556
557
558
559
560
561
562 static int probe_itpm(struct tpm_chip *chip)
563 {
564 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
565 int rc = 0;
566 static const u8 cmd_getticks[] = {
567 0x00, 0xc1, 0x00, 0x00, 0x00, 0x0a,
568 0x00, 0x00, 0x00, 0xf1
569 };
570 size_t len = sizeof(cmd_getticks);
571 u16 vendor;
572
573 if (priv->flags & TPM_TIS_ITPM_WORKAROUND)
574 return 0;
575
576 rc = tpm_tis_read16(priv, TPM_DID_VID(0), &vendor);
577 if (rc < 0)
578 return rc;
579
580
581 if (vendor != TPM_VID_INTEL)
582 return 0;
583
584 if (request_locality(chip, 0) != 0)
585 return -EBUSY;
586
587 rc = tpm_tis_send_data(chip, cmd_getticks, len);
588 if (rc == 0)
589 goto out;
590
591 tpm_tis_ready(chip);
592
593 priv->flags |= TPM_TIS_ITPM_WORKAROUND;
594
595 rc = tpm_tis_send_data(chip, cmd_getticks, len);
596 if (rc == 0)
597 dev_info(&chip->dev, "Detected an iTPM.\n");
598 else {
599 priv->flags &= ~TPM_TIS_ITPM_WORKAROUND;
600 rc = -EFAULT;
601 }
602
603 out:
604 tpm_tis_ready(chip);
605 release_locality(chip, priv->locality);
606
607 return rc;
608 }
609
610 static bool tpm_tis_req_canceled(struct tpm_chip *chip, u8 status)
611 {
612 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
613
614 switch (priv->manufacturer_id) {
615 case TPM_VID_WINBOND:
616 return ((status == TPM_STS_VALID) ||
617 (status == (TPM_STS_VALID | TPM_STS_COMMAND_READY)));
618 case TPM_VID_STM:
619 return (status == (TPM_STS_VALID | TPM_STS_COMMAND_READY));
620 default:
621 return (status == TPM_STS_COMMAND_READY);
622 }
623 }
624
625 static irqreturn_t tis_int_handler(int dummy, void *dev_id)
626 {
627 struct tpm_chip *chip = dev_id;
628 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
629 u32 interrupt;
630 int i, rc;
631
632 rc = tpm_tis_read32(priv, TPM_INT_STATUS(priv->locality), &interrupt);
633 if (rc < 0)
634 return IRQ_NONE;
635
636 if (interrupt == 0)
637 return IRQ_NONE;
638
639 priv->irq_tested = true;
640 if (interrupt & TPM_INTF_DATA_AVAIL_INT)
641 wake_up_interruptible(&priv->read_queue);
642 if (interrupt & TPM_INTF_LOCALITY_CHANGE_INT)
643 for (i = 0; i < 5; i++)
644 if (check_locality(chip, i))
645 break;
646 if (interrupt &
647 (TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_STS_VALID_INT |
648 TPM_INTF_CMD_READY_INT))
649 wake_up_interruptible(&priv->int_queue);
650
651
652 rc = tpm_tis_write32(priv, TPM_INT_STATUS(priv->locality), interrupt);
653 if (rc < 0)
654 return IRQ_NONE;
655
656 tpm_tis_read32(priv, TPM_INT_STATUS(priv->locality), &interrupt);
657 return IRQ_HANDLED;
658 }
659
660 static int tpm_tis_gen_interrupt(struct tpm_chip *chip)
661 {
662 const char *desc = "attempting to generate an interrupt";
663 u32 cap2;
664 cap_t cap;
665
666 if (chip->flags & TPM_CHIP_FLAG_TPM2)
667 return tpm2_get_tpm_pt(chip, 0x100, &cap2, desc);
668 else
669 return tpm1_getcap(chip, TPM_CAP_PROP_TIS_TIMEOUT, &cap, desc,
670 0);
671 }
672
673
674
675
676
677 static int tpm_tis_probe_irq_single(struct tpm_chip *chip, u32 intmask,
678 int flags, int irq)
679 {
680 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
681 u8 original_int_vec;
682 int rc;
683 u32 int_status;
684
685 if (devm_request_irq(chip->dev.parent, irq, tis_int_handler, flags,
686 dev_name(&chip->dev), chip) != 0) {
687 dev_info(&chip->dev, "Unable to request irq: %d for probe\n",
688 irq);
689 return -1;
690 }
691 priv->irq = irq;
692
693 rc = tpm_tis_read8(priv, TPM_INT_VECTOR(priv->locality),
694 &original_int_vec);
695 if (rc < 0)
696 return rc;
697
698 rc = tpm_tis_write8(priv, TPM_INT_VECTOR(priv->locality), irq);
699 if (rc < 0)
700 return rc;
701
702 rc = tpm_tis_read32(priv, TPM_INT_STATUS(priv->locality), &int_status);
703 if (rc < 0)
704 return rc;
705
706
707 rc = tpm_tis_write32(priv, TPM_INT_STATUS(priv->locality), int_status);
708 if (rc < 0)
709 return rc;
710
711
712 rc = tpm_tis_write32(priv, TPM_INT_ENABLE(priv->locality),
713 intmask | TPM_GLOBAL_INT_ENABLE);
714 if (rc < 0)
715 return rc;
716
717 priv->irq_tested = false;
718
719
720
721
722 rc = tpm_tis_gen_interrupt(chip);
723 if (rc < 0)
724 return rc;
725
726
727
728
729 if (!(chip->flags & TPM_CHIP_FLAG_IRQ)) {
730 rc = tpm_tis_write8(priv, original_int_vec,
731 TPM_INT_VECTOR(priv->locality));
732 if (rc < 0)
733 return rc;
734
735 return 1;
736 }
737
738 return 0;
739 }
740
741
742
743
744
745 static void tpm_tis_probe_irq(struct tpm_chip *chip, u32 intmask)
746 {
747 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
748 u8 original_int_vec;
749 int i, rc;
750
751 rc = tpm_tis_read8(priv, TPM_INT_VECTOR(priv->locality),
752 &original_int_vec);
753 if (rc < 0)
754 return;
755
756 if (!original_int_vec) {
757 if (IS_ENABLED(CONFIG_X86))
758 for (i = 3; i <= 15; i++)
759 if (!tpm_tis_probe_irq_single(chip, intmask, 0,
760 i))
761 return;
762 } else if (!tpm_tis_probe_irq_single(chip, intmask, 0,
763 original_int_vec))
764 return;
765 }
766
767 void tpm_tis_remove(struct tpm_chip *chip)
768 {
769 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
770 u32 reg = TPM_INT_ENABLE(priv->locality);
771 u32 interrupt;
772 int rc;
773
774 tpm_tis_clkrun_enable(chip, true);
775
776 rc = tpm_tis_read32(priv, reg, &interrupt);
777 if (rc < 0)
778 interrupt = 0;
779
780 tpm_tis_write32(priv, reg, ~TPM_GLOBAL_INT_ENABLE & interrupt);
781
782 tpm_tis_clkrun_enable(chip, false);
783
784 if (priv->ilb_base_addr)
785 iounmap(priv->ilb_base_addr);
786 }
787 EXPORT_SYMBOL_GPL(tpm_tis_remove);
788
789
790
791
792
793
794
795
796
797
798 static void tpm_tis_clkrun_enable(struct tpm_chip *chip, bool value)
799 {
800 struct tpm_tis_data *data = dev_get_drvdata(&chip->dev);
801 u32 clkrun_val;
802
803 if (!IS_ENABLED(CONFIG_X86) || !is_bsw() ||
804 !data->ilb_base_addr)
805 return;
806
807 if (value) {
808 data->clkrun_enabled++;
809 if (data->clkrun_enabled > 1)
810 return;
811 clkrun_val = ioread32(data->ilb_base_addr + LPC_CNTRL_OFFSET);
812
813
814 clkrun_val &= ~LPC_CLKRUN_EN;
815 iowrite32(clkrun_val, data->ilb_base_addr + LPC_CNTRL_OFFSET);
816
817
818
819
820
821 outb(0xCC, 0x80);
822 } else {
823 data->clkrun_enabled--;
824 if (data->clkrun_enabled)
825 return;
826
827 clkrun_val = ioread32(data->ilb_base_addr + LPC_CNTRL_OFFSET);
828
829
830 clkrun_val |= LPC_CLKRUN_EN;
831 iowrite32(clkrun_val, data->ilb_base_addr + LPC_CNTRL_OFFSET);
832
833
834
835
836
837 outb(0xCC, 0x80);
838 }
839 }
840
841 static const struct tpm_class_ops tpm_tis = {
842 .flags = TPM_OPS_AUTO_STARTUP,
843 .status = tpm_tis_status,
844 .recv = tpm_tis_recv,
845 .send = tpm_tis_send,
846 .cancel = tpm_tis_ready,
847 .update_timeouts = tpm_tis_update_timeouts,
848 .req_complete_mask = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
849 .req_complete_val = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
850 .req_canceled = tpm_tis_req_canceled,
851 .request_locality = request_locality,
852 .relinquish_locality = release_locality,
853 .clk_enable = tpm_tis_clkrun_enable,
854 };
855
856 int tpm_tis_core_init(struct device *dev, struct tpm_tis_data *priv, int irq,
857 const struct tpm_tis_phy_ops *phy_ops,
858 acpi_handle acpi_dev_handle)
859 {
860 u32 vendor;
861 u32 intfcaps;
862 u32 intmask;
863 u32 clkrun_val;
864 u8 rid;
865 int rc, probe;
866 struct tpm_chip *chip;
867
868 chip = tpmm_chip_alloc(dev, &tpm_tis);
869 if (IS_ERR(chip))
870 return PTR_ERR(chip);
871
872 #ifdef CONFIG_ACPI
873 chip->acpi_dev_handle = acpi_dev_handle;
874 #endif
875
876 chip->hwrng.quality = priv->rng_quality;
877
878
879 chip->timeout_a = msecs_to_jiffies(TIS_TIMEOUT_A_MAX);
880 chip->timeout_b = msecs_to_jiffies(TIS_TIMEOUT_B_MAX);
881 chip->timeout_c = msecs_to_jiffies(TIS_TIMEOUT_C_MAX);
882 chip->timeout_d = msecs_to_jiffies(TIS_TIMEOUT_D_MAX);
883 priv->phy_ops = phy_ops;
884 dev_set_drvdata(&chip->dev, priv);
885
886 if (is_bsw()) {
887 priv->ilb_base_addr = ioremap(INTEL_LEGACY_BLK_BASE_ADDR,
888 ILB_REMAP_SIZE);
889 if (!priv->ilb_base_addr)
890 return -ENOMEM;
891
892 clkrun_val = ioread32(priv->ilb_base_addr + LPC_CNTRL_OFFSET);
893
894 if (!(clkrun_val & LPC_CLKRUN_EN)) {
895 iounmap(priv->ilb_base_addr);
896 priv->ilb_base_addr = NULL;
897 }
898 }
899
900 if (chip->ops->clk_enable != NULL)
901 chip->ops->clk_enable(chip, true);
902
903 if (wait_startup(chip, 0) != 0) {
904 rc = -ENODEV;
905 goto out_err;
906 }
907
908
909 rc = tpm_tis_read32(priv, TPM_INT_ENABLE(priv->locality), &intmask);
910 if (rc < 0)
911 goto out_err;
912
913 intmask |= TPM_INTF_CMD_READY_INT | TPM_INTF_LOCALITY_CHANGE_INT |
914 TPM_INTF_DATA_AVAIL_INT | TPM_INTF_STS_VALID_INT;
915 intmask &= ~TPM_GLOBAL_INT_ENABLE;
916 tpm_tis_write32(priv, TPM_INT_ENABLE(priv->locality), intmask);
917
918 rc = tpm_chip_start(chip);
919 if (rc)
920 goto out_err;
921 rc = tpm2_probe(chip);
922 tpm_chip_stop(chip);
923 if (rc)
924 goto out_err;
925
926 rc = tpm_tis_read32(priv, TPM_DID_VID(0), &vendor);
927 if (rc < 0)
928 goto out_err;
929
930 priv->manufacturer_id = vendor;
931
932 rc = tpm_tis_read8(priv, TPM_RID(0), &rid);
933 if (rc < 0)
934 goto out_err;
935
936 dev_info(dev, "%s TPM (device-id 0x%X, rev-id %d)\n",
937 (chip->flags & TPM_CHIP_FLAG_TPM2) ? "2.0" : "1.2",
938 vendor >> 16, rid);
939
940 probe = probe_itpm(chip);
941 if (probe < 0) {
942 rc = -ENODEV;
943 goto out_err;
944 }
945
946
947 rc = tpm_tis_read32(priv, TPM_INTF_CAPS(priv->locality), &intfcaps);
948 if (rc < 0)
949 goto out_err;
950
951 dev_dbg(dev, "TPM interface capabilities (0x%x):\n",
952 intfcaps);
953 if (intfcaps & TPM_INTF_BURST_COUNT_STATIC)
954 dev_dbg(dev, "\tBurst Count Static\n");
955 if (intfcaps & TPM_INTF_CMD_READY_INT)
956 dev_dbg(dev, "\tCommand Ready Int Support\n");
957 if (intfcaps & TPM_INTF_INT_EDGE_FALLING)
958 dev_dbg(dev, "\tInterrupt Edge Falling\n");
959 if (intfcaps & TPM_INTF_INT_EDGE_RISING)
960 dev_dbg(dev, "\tInterrupt Edge Rising\n");
961 if (intfcaps & TPM_INTF_INT_LEVEL_LOW)
962 dev_dbg(dev, "\tInterrupt Level Low\n");
963 if (intfcaps & TPM_INTF_INT_LEVEL_HIGH)
964 dev_dbg(dev, "\tInterrupt Level High\n");
965 if (intfcaps & TPM_INTF_LOCALITY_CHANGE_INT)
966 dev_dbg(dev, "\tLocality Change Int Support\n");
967 if (intfcaps & TPM_INTF_STS_VALID_INT)
968 dev_dbg(dev, "\tSts Valid Int Support\n");
969 if (intfcaps & TPM_INTF_DATA_AVAIL_INT)
970 dev_dbg(dev, "\tData Avail Int Support\n");
971
972
973 init_waitqueue_head(&priv->read_queue);
974 init_waitqueue_head(&priv->int_queue);
975 if (irq != -1) {
976
977
978
979
980 if (tpm_get_timeouts(chip)) {
981 dev_err(dev, "Could not get TPM timeouts and durations\n");
982 rc = -ENODEV;
983 goto out_err;
984 }
985
986 if (irq) {
987 tpm_tis_probe_irq_single(chip, intmask, IRQF_SHARED,
988 irq);
989 if (!(chip->flags & TPM_CHIP_FLAG_IRQ)) {
990 dev_err(&chip->dev, FW_BUG
991 "TPM interrupt not working, polling instead\n");
992
993 disable_interrupts(chip);
994 }
995 } else {
996 tpm_tis_probe_irq(chip, intmask);
997 }
998 }
999
1000 rc = tpm_chip_register(chip);
1001 if (rc)
1002 goto out_err;
1003
1004 if (chip->ops->clk_enable != NULL)
1005 chip->ops->clk_enable(chip, false);
1006
1007 return 0;
1008 out_err:
1009 if ((chip->ops != NULL) && (chip->ops->clk_enable != NULL))
1010 chip->ops->clk_enable(chip, false);
1011
1012 tpm_tis_remove(chip);
1013
1014 return rc;
1015 }
1016 EXPORT_SYMBOL_GPL(tpm_tis_core_init);
1017
1018 #ifdef CONFIG_PM_SLEEP
1019 static void tpm_tis_reenable_interrupts(struct tpm_chip *chip)
1020 {
1021 struct tpm_tis_data *priv = dev_get_drvdata(&chip->dev);
1022 u32 intmask;
1023 int rc;
1024
1025 if (chip->ops->clk_enable != NULL)
1026 chip->ops->clk_enable(chip, true);
1027
1028
1029
1030
1031 rc = tpm_tis_write8(priv, TPM_INT_VECTOR(priv->locality), priv->irq);
1032 if (rc < 0)
1033 goto out;
1034
1035 rc = tpm_tis_read32(priv, TPM_INT_ENABLE(priv->locality), &intmask);
1036 if (rc < 0)
1037 goto out;
1038
1039 intmask |= TPM_INTF_CMD_READY_INT
1040 | TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_DATA_AVAIL_INT
1041 | TPM_INTF_STS_VALID_INT | TPM_GLOBAL_INT_ENABLE;
1042
1043 tpm_tis_write32(priv, TPM_INT_ENABLE(priv->locality), intmask);
1044
1045 out:
1046 if (chip->ops->clk_enable != NULL)
1047 chip->ops->clk_enable(chip, false);
1048
1049 return;
1050 }
1051
1052 int tpm_tis_resume(struct device *dev)
1053 {
1054 struct tpm_chip *chip = dev_get_drvdata(dev);
1055 int ret;
1056
1057 if (chip->flags & TPM_CHIP_FLAG_IRQ)
1058 tpm_tis_reenable_interrupts(chip);
1059
1060 ret = tpm_pm_resume(dev);
1061 if (ret)
1062 return ret;
1063
1064
1065
1066
1067 if (!(chip->flags & TPM_CHIP_FLAG_TPM2))
1068 tpm1_do_selftest(chip);
1069
1070 return 0;
1071 }
1072 EXPORT_SYMBOL_GPL(tpm_tis_resume);
1073 #endif
1074
1075 MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
1076 MODULE_DESCRIPTION("TPM Driver");
1077 MODULE_VERSION("2.0");
1078 MODULE_LICENSE("GPL");