1
2
3
4 #ifndef _ASM_CSKY_PERF_REGS_H
5 #define _ASM_CSKY_PERF_REGS_H
6
7
8 enum perf_event_csky_regs {
9 PERF_REG_CSKY_TLS,
10 PERF_REG_CSKY_LR,
11 PERF_REG_CSKY_PC,
12 PERF_REG_CSKY_SR,
13 PERF_REG_CSKY_SP,
14 PERF_REG_CSKY_ORIG_A0,
15 PERF_REG_CSKY_A0,
16 PERF_REG_CSKY_A1,
17 PERF_REG_CSKY_A2,
18 PERF_REG_CSKY_A3,
19 PERF_REG_CSKY_REGS0,
20 PERF_REG_CSKY_REGS1,
21 PERF_REG_CSKY_REGS2,
22 PERF_REG_CSKY_REGS3,
23 PERF_REG_CSKY_REGS4,
24 PERF_REG_CSKY_REGS5,
25 PERF_REG_CSKY_REGS6,
26 PERF_REG_CSKY_REGS7,
27 PERF_REG_CSKY_REGS8,
28 PERF_REG_CSKY_REGS9,
29 #if defined(__CSKYABIV2__)
30 PERF_REG_CSKY_EXREGS0,
31 PERF_REG_CSKY_EXREGS1,
32 PERF_REG_CSKY_EXREGS2,
33 PERF_REG_CSKY_EXREGS3,
34 PERF_REG_CSKY_EXREGS4,
35 PERF_REG_CSKY_EXREGS5,
36 PERF_REG_CSKY_EXREGS6,
37 PERF_REG_CSKY_EXREGS7,
38 PERF_REG_CSKY_EXREGS8,
39 PERF_REG_CSKY_EXREGS9,
40 PERF_REG_CSKY_EXREGS10,
41 PERF_REG_CSKY_EXREGS11,
42 PERF_REG_CSKY_EXREGS12,
43 PERF_REG_CSKY_EXREGS13,
44 PERF_REG_CSKY_EXREGS14,
45 PERF_REG_CSKY_HI,
46 PERF_REG_CSKY_LO,
47 PERF_REG_CSKY_DCSR,
48 #endif
49 PERF_REG_CSKY_MAX,
50 };
51 #endif