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63 #ifndef MPI2_INIT_H
64 #define MPI2_INIT_H
65
66
67
68
69
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71
72
73
74
75
76 typedef struct _MPI2_SCSI_IO_CDB_EEDP32 {
77 U8 CDB[20];
78 __be32 PrimaryReferenceTag;
79 U16 PrimaryApplicationTag;
80 U16 PrimaryApplicationTagMask;
81 U32 TransferLength;
82 } MPI2_SCSI_IO_CDB_EEDP32, *PTR_MPI2_SCSI_IO_CDB_EEDP32,
83 Mpi2ScsiIoCdbEedp32_t, *pMpi2ScsiIoCdbEedp32_t;
84
85
86 typedef union _MPI2_SCSI_IO_CDB_UNION {
87 U8 CDB32[32];
88 MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
89 MPI2_SGE_SIMPLE_UNION SGE;
90 } MPI2_SCSI_IO_CDB_UNION, *PTR_MPI2_SCSI_IO_CDB_UNION,
91 Mpi2ScsiIoCdb_t, *pMpi2ScsiIoCdb_t;
92
93
94 typedef struct _MPI2_SCSI_IO_REQUEST {
95 U16 DevHandle;
96 U8 ChainOffset;
97 U8 Function;
98 U16 Reserved1;
99 U8 Reserved2;
100 U8 MsgFlags;
101 U8 VP_ID;
102 U8 VF_ID;
103 U16 Reserved3;
104 U32 SenseBufferLowAddress;
105 U16 SGLFlags;
106 U8 SenseBufferLength;
107 U8 Reserved4;
108 U8 SGLOffset0;
109 U8 SGLOffset1;
110 U8 SGLOffset2;
111 U8 SGLOffset3;
112 U32 SkipCount;
113 U32 DataLength;
114 U32 BidirectionalDataLength;
115 U16 IoFlags;
116 U16 EEDPFlags;
117 U32 EEDPBlockSize;
118 U32 SecondaryReferenceTag;
119 U16 SecondaryApplicationTag;
120 U16 ApplicationTagTranslationMask;
121 U8 LUN[8];
122 U32 Control;
123 MPI2_SCSI_IO_CDB_UNION CDB;
124
125 #ifdef MPI2_SCSI_IO_VENDOR_UNIQUE_REGION
126 MPI2_SCSI_IO_VENDOR_UNIQUE VendorRegion;
127 #endif
128
129 MPI2_SGE_IO_UNION SGL;
130
131 } MPI2_SCSI_IO_REQUEST, *PTR_MPI2_SCSI_IO_REQUEST,
132 Mpi2SCSIIORequest_t, *pMpi2SCSIIORequest_t;
133
134
135
136
137 #define MPI2_SCSIIO_MSGFLAGS_MASK_SENSE_ADDR (0x0C)
138 #define MPI2_SCSIIO_MSGFLAGS_SYSTEM_SENSE_ADDR (0x00)
139 #define MPI2_SCSIIO_MSGFLAGS_IOCDDR_SENSE_ADDR (0x04)
140 #define MPI2_SCSIIO_MSGFLAGS_IOCPLB_SENSE_ADDR (0x08)
141 #define MPI2_SCSIIO_MSGFLAGS_IOCPLBNTA_SENSE_ADDR (0x0C)
142 #define MPI26_SCSIIO_MSGFLAGS_IOCCTL_SENSE_ADDR (0x08)
143
144
145
146
147 #define MPI2_SCSIIO_SGLFLAGS_ADDR_MASK (0x0C)
148 #define MPI2_SCSIIO_SGLFLAGS_SYSTEM_ADDR (0x00)
149 #define MPI2_SCSIIO_SGLFLAGS_IOCDDR_ADDR (0x04)
150 #define MPI2_SCSIIO_SGLFLAGS_IOCPLB_ADDR (0x08)
151 #define MPI2_SCSIIO_SGLFLAGS_IOCPLBNTA_ADDR (0x0C)
152
153
154 #define MPI2_SCSIIO_SGLFLAGS_TYPE_MASK (0x03)
155 #define MPI2_SCSIIO_SGLFLAGS_TYPE_MPI (0x00)
156 #define MPI2_SCSIIO_SGLFLAGS_TYPE_IEEE32 (0x01)
157 #define MPI2_SCSIIO_SGLFLAGS_TYPE_IEEE64 (0x02)
158
159
160 #define MPI2_SCSIIO_SGLFLAGS_SGL3_SHIFT (12)
161 #define MPI2_SCSIIO_SGLFLAGS_SGL2_SHIFT (8)
162 #define MPI2_SCSIIO_SGLFLAGS_SGL1_SHIFT (4)
163 #define MPI2_SCSIIO_SGLFLAGS_SGL0_SHIFT (0)
164
165
166 #define MPI2_SCSIIO_NUM_SGLOFFSETS (4)
167
168
169
170
171 #define MPI2_SCSIIO_CDB_ADDR_MASK (0x6000)
172 #define MPI2_SCSIIO_CDB_ADDR_SYSTEM (0x0000)
173 #define MPI2_SCSIIO_CDB_ADDR_IOCDDR (0x2000)
174 #define MPI2_SCSIIO_CDB_ADDR_IOCPLB (0x4000)
175 #define MPI2_SCSIIO_CDB_ADDR_IOCPLBNTA (0x6000)
176
177 #define MPI2_SCSIIO_IOFLAGS_LARGE_CDB (0x1000)
178 #define MPI2_SCSIIO_IOFLAGS_BIDIRECTIONAL (0x0800)
179 #define MPI2_SCSIIO_IOFLAGS_MULTICAST (0x0400)
180 #define MPI2_SCSIIO_IOFLAGS_CMD_DETERMINES_DATA_DIR (0x0200)
181 #define MPI2_SCSIIO_IOFLAGS_CDBLENGTH_MASK (0x01FF)
182
183
184
185 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000)
186 #define MPI2_SCSIIO_EEDPFLAGS_INC_SEC_REFTAG (0x4000)
187 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_APPTAG (0x2000)
188 #define MPI2_SCSIIO_EEDPFLAGS_INC_SEC_APPTAG (0x1000)
189
190 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400)
191 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200)
192 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100)
193
194 #define MPI2_SCSIIO_EEDPFLAGS_PASSTHRU_REFTAG (0x0008)
195
196 #define MPI2_SCSIIO_EEDPFLAGS_MASK_OP (0x0007)
197 #define MPI2_SCSIIO_EEDPFLAGS_NOOP_OP (0x0000)
198 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_OP (0x0001)
199 #define MPI2_SCSIIO_EEDPFLAGS_STRIP_OP (0x0002)
200 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003)
201 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004)
202 #define MPI2_SCSIIO_EEDPFLAGS_REPLACE_OP (0x0006)
203 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REGEN_OP (0x0007)
204
205
206
207
208 #define MPI2_SCSIIO_CONTROL_ADDCDBLEN_MASK (0xFC000000)
209 #define MPI2_SCSIIO_CONTROL_ADDCDBLEN_SHIFT (26)
210
211 #define MPI2_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000)
212 #define MPI2_SCSIIO_CONTROL_SHIFT_DATADIRECTION (24)
213 #define MPI2_SCSIIO_CONTROL_NODATATRANSFER (0x00000000)
214 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000)
215 #define MPI2_SCSIIO_CONTROL_READ (0x02000000)
216 #define MPI2_SCSIIO_CONTROL_BIDIRECTIONAL (0x03000000)
217
218 #define MPI2_SCSIIO_CONTROL_TASKPRI_MASK (0x00007800)
219 #define MPI2_SCSIIO_CONTROL_TASKPRI_SHIFT (11)
220
221 #define MPI2_SCSIIO_CONTROL_CMDPRI_MASK (0x00007800)
222 #define MPI2_SCSIIO_CONTROL_CMDPRI_SHIFT (11)
223
224 #define MPI2_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700)
225 #define MPI2_SCSIIO_CONTROL_SIMPLEQ (0x00000000)
226 #define MPI2_SCSIIO_CONTROL_HEADOFQ (0x00000100)
227 #define MPI2_SCSIIO_CONTROL_ORDEREDQ (0x00000200)
228 #define MPI2_SCSIIO_CONTROL_ACAQ (0x00000400)
229
230 #define MPI2_SCSIIO_CONTROL_TLR_MASK (0x000000C0)
231 #define MPI2_SCSIIO_CONTROL_NO_TLR (0x00000000)
232 #define MPI2_SCSIIO_CONTROL_TLR_ON (0x00000040)
233 #define MPI2_SCSIIO_CONTROL_TLR_OFF (0x00000080)
234
235
236 typedef union _MPI25_SCSI_IO_CDB_UNION {
237 U8 CDB32[32];
238 MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
239 MPI2_IEEE_SGE_SIMPLE64 SGE;
240 } MPI25_SCSI_IO_CDB_UNION, *PTR_MPI25_SCSI_IO_CDB_UNION,
241 Mpi25ScsiIoCdb_t, *pMpi25ScsiIoCdb_t;
242
243
244 typedef struct _MPI25_SCSI_IO_REQUEST {
245 U16 DevHandle;
246 U8 ChainOffset;
247 U8 Function;
248 U16 Reserved1;
249 U8 Reserved2;
250 U8 MsgFlags;
251 U8 VP_ID;
252 U8 VF_ID;
253 U16 Reserved3;
254 U32 SenseBufferLowAddress;
255 U8 DMAFlags;
256 U8 Reserved5;
257 U8 SenseBufferLength;
258 U8 Reserved4;
259 U8 SGLOffset0;
260 U8 SGLOffset1;
261 U8 SGLOffset2;
262 U8 SGLOffset3;
263 U32 SkipCount;
264 U32 DataLength;
265 U32 BidirectionalDataLength;
266 U16 IoFlags;
267 U16 EEDPFlags;
268 U16 EEDPBlockSize;
269 U16 Reserved6;
270 U32 SecondaryReferenceTag;
271 U16 SecondaryApplicationTag;
272 U16 ApplicationTagTranslationMask;
273 U8 LUN[8];
274 U32 Control;
275 MPI25_SCSI_IO_CDB_UNION CDB;
276
277 #ifdef MPI25_SCSI_IO_VENDOR_UNIQUE_REGION
278 MPI25_SCSI_IO_VENDOR_UNIQUE VendorRegion;
279 #endif
280
281 MPI25_SGE_IO_UNION SGL;
282
283 } MPI25_SCSI_IO_REQUEST, *PTR_MPI25_SCSI_IO_REQUEST,
284 Mpi25SCSIIORequest_t, *pMpi25SCSIIORequest_t;
285
286
287
288
289
290
291
292
293
294
295 #define MPI25_SCSIIO_DMAFLAGS_OP_MASK (0x0F)
296 #define MPI25_SCSIIO_DMAFLAGS_OP_D_D_D_D (0x00)
297 #define MPI25_SCSIIO_DMAFLAGS_OP_D_D_D_C (0x01)
298 #define MPI25_SCSIIO_DMAFLAGS_OP_D_D_D_I (0x02)
299 #define MPI25_SCSIIO_DMAFLAGS_OP_D_D_C_C (0x03)
300 #define MPI25_SCSIIO_DMAFLAGS_OP_D_D_C_I (0x04)
301 #define MPI25_SCSIIO_DMAFLAGS_OP_D_D_I_I (0x05)
302 #define MPI25_SCSIIO_DMAFLAGS_OP_D_C_C_C (0x06)
303 #define MPI25_SCSIIO_DMAFLAGS_OP_D_C_C_I (0x07)
304 #define MPI25_SCSIIO_DMAFLAGS_OP_D_C_I_I (0x08)
305 #define MPI25_SCSIIO_DMAFLAGS_OP_D_I_I_I (0x09)
306 #define MPI25_SCSIIO_DMAFLAGS_OP_D_H_D_D (0x0A)
307 #define MPI25_SCSIIO_DMAFLAGS_OP_D_H_D_C (0x0B)
308 #define MPI25_SCSIIO_DMAFLAGS_OP_D_H_D_I (0x0C)
309 #define MPI25_SCSIIO_DMAFLAGS_OP_D_H_C_C (0x0D)
310 #define MPI25_SCSIIO_DMAFLAGS_OP_D_H_C_I (0x0E)
311 #define MPI25_SCSIIO_DMAFLAGS_OP_D_H_I_I (0x0F)
312
313
314 #define MPI25_SCSIIO_NUM_SGLOFFSETS (4)
315
316
317 #define MPI25_SCSIIO_IOFLAGS_IO_PATH_MASK (0xC000)
318 #define MPI25_SCSIIO_IOFLAGS_NORMAL_PATH (0x0000)
319 #define MPI25_SCSIIO_IOFLAGS_FAST_PATH (0x4000)
320
321 #define MPI26_SCSIIO_IOFLAGS_ESCAPE_PASSTHROUGH (0x2000)
322 #define MPI25_SCSIIO_IOFLAGS_LARGE_CDB (0x1000)
323 #define MPI25_SCSIIO_IOFLAGS_BIDIRECTIONAL (0x0800)
324 #define MPI26_SCSIIO_IOFLAGS_PORT_REQUEST (0x0400)
325 #define MPI25_SCSIIO_IOFLAGS_CDBLENGTH_MASK (0x01FF)
326
327
328
329 #define MPI25_SCSIIO_EEDPFLAGS_ESCAPE_MODE_MASK (0x00C0)
330 #define MPI25_SCSIIO_EEDPFLAGS_COMPATIBLE_MODE (0x0000)
331 #define MPI25_SCSIIO_EEDPFLAGS_DO_NOT_DISABLE_MODE (0x0040)
332 #define MPI25_SCSIIO_EEDPFLAGS_APPTAG_DISABLE_MODE (0x0080)
333 #define MPI25_SCSIIO_EEDPFLAGS_APPTAG_REFTAG_DISABLE_MODE (0x00C0)
334
335 #define MPI25_SCSIIO_EEDPFLAGS_HOST_GUARD_METHOD_MASK (0x0030)
336 #define MPI25_SCSIIO_EEDPFLAGS_T10_CRC_HOST_GUARD (0x0000)
337 #define MPI25_SCSIIO_EEDPFLAGS_IP_CHKSUM_HOST_GUARD (0x0010)
338
339
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342
343
344
345
346
347
348 typedef struct _MPI2_SCSI_IO_REPLY {
349 U16 DevHandle;
350 U8 MsgLength;
351 U8 Function;
352 U16 Reserved1;
353 U8 Reserved2;
354 U8 MsgFlags;
355 U8 VP_ID;
356 U8 VF_ID;
357 U16 Reserved3;
358 U8 SCSIStatus;
359 U8 SCSIState;
360 U16 IOCStatus;
361 U32 IOCLogInfo;
362 U32 TransferCount;
363 U32 SenseCount;
364 U32 ResponseInfo;
365 U16 TaskTag;
366 U16 SCSIStatusQualifier;
367 U32 BidirectionalTransferCount;
368
369 U32 EEDPErrorOffset;
370
371 U16 EEDPObservedAppTag;
372
373 U16 EEDPObservedGuard;
374
375 U32 EEDPObservedRefTag;
376 } MPI2_SCSI_IO_REPLY, *PTR_MPI2_SCSI_IO_REPLY,
377 Mpi2SCSIIOReply_t, *pMpi2SCSIIOReply_t;
378
379
380 #define MPI26_SCSIIO_REPLY_MSGFLAGS_REFTAG_OBSERVED_VALID (0x01)
381 #define MPI26_SCSIIO_REPLY_MSGFLAGS_GUARD_OBSERVED_VALID (0x02)
382 #define MPI26_SCSIIO_REPLY_MSGFLAGS_APPTAG_OBSERVED_VALID (0x04)
383
384
385
386 #define MPI2_SCSI_STATUS_GOOD (0x00)
387 #define MPI2_SCSI_STATUS_CHECK_CONDITION (0x02)
388 #define MPI2_SCSI_STATUS_CONDITION_MET (0x04)
389 #define MPI2_SCSI_STATUS_BUSY (0x08)
390 #define MPI2_SCSI_STATUS_INTERMEDIATE (0x10)
391 #define MPI2_SCSI_STATUS_INTERMEDIATE_CONDMET (0x14)
392 #define MPI2_SCSI_STATUS_RESERVATION_CONFLICT (0x18)
393 #define MPI2_SCSI_STATUS_COMMAND_TERMINATED (0x22)
394 #define MPI2_SCSI_STATUS_TASK_SET_FULL (0x28)
395 #define MPI2_SCSI_STATUS_ACA_ACTIVE (0x30)
396 #define MPI2_SCSI_STATUS_TASK_ABORTED (0x40)
397
398
399
400 #define MPI2_SCSI_STATE_RESPONSE_INFO_VALID (0x10)
401 #define MPI2_SCSI_STATE_TERMINATED (0x08)
402 #define MPI2_SCSI_STATE_NO_SCSI_STATUS (0x04)
403 #define MPI2_SCSI_STATE_AUTOSENSE_FAILED (0x02)
404 #define MPI2_SCSI_STATE_AUTOSENSE_VALID (0x01)
405
406
407
408 #define MPI2_SCSI_RI_MASK_REASONCODE (0x000000FF)
409 #define MPI2_SCSI_RI_SHIFT_REASONCODE (0)
410
411 #define MPI2_SCSI_TASKTAG_UNKNOWN (0xFFFF)
412
413
414
415
416
417
418 typedef struct _MPI2_SCSI_TASK_MANAGE_REQUEST {
419 U16 DevHandle;
420 U8 ChainOffset;
421 U8 Function;
422 U8 Reserved1;
423 U8 TaskType;
424 U8 Reserved2;
425 U8 MsgFlags;
426 U8 VP_ID;
427 U8 VF_ID;
428 U16 Reserved3;
429 U8 LUN[8];
430 U32 Reserved4[7];
431 U16 TaskMID;
432 U16 Reserved5;
433 } MPI2_SCSI_TASK_MANAGE_REQUEST,
434 *PTR_MPI2_SCSI_TASK_MANAGE_REQUEST,
435 Mpi2SCSITaskManagementRequest_t,
436 *pMpi2SCSITaskManagementRequest_t;
437
438
439
440 #define MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01)
441 #define MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET (0x02)
442 #define MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03)
443 #define MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05)
444 #define MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06)
445 #define MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07)
446 #define MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA (0x08)
447 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET (0x09)
448 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_ASYNC_EVENT (0x0A)
449
450
451 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_UNIT_ATTENTION \
452 (MPI2_SCSITASKMGMT_TASKTYPE_QRY_ASYNC_EVENT)
453
454
455
456 #define MPI2_SCSITASKMGMT_MSGFLAGS_MASK_TARGET_RESET (0x18)
457 #define MPI26_SCSITASKMGMT_MSGFLAGS_HOT_RESET_PCIE (0x00)
458 #define MPI2_SCSITASKMGMT_MSGFLAGS_LINK_RESET (0x00)
459 #define MPI2_SCSITASKMGMT_MSGFLAGS_NEXUS_RESET_SRST (0x08)
460 #define MPI2_SCSITASKMGMT_MSGFLAGS_SAS_HARD_LINK_RESET (0x10)
461
462 #define MPI2_SCSITASKMGMT_MSGFLAGS_DO_NOT_SEND_TASK_IU (0x01)
463 #define MPI26_SCSITASKMGMT_MSGFLAGS_PROTOCOL_LVL_RST_PCIE (0x18)
464
465
466 typedef struct _MPI2_SCSI_TASK_MANAGE_REPLY {
467 U16 DevHandle;
468 U8 MsgLength;
469 U8 Function;
470 U8 ResponseCode;
471 U8 TaskType;
472 U8 Reserved1;
473 U8 MsgFlags;
474 U8 VP_ID;
475 U8 VF_ID;
476 U16 Reserved2;
477 U16 Reserved3;
478 U16 IOCStatus;
479 U32 IOCLogInfo;
480 U32 TerminationCount;
481 U32 ResponseInfo;
482 } MPI2_SCSI_TASK_MANAGE_REPLY,
483 *PTR_MPI2_SCSI_TASK_MANAGE_REPLY,
484 Mpi2SCSITaskManagementReply_t, *pMpi2SCSIManagementReply_t;
485
486
487
488 #define MPI2_SCSITASKMGMT_RSP_TM_COMPLETE (0x00)
489 #define MPI2_SCSITASKMGMT_RSP_INVALID_FRAME (0x02)
490 #define MPI2_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED (0x04)
491 #define MPI2_SCSITASKMGMT_RSP_TM_FAILED (0x05)
492 #define MPI2_SCSITASKMGMT_RSP_TM_SUCCEEDED (0x08)
493 #define MPI2_SCSITASKMGMT_RSP_TM_INVALID_LUN (0x09)
494 #define MPI2_SCSITASKMGMT_RSP_TM_OVERLAPPED_TAG (0x0A)
495 #define MPI2_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC (0x80)
496
497
498
499 #define MPI2_SCSITASKMGMT_RI_MASK_REASONCODE (0x000000FF)
500 #define MPI2_SCSITASKMGMT_RI_SHIFT_REASONCODE (0)
501 #define MPI2_SCSITASKMGMT_RI_MASK_ARI2 (0x0000FF00)
502 #define MPI2_SCSITASKMGMT_RI_SHIFT_ARI2 (8)
503 #define MPI2_SCSITASKMGMT_RI_MASK_ARI1 (0x00FF0000)
504 #define MPI2_SCSITASKMGMT_RI_SHIFT_ARI1 (16)
505 #define MPI2_SCSITASKMGMT_RI_MASK_ARI0 (0xFF000000)
506 #define MPI2_SCSITASKMGMT_RI_SHIFT_ARI0 (24)
507
508
509
510
511
512
513 typedef struct _MPI2_SEP_REQUEST {
514 U16 DevHandle;
515 U8 ChainOffset;
516 U8 Function;
517 U8 Action;
518 U8 Flags;
519 U8 Reserved1;
520 U8 MsgFlags;
521 U8 VP_ID;
522 U8 VF_ID;
523 U16 Reserved2;
524 U32 SlotStatus;
525 U32 Reserved3;
526 U32 Reserved4;
527 U32 Reserved5;
528 U16 Slot;
529 U16 EnclosureHandle;
530 } MPI2_SEP_REQUEST, *PTR_MPI2_SEP_REQUEST,
531 Mpi2SepRequest_t, *pMpi2SepRequest_t;
532
533
534 #define MPI2_SEP_REQ_ACTION_WRITE_STATUS (0x00)
535 #define MPI2_SEP_REQ_ACTION_READ_STATUS (0x01)
536
537
538 #define MPI2_SEP_REQ_FLAGS_DEVHANDLE_ADDRESS (0x00)
539 #define MPI2_SEP_REQ_FLAGS_ENCLOSURE_SLOT_ADDRESS (0x01)
540
541
542 #define MPI2_SEP_REQ_SLOTSTATUS_DEV_OFF (0x00080000)
543 #define MPI2_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE (0x00040000)
544 #define MPI2_SEP_REQ_SLOTSTATUS_IDENTIFY_REQUEST (0x00020000)
545 #define MPI2_SEP_REQ_SLOTSTATUS_REBUILD_STOPPED (0x00000200)
546 #define MPI2_SEP_REQ_SLOTSTATUS_HOT_SPARE (0x00000100)
547 #define MPI2_SEP_REQ_SLOTSTATUS_UNCONFIGURED (0x00000080)
548 #define MPI2_SEP_REQ_SLOTSTATUS_PREDICTED_FAULT (0x00000040)
549 #define MPI2_SEP_REQ_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000010)
550 #define MPI2_SEP_REQ_SLOTSTATUS_IN_FAILED_ARRAY (0x00000008)
551 #define MPI2_SEP_REQ_SLOTSTATUS_DEV_REBUILDING (0x00000004)
552 #define MPI2_SEP_REQ_SLOTSTATUS_DEV_FAULTY (0x00000002)
553 #define MPI2_SEP_REQ_SLOTSTATUS_NO_ERROR (0x00000001)
554
555
556 typedef struct _MPI2_SEP_REPLY {
557 U16 DevHandle;
558 U8 MsgLength;
559 U8 Function;
560 U8 Action;
561 U8 Flags;
562 U8 Reserved1;
563 U8 MsgFlags;
564 U8 VP_ID;
565 U8 VF_ID;
566 U16 Reserved2;
567 U16 Reserved3;
568 U16 IOCStatus;
569 U32 IOCLogInfo;
570 U32 SlotStatus;
571 U32 Reserved4;
572 U16 Slot;
573 U16 EnclosureHandle;
574 } MPI2_SEP_REPLY, *PTR_MPI2_SEP_REPLY,
575 Mpi2SepReply_t, *pMpi2SepReply_t;
576
577
578 #define MPI2_SEP_REPLY_SLOTSTATUS_DEV_OFF (0x00080000)
579 #define MPI2_SEP_REPLY_SLOTSTATUS_REMOVE_READY (0x00040000)
580 #define MPI2_SEP_REPLY_SLOTSTATUS_IDENTIFY_REQUEST (0x00020000)
581 #define MPI2_SEP_REPLY_SLOTSTATUS_REBUILD_STOPPED (0x00000200)
582 #define MPI2_SEP_REPLY_SLOTSTATUS_HOT_SPARE (0x00000100)
583 #define MPI2_SEP_REPLY_SLOTSTATUS_UNCONFIGURED (0x00000080)
584 #define MPI2_SEP_REPLY_SLOTSTATUS_PREDICTED_FAULT (0x00000040)
585 #define MPI2_SEP_REPLY_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000010)
586 #define MPI2_SEP_REPLY_SLOTSTATUS_IN_FAILED_ARRAY (0x00000008)
587 #define MPI2_SEP_REPLY_SLOTSTATUS_DEV_REBUILDING (0x00000004)
588 #define MPI2_SEP_REPLY_SLOTSTATUS_DEV_FAULTY (0x00000002)
589 #define MPI2_SEP_REPLY_SLOTSTATUS_NO_ERROR (0x00000001)
590
591 #endif