root/drivers/scsi/mpt3sas/mpi/mpi2.h

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   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright 2000-2020 Broadcom Inc. All rights reserved.
   4  *
   5  *
   6  *          Name:  mpi2.h
   7  *         Title:  MPI Message independent structures and definitions
   8  *                 including System Interface Register Set and
   9  *                 scatter/gather formats.
  10  * Creation Date:  June 21, 2006
  11  *
  12  *  mpi2.h Version:  02.00.54
  13  *
  14  * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
  15  *       prefix are for use only on MPI v2.5 products, and must not be used
  16  *       with MPI v2.0 products. Unless otherwise noted, names beginning with
  17  *       MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
  18  *
  19  * Version History
  20  * ---------------
  21  *
  22  * Date      Version   Description
  23  * --------  --------  ------------------------------------------------------
  24  * 04-30-07  02.00.00  Corresponds to Fusion-MPT MPI Specification Rev A.
  25  * 06-04-07  02.00.01  Bumped MPI2_HEADER_VERSION_UNIT.
  26  * 06-26-07  02.00.02  Bumped MPI2_HEADER_VERSION_UNIT.
  27  * 08-31-07  02.00.03  Bumped MPI2_HEADER_VERSION_UNIT.
  28  *                     Moved ReplyPostHostIndex register to offset 0x6C of the
  29  *                     MPI2_SYSTEM_INTERFACE_REGS and modified the define for
  30  *                     MPI2_REPLY_POST_HOST_INDEX_OFFSET.
  31  *                     Added union of request descriptors.
  32  *                     Added union of reply descriptors.
  33  * 10-31-07  02.00.04  Bumped MPI2_HEADER_VERSION_UNIT.
  34  *                     Added define for MPI2_VERSION_02_00.
  35  *                     Fixed the size of the FunctionDependent5 field in the
  36  *                     MPI2_DEFAULT_REPLY structure.
  37  * 12-18-07  02.00.05  Bumped MPI2_HEADER_VERSION_UNIT.
  38  *                     Removed the MPI-defined Fault Codes and extended the
  39  *                     product specific codes up to 0xEFFF.
  40  *                     Added a sixth key value for the WriteSequence register
  41  *                     and changed the flush value to 0x0.
  42  *                     Added message function codes for Diagnostic Buffer Post
  43  *                     and Diagnsotic Release.
  44  *                     New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
  45  *                     Moved MPI2_VERSION_UNION from mpi2_ioc.h.
  46  * 02-29-08  02.00.06  Bumped MPI2_HEADER_VERSION_UNIT.
  47  * 03-03-08  02.00.07  Bumped MPI2_HEADER_VERSION_UNIT.
  48  * 05-21-08  02.00.08  Bumped MPI2_HEADER_VERSION_UNIT.
  49  *                     Added #defines for marking a reply descriptor as unused.
  50  * 06-27-08  02.00.09  Bumped MPI2_HEADER_VERSION_UNIT.
  51  * 10-02-08  02.00.10  Bumped MPI2_HEADER_VERSION_UNIT.
  52  *                     Moved LUN field defines from mpi2_init.h.
  53  * 01-19-09  02.00.11  Bumped MPI2_HEADER_VERSION_UNIT.
  54  * 05-06-09  02.00.12  Bumped MPI2_HEADER_VERSION_UNIT.
  55  *                     In all request and reply descriptors, replaced VF_ID
  56  *                     field with MSIxIndex field.
  57  *                     Removed DevHandle field from
  58  *                     MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
  59  *                     bytes reserved.
  60  *                     Added RAID Accelerator functionality.
  61  * 07-30-09  02.00.13  Bumped MPI2_HEADER_VERSION_UNIT.
  62  * 10-28-09  02.00.14  Bumped MPI2_HEADER_VERSION_UNIT.
  63  *                     Added MSI-x index mask and shift for Reply Post Host
  64  *                     Index register.
  65  *                     Added function code for Host Based Discovery Action.
  66  * 02-10-10  02.00.15  Bumped MPI2_HEADER_VERSION_UNIT.
  67  *                     Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL.
  68  *                     Added defines for product-specific range of message
  69  *                     function codes, 0xF0 to 0xFF.
  70  * 05-12-10  02.00.16  Bumped MPI2_HEADER_VERSION_UNIT.
  71  *                     Added alternative defines for the SGE Direction bit.
  72  * 08-11-10  02.00.17  Bumped MPI2_HEADER_VERSION_UNIT.
  73  * 11-10-10  02.00.18  Bumped MPI2_HEADER_VERSION_UNIT.
  74  *                     Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define.
  75  * 02-23-11  02.00.19  Bumped MPI2_HEADER_VERSION_UNIT.
  76  *                     Added MPI2_FUNCTION_SEND_HOST_MESSAGE.
  77  * 03-09-11  02.00.20  Bumped MPI2_HEADER_VERSION_UNIT.
  78  * 05-25-11  02.00.21  Bumped MPI2_HEADER_VERSION_UNIT.
  79  * 08-24-11  02.00.22  Bumped MPI2_HEADER_VERSION_UNIT.
  80  * 11-18-11  02.00.23  Bumped MPI2_HEADER_VERSION_UNIT.
  81  *                     Incorporating additions for MPI v2.5.
  82  * 02-06-12  02.00.24  Bumped MPI2_HEADER_VERSION_UNIT.
  83  * 03-29-12  02.00.25  Bumped MPI2_HEADER_VERSION_UNIT.
  84  *                     Added Hard Reset delay timings.
  85  * 07-10-12  02.00.26  Bumped MPI2_HEADER_VERSION_UNIT.
  86  * 07-26-12  02.00.27  Bumped MPI2_HEADER_VERSION_UNIT.
  87  * 11-27-12  02.00.28  Bumped MPI2_HEADER_VERSION_UNIT.
  88  * 12-20-12  02.00.29  Bumped MPI2_HEADER_VERSION_UNIT.
  89  *                     Added MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET.
  90  * 04-09-13  02.00.30  Bumped MPI2_HEADER_VERSION_UNIT.
  91  * 04-17-13  02.00.31  Bumped MPI2_HEADER_VERSION_UNIT.
  92  * 08-19-13  02.00.32  Bumped MPI2_HEADER_VERSION_UNIT.
  93  * 12-05-13  02.00.33  Bumped MPI2_HEADER_VERSION_UNIT.
  94  * 01-08-14  02.00.34  Bumped MPI2_HEADER_VERSION_UNIT
  95  * 06-13-14  02.00.35  Bumped MPI2_HEADER_VERSION_UNIT.
  96  * 11-18-14  02.00.36  Updated copyright information.
  97  *                     Bumped MPI2_HEADER_VERSION_UNIT.
  98  * 03-16-15  02.00.37  Bumped MPI2_HEADER_VERSION_UNIT.
  99  *                     Added Scratchpad registers to
 100  *                     MPI2_SYSTEM_INTERFACE_REGS.
 101  *                     Added MPI2_DIAG_SBR_RELOAD.
 102  * 03-19-15  02.00.38  Bumped MPI2_HEADER_VERSION_UNIT.
 103  * 05-25-15  02.00.39  Bumped MPI2_HEADER_VERSION_UNIT.
 104  * 08-25-15  02.00.40  Bumped MPI2_HEADER_VERSION_UNIT.
 105  * 12-15-15  02.00.41  Bumped MPI_HEADER_VERSION_UNIT
 106  * 01-01-16  02.00.42  Bumped MPI_HEADER_VERSION_UNIT
 107  * 04-05-16  02.00.43  Modified  MPI26_DIAG_BOOT_DEVICE_SELECT defines
 108  *                     to be unique within first 32 characters.
 109  *                     Removed AHCI support.
 110  *                     Removed SOP support.
 111  *                     Bumped MPI2_HEADER_VERSION_UNIT.
 112  * 04-10-16  02.00.44  Bumped MPI2_HEADER_VERSION_UNIT.
 113  * 07-06-16  02.00.45  Bumped MPI2_HEADER_VERSION_UNIT.
 114  * 09-02-16  02.00.46  Bumped MPI2_HEADER_VERSION_UNIT.
 115  * 11-23-16  02.00.47  Bumped MPI2_HEADER_VERSION_UNIT.
 116  * 02-03-17  02.00.48  Bumped MPI2_HEADER_VERSION_UNIT.
 117  * 06-13-17  02.00.49  Bumped MPI2_HEADER_VERSION_UNIT.
 118  * 09-29-17  02.00.50  Bumped MPI2_HEADER_VERSION_UNIT.
 119  * 07-22-18  02.00.51  Added SECURE_BOOT define.
 120  *                     Bumped MPI2_HEADER_VERSION_UNIT
 121  * 08-15-18  02.00.52  Bumped MPI2_HEADER_VERSION_UNIT.
 122  * 08-28-18  02.00.53  Bumped MPI2_HEADER_VERSION_UNIT.
 123  *                     Added MPI2_IOCSTATUS_FAILURE
 124  * 12-17-18  02.00.54  Bumped MPI2_HEADER_VERSION_UNIT
 125  *  --------------------------------------------------------------------------
 126  */
 127 
 128 #ifndef MPI2_H
 129 #define MPI2_H
 130 
 131 /*****************************************************************************
 132 *
 133 *       MPI Version Definitions
 134 *
 135 *****************************************************************************/
 136 
 137 #define MPI2_VERSION_MAJOR_MASK             (0xFF00)
 138 #define MPI2_VERSION_MAJOR_SHIFT            (8)
 139 #define MPI2_VERSION_MINOR_MASK             (0x00FF)
 140 #define MPI2_VERSION_MINOR_SHIFT            (0)
 141 
 142 /*major version for all MPI v2.x */
 143 #define MPI2_VERSION_MAJOR                  (0x02)
 144 
 145 /*minor version for MPI v2.0 compatible products */
 146 #define MPI2_VERSION_MINOR                  (0x00)
 147 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
 148                                         MPI2_VERSION_MINOR)
 149 #define MPI2_VERSION_02_00                  (0x0200)
 150 
 151 /*minor version for MPI v2.5 compatible products */
 152 #define MPI25_VERSION_MINOR                 (0x05)
 153 #define MPI25_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
 154                                         MPI25_VERSION_MINOR)
 155 #define MPI2_VERSION_02_05                  (0x0205)
 156 
 157 /*minor version for MPI v2.6 compatible products */
 158 #define MPI26_VERSION_MINOR                 (0x06)
 159 #define MPI26_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
 160                                         MPI26_VERSION_MINOR)
 161 #define MPI2_VERSION_02_06                  (0x0206)
 162 
 163 
 164 /* Unit and Dev versioning for this MPI header set */
 165 #define MPI2_HEADER_VERSION_UNIT            (0x36)
 166 #define MPI2_HEADER_VERSION_DEV             (0x00)
 167 #define MPI2_HEADER_VERSION_UNIT_MASK       (0xFF00)
 168 #define MPI2_HEADER_VERSION_UNIT_SHIFT      (8)
 169 #define MPI2_HEADER_VERSION_DEV_MASK        (0x00FF)
 170 #define MPI2_HEADER_VERSION_DEV_SHIFT       (0)
 171 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \
 172                                         MPI2_HEADER_VERSION_DEV)
 173 
 174 /*****************************************************************************
 175 *
 176 *       IOC State Definitions
 177 *
 178 *****************************************************************************/
 179 
 180 #define MPI2_IOC_STATE_RESET               (0x00000000)
 181 #define MPI2_IOC_STATE_READY               (0x10000000)
 182 #define MPI2_IOC_STATE_OPERATIONAL         (0x20000000)
 183 #define MPI2_IOC_STATE_FAULT               (0x40000000)
 184 
 185 #define MPI2_IOC_STATE_MASK                (0xF0000000)
 186 #define MPI2_IOC_STATE_SHIFT               (28)
 187 
 188 /*Fault state range for prodcut specific codes */
 189 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN                 (0x0000)
 190 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX                 (0xEFFF)
 191 
 192 /*****************************************************************************
 193 *
 194 *       System Interface Register Definitions
 195 *
 196 *****************************************************************************/
 197 
 198 typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS {
 199         U32 Doorbell;           /*0x00 */
 200         U32 WriteSequence;      /*0x04 */
 201         U32 HostDiagnostic;     /*0x08 */
 202         U32 Reserved1;          /*0x0C */
 203         U32 DiagRWData;         /*0x10 */
 204         U32 DiagRWAddressLow;   /*0x14 */
 205         U32 DiagRWAddressHigh;  /*0x18 */
 206         U32 Reserved2[5];       /*0x1C */
 207         U32 HostInterruptStatus;        /*0x30 */
 208         U32 HostInterruptMask;  /*0x34 */
 209         U32 DCRData;            /*0x38 */
 210         U32 DCRAddress;         /*0x3C */
 211         U32 Reserved3[2];       /*0x40 */
 212         U32 ReplyFreeHostIndex; /*0x48 */
 213         U32 Reserved4[8];       /*0x4C */
 214         U32 ReplyPostHostIndex; /*0x6C */
 215         U32 Reserved5;          /*0x70 */
 216         U32 HCBSize;            /*0x74 */
 217         U32 HCBAddressLow;      /*0x78 */
 218         U32 HCBAddressHigh;     /*0x7C */
 219         U32 Reserved6[12];      /*0x80 */
 220         U32 Scratchpad[4];      /*0xB0 */
 221         U32 RequestDescriptorPostLow;   /*0xC0 */
 222         U32 RequestDescriptorPostHigh;  /*0xC4 */
 223         U32 AtomicRequestDescriptorPost;/*0xC8 */
 224         U32 Reserved7[13];      /*0xCC */
 225 } MPI2_SYSTEM_INTERFACE_REGS,
 226         *PTR_MPI2_SYSTEM_INTERFACE_REGS,
 227         Mpi2SystemInterfaceRegs_t,
 228         *pMpi2SystemInterfaceRegs_t;
 229 
 230 /*
 231  *Defines for working with the Doorbell register.
 232  */
 233 #define MPI2_DOORBELL_OFFSET                    (0x00000000)
 234 
 235 /*IOC --> System values */
 236 #define MPI2_DOORBELL_USED                      (0x08000000)
 237 #define MPI2_DOORBELL_WHO_INIT_MASK             (0x07000000)
 238 #define MPI2_DOORBELL_WHO_INIT_SHIFT            (24)
 239 #define MPI2_DOORBELL_FAULT_CODE_MASK           (0x0000FFFF)
 240 #define MPI2_DOORBELL_DATA_MASK                 (0x0000FFFF)
 241 
 242 /*System --> IOC values */
 243 #define MPI2_DOORBELL_FUNCTION_MASK             (0xFF000000)
 244 #define MPI2_DOORBELL_FUNCTION_SHIFT            (24)
 245 #define MPI2_DOORBELL_ADD_DWORDS_MASK           (0x00FF0000)
 246 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT          (16)
 247 
 248 /*
 249  *Defines for the WriteSequence register
 250  */
 251 #define MPI2_WRITE_SEQUENCE_OFFSET              (0x00000004)
 252 #define MPI2_WRSEQ_KEY_VALUE_MASK               (0x0000000F)
 253 #define MPI2_WRSEQ_FLUSH_KEY_VALUE              (0x0)
 254 #define MPI2_WRSEQ_1ST_KEY_VALUE                (0xF)
 255 #define MPI2_WRSEQ_2ND_KEY_VALUE                (0x4)
 256 #define MPI2_WRSEQ_3RD_KEY_VALUE                (0xB)
 257 #define MPI2_WRSEQ_4TH_KEY_VALUE                (0x2)
 258 #define MPI2_WRSEQ_5TH_KEY_VALUE                (0x7)
 259 #define MPI2_WRSEQ_6TH_KEY_VALUE                (0xD)
 260 
 261 /*
 262  *Defines for the HostDiagnostic register
 263  */
 264 #define MPI2_HOST_DIAGNOSTIC_OFFSET             (0x00000008)
 265 
 266 #define MPI26_DIAG_SECURE_BOOT                  (0x80000000)
 267 
 268 #define MPI2_DIAG_SBR_RELOAD                    (0x00002000)
 269 
 270 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK       (0x00001800)
 271 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT    (0x00000000)
 272 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW       (0x00000800)
 273 
 274 /* Defines for V7A/V7R HostDiagnostic Register */
 275 #define MPI26_DIAG_BOOT_DEVICE_SEL_64FLASH      (0x00000000)
 276 #define MPI26_DIAG_BOOT_DEVICE_SEL_64HCDW       (0x00000800)
 277 #define MPI26_DIAG_BOOT_DEVICE_SEL_32FLASH      (0x00001000)
 278 #define MPI26_DIAG_BOOT_DEVICE_SEL_32HCDW       (0x00001800)
 279 
 280 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG           (0x00000400)
 281 #define MPI2_DIAG_FORCE_HCB_ON_RESET            (0x00000200)
 282 #define MPI2_DIAG_HCB_MODE                      (0x00000100)
 283 #define MPI2_DIAG_DIAG_WRITE_ENABLE             (0x00000080)
 284 #define MPI2_DIAG_FLASH_BAD_SIG                 (0x00000040)
 285 #define MPI2_DIAG_RESET_HISTORY                 (0x00000020)
 286 #define MPI2_DIAG_DIAG_RW_ENABLE                (0x00000010)
 287 #define MPI2_DIAG_RESET_ADAPTER                 (0x00000004)
 288 #define MPI2_DIAG_HOLD_IOC_RESET                (0x00000002)
 289 
 290 /*
 291  *Offsets for DiagRWData and address
 292  */
 293 #define MPI2_DIAG_RW_DATA_OFFSET                (0x00000010)
 294 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET         (0x00000014)
 295 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET        (0x00000018)
 296 
 297 /*
 298  *Defines for the HostInterruptStatus register
 299  */
 300 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET       (0x00000030)
 301 #define MPI2_HIS_SYS2IOC_DB_STATUS              (0x80000000)
 302 #define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS
 303 #define MPI2_HIS_RESET_IRQ_STATUS               (0x40000000)
 304 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT     (0x00000008)
 305 #define MPI2_HIS_IOC2SYS_DB_STATUS              (0x00000001)
 306 #define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS
 307 
 308 /*
 309  *Defines for the HostInterruptMask register
 310  */
 311 #define MPI2_HOST_INTERRUPT_MASK_OFFSET         (0x00000034)
 312 #define MPI2_HIM_RESET_IRQ_MASK                 (0x40000000)
 313 #define MPI2_HIM_REPLY_INT_MASK                 (0x00000008)
 314 #define MPI2_HIM_RIM                            MPI2_HIM_REPLY_INT_MASK
 315 #define MPI2_HIM_IOC2SYS_DB_MASK                (0x00000001)
 316 #define MPI2_HIM_DIM                            MPI2_HIM_IOC2SYS_DB_MASK
 317 
 318 /*
 319  *Offsets for DCRData and address
 320  */
 321 #define MPI2_DCR_DATA_OFFSET                    (0x00000038)
 322 #define MPI2_DCR_ADDRESS_OFFSET                 (0x0000003C)
 323 
 324 /*
 325  *Offset for the Reply Free Queue
 326  */
 327 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET       (0x00000048)
 328 
 329 /*
 330  *Defines for the Reply Descriptor Post Queue
 331  */
 332 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET       (0x0000006C)
 333 #define MPI2_REPLY_POST_HOST_INDEX_MASK         (0x00FFFFFF)
 334 #define MPI2_RPHI_MSIX_INDEX_MASK               (0xFF000000)
 335 #define MPI2_RPHI_MSIX_INDEX_SHIFT              (24)
 336 #define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET  (0x0000030C) /*MPI v2.5 only*/
 337 
 338 
 339 /*
 340  *Defines for the HCBSize and address
 341  */
 342 #define MPI2_HCB_SIZE_OFFSET                    (0x00000074)
 343 #define MPI2_HCB_SIZE_SIZE_MASK                 (0xFFFFF000)
 344 #define MPI2_HCB_SIZE_HCB_ENABLE                (0x00000001)
 345 
 346 #define MPI2_HCB_ADDRESS_LOW_OFFSET             (0x00000078)
 347 #define MPI2_HCB_ADDRESS_HIGH_OFFSET            (0x0000007C)
 348 
 349 /*
 350  *Offsets for the Scratchpad registers
 351  */
 352 #define MPI26_SCRATCHPAD0_OFFSET                (0x000000B0)
 353 #define MPI26_SCRATCHPAD1_OFFSET                (0x000000B4)
 354 #define MPI26_SCRATCHPAD2_OFFSET                (0x000000B8)
 355 #define MPI26_SCRATCHPAD3_OFFSET                (0x000000BC)
 356 
 357 /*
 358  *Offsets for the Request Descriptor Post Queue
 359  */
 360 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET     (0x000000C0)
 361 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET    (0x000000C4)
 362 #define MPI26_ATOMIC_REQUEST_DESCRIPTOR_POST_OFFSET (0x000000C8)
 363 
 364 /*Hard Reset delay timings */
 365 #define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC     (50000)
 366 #define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC    (255000)
 367 #define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC    (256000)
 368 
 369 /*****************************************************************************
 370 *
 371 *       Message Descriptors
 372 *
 373 *****************************************************************************/
 374 
 375 /*Request Descriptors */
 376 
 377 /*Default Request Descriptor */
 378 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR {
 379         U8 RequestFlags;        /*0x00 */
 380         U8 MSIxIndex;           /*0x01 */
 381         U16 SMID;               /*0x02 */
 382         U16 LMID;               /*0x04 */
 383         U16 DescriptorTypeDependent;    /*0x06 */
 384 } MPI2_DEFAULT_REQUEST_DESCRIPTOR,
 385         *PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
 386         Mpi2DefaultRequestDescriptor_t,
 387         *pMpi2DefaultRequestDescriptor_t;
 388 
 389 /*defines for the RequestFlags field */
 390 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK               (0x1E)
 391 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_RSHIFT             (1)
 392 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO                 (0x00)
 393 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET             (0x02)
 394 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY           (0x06)
 395 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE            (0x08)
 396 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR        (0x0A)
 397 #define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO      (0x0C)
 398 #define MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED      (0x10)
 399 
 400 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER         (0x01)
 401 
 402 /*High Priority Request Descriptor */
 403 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
 404         U8 RequestFlags;        /*0x00 */
 405         U8 MSIxIndex;           /*0x01 */
 406         U16 SMID;               /*0x02 */
 407         U16 LMID;               /*0x04 */
 408         U16 Reserved1;          /*0x06 */
 409 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
 410         *PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
 411         Mpi2HighPriorityRequestDescriptor_t,
 412         *pMpi2HighPriorityRequestDescriptor_t;
 413 
 414 /*SCSI IO Request Descriptor */
 415 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
 416         U8 RequestFlags;        /*0x00 */
 417         U8 MSIxIndex;           /*0x01 */
 418         U16 SMID;               /*0x02 */
 419         U16 LMID;               /*0x04 */
 420         U16 DevHandle;          /*0x06 */
 421 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
 422         *PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
 423         Mpi2SCSIIORequestDescriptor_t,
 424         *pMpi2SCSIIORequestDescriptor_t;
 425 
 426 /*SCSI Target Request Descriptor */
 427 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
 428         U8 RequestFlags;        /*0x00 */
 429         U8 MSIxIndex;           /*0x01 */
 430         U16 SMID;               /*0x02 */
 431         U16 LMID;               /*0x04 */
 432         U16 IoIndex;            /*0x06 */
 433 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
 434         *PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
 435         Mpi2SCSITargetRequestDescriptor_t,
 436         *pMpi2SCSITargetRequestDescriptor_t;
 437 
 438 /*RAID Accelerator Request Descriptor */
 439 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
 440         U8 RequestFlags;        /*0x00 */
 441         U8 MSIxIndex;           /*0x01 */
 442         U16 SMID;               /*0x02 */
 443         U16 LMID;               /*0x04 */
 444         U16 Reserved;           /*0x06 */
 445 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
 446         *PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
 447         Mpi2RAIDAcceleratorRequestDescriptor_t,
 448         *pMpi2RAIDAcceleratorRequestDescriptor_t;
 449 
 450 /*Fast Path SCSI IO Request Descriptor */
 451 typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR
 452         MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
 453         *PTR_MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
 454         Mpi25FastPathSCSIIORequestDescriptor_t,
 455         *pMpi25FastPathSCSIIORequestDescriptor_t;
 456 
 457 /*PCIe Encapsulated Request Descriptor */
 458 typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR
 459         MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR,
 460         *PTR_MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR,
 461         Mpi26PCIeEncapsulatedRequestDescriptor_t,
 462         *pMpi26PCIeEncapsulatedRequestDescriptor_t;
 463 
 464 /*union of Request Descriptors */
 465 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION {
 466         MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
 467         MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
 468         MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
 469         MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
 470         MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
 471         MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO;
 472         MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR PCIeEncapsulated;
 473         U64 Words;
 474 } MPI2_REQUEST_DESCRIPTOR_UNION,
 475         *PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
 476         Mpi2RequestDescriptorUnion_t,
 477         *pMpi2RequestDescriptorUnion_t;
 478 
 479 /*Atomic Request Descriptors */
 480 
 481 /*
 482  * All Atomic Request Descriptors have the same format, so the following
 483  * structure is used for all Atomic Request Descriptors:
 484  *      Atomic Default Request Descriptor
 485  *      Atomic High Priority Request Descriptor
 486  *      Atomic SCSI IO Request Descriptor
 487  *      Atomic SCSI Target Request Descriptor
 488  *      Atomic RAID Accelerator Request Descriptor
 489  *      Atomic Fast Path SCSI IO Request Descriptor
 490  *      Atomic PCIe Encapsulated Request Descriptor
 491  */
 492 
 493 /*Atomic Request Descriptor */
 494 typedef struct _MPI26_ATOMIC_REQUEST_DESCRIPTOR {
 495         U8 RequestFlags;        /* 0x00 */
 496         U8 MSIxIndex;           /* 0x01 */
 497         U16 SMID;               /* 0x02 */
 498 } MPI26_ATOMIC_REQUEST_DESCRIPTOR,
 499         *PTR_MPI26_ATOMIC_REQUEST_DESCRIPTOR,
 500         Mpi26AtomicRequestDescriptor_t,
 501         *pMpi26AtomicRequestDescriptor_t;
 502 
 503 /*for the RequestFlags field, use the same
 504  *defines as MPI2_DEFAULT_REQUEST_DESCRIPTOR
 505  */
 506 
 507 /*Reply Descriptors */
 508 
 509 /*Default Reply Descriptor */
 510 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR {
 511         U8 ReplyFlags;          /*0x00 */
 512         U8 MSIxIndex;           /*0x01 */
 513         U16 DescriptorTypeDependent1;   /*0x02 */
 514         U32 DescriptorTypeDependent2;   /*0x04 */
 515 } MPI2_DEFAULT_REPLY_DESCRIPTOR,
 516         *PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
 517         Mpi2DefaultReplyDescriptor_t,
 518         *pMpi2DefaultReplyDescriptor_t;
 519 
 520 /*defines for the ReplyFlags field */
 521 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK                   (0x0F)
 522 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS             (0x00)
 523 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY               (0x01)
 524 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS        (0x02)
 525 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER       (0x03)
 526 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS    (0x05)
 527 #define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS  (0x06)
 528 #define MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS  (0x08)
 529 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED                      (0x0F)
 530 
 531 /*values for marking a reply descriptor as unused */
 532 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK             (0xFFFFFFFF)
 533 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK             (0xFFFFFFFF)
 534 
 535 /*Address Reply Descriptor */
 536 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR {
 537         U8 ReplyFlags;          /*0x00 */
 538         U8 MSIxIndex;           /*0x01 */
 539         U16 SMID;               /*0x02 */
 540         U32 ReplyFrameAddress;  /*0x04 */
 541 } MPI2_ADDRESS_REPLY_DESCRIPTOR,
 542         *PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
 543         Mpi2AddressReplyDescriptor_t,
 544         *pMpi2AddressReplyDescriptor_t;
 545 
 546 #define MPI2_ADDRESS_REPLY_SMID_INVALID                 (0x00)
 547 
 548 /*SCSI IO Success Reply Descriptor */
 549 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
 550         U8 ReplyFlags;          /*0x00 */
 551         U8 MSIxIndex;           /*0x01 */
 552         U16 SMID;               /*0x02 */
 553         U16 TaskTag;            /*0x04 */
 554         U16 Reserved1;          /*0x06 */
 555 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
 556         *PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
 557         Mpi2SCSIIOSuccessReplyDescriptor_t,
 558         *pMpi2SCSIIOSuccessReplyDescriptor_t;
 559 
 560 /*TargetAssist Success Reply Descriptor */
 561 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
 562         U8 ReplyFlags;          /*0x00 */
 563         U8 MSIxIndex;           /*0x01 */
 564         U16 SMID;               /*0x02 */
 565         U8 SequenceNumber;      /*0x04 */
 566         U8 Reserved1;           /*0x05 */
 567         U16 IoIndex;            /*0x06 */
 568 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
 569         *PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
 570         Mpi2TargetAssistSuccessReplyDescriptor_t,
 571         *pMpi2TargetAssistSuccessReplyDescriptor_t;
 572 
 573 /*Target Command Buffer Reply Descriptor */
 574 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
 575         U8 ReplyFlags;          /*0x00 */
 576         U8 MSIxIndex;           /*0x01 */
 577         U8 VP_ID;               /*0x02 */
 578         U8 Flags;               /*0x03 */
 579         U16 InitiatorDevHandle; /*0x04 */
 580         U16 IoIndex;            /*0x06 */
 581 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
 582         *PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
 583         Mpi2TargetCommandBufferReplyDescriptor_t,
 584         *pMpi2TargetCommandBufferReplyDescriptor_t;
 585 
 586 /*defines for Flags field */
 587 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK     (0x3F)
 588 
 589 /*RAID Accelerator Success Reply Descriptor */
 590 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
 591         U8 ReplyFlags;          /*0x00 */
 592         U8 MSIxIndex;           /*0x01 */
 593         U16 SMID;               /*0x02 */
 594         U32 Reserved;           /*0x04 */
 595 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
 596         *PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
 597         Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
 598         *pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
 599 
 600 /*Fast Path SCSI IO Success Reply Descriptor */
 601 typedef MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
 602         MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
 603         *PTR_MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
 604         Mpi25FastPathSCSIIOSuccessReplyDescriptor_t,
 605         *pMpi25FastPathSCSIIOSuccessReplyDescriptor_t;
 606 
 607 /*PCIe Encapsulated Success Reply Descriptor */
 608 typedef MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
 609         MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR,
 610         *PTR_MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR,
 611         Mpi26PCIeEncapsulatedSuccessReplyDescriptor_t,
 612         *pMpi26PCIeEncapsulatedSuccessReplyDescriptor_t;
 613 
 614 /*union of Reply Descriptors */
 615 typedef union _MPI2_REPLY_DESCRIPTORS_UNION {
 616         MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
 617         MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
 618         MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
 619         MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
 620         MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
 621         MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
 622         MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR FastPathSCSIIOSuccess;
 623         MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR
 624                                                 PCIeEncapsulatedSuccess;
 625         U64 Words;
 626 } MPI2_REPLY_DESCRIPTORS_UNION,
 627         *PTR_MPI2_REPLY_DESCRIPTORS_UNION,
 628         Mpi2ReplyDescriptorsUnion_t,
 629         *pMpi2ReplyDescriptorsUnion_t;
 630 
 631 /*****************************************************************************
 632 *
 633 *       Message Functions
 634 *
 635 *****************************************************************************/
 636 
 637 #define MPI2_FUNCTION_SCSI_IO_REQUEST               (0x00)
 638 #define MPI2_FUNCTION_SCSI_TASK_MGMT                (0x01)
 639 #define MPI2_FUNCTION_IOC_INIT                      (0x02)
 640 #define MPI2_FUNCTION_IOC_FACTS                     (0x03)
 641 #define MPI2_FUNCTION_CONFIG                        (0x04)
 642 #define MPI2_FUNCTION_PORT_FACTS                    (0x05)
 643 #define MPI2_FUNCTION_PORT_ENABLE                   (0x06)
 644 #define MPI2_FUNCTION_EVENT_NOTIFICATION            (0x07)
 645 #define MPI2_FUNCTION_EVENT_ACK                     (0x08)
 646 #define MPI2_FUNCTION_FW_DOWNLOAD                   (0x09)
 647 #define MPI2_FUNCTION_TARGET_ASSIST                 (0x0B)
 648 #define MPI2_FUNCTION_TARGET_STATUS_SEND            (0x0C)
 649 #define MPI2_FUNCTION_TARGET_MODE_ABORT             (0x0D)
 650 #define MPI2_FUNCTION_FW_UPLOAD                     (0x12)
 651 #define MPI2_FUNCTION_RAID_ACTION                   (0x15)
 652 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH      (0x16)
 653 #define MPI2_FUNCTION_TOOLBOX                       (0x17)
 654 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR      (0x18)
 655 #define MPI2_FUNCTION_SMP_PASSTHROUGH               (0x1A)
 656 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL           (0x1B)
 657 #define MPI2_FUNCTION_IO_UNIT_CONTROL               (0x1B)
 658 #define MPI2_FUNCTION_SATA_PASSTHROUGH              (0x1C)
 659 #define MPI2_FUNCTION_DIAG_BUFFER_POST              (0x1D)
 660 #define MPI2_FUNCTION_DIAG_RELEASE                  (0x1E)
 661 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST      (0x24)
 662 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST      (0x25)
 663 #define MPI2_FUNCTION_RAID_ACCELERATOR              (0x2C)
 664 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION   (0x2F)
 665 #define MPI2_FUNCTION_PWR_MGMT_CONTROL              (0x30)
 666 #define MPI2_FUNCTION_SEND_HOST_MESSAGE             (0x31)
 667 #define MPI2_FUNCTION_NVME_ENCAPSULATED             (0x33)
 668 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC          (0xF0)
 669 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC          (0xFF)
 670 
 671 /*Doorbell functions */
 672 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET        (0x40)
 673 #define MPI2_FUNCTION_HANDSHAKE                     (0x42)
 674 
 675 /*****************************************************************************
 676 *
 677 *       IOC Status Values
 678 *
 679 *****************************************************************************/
 680 
 681 /*mask for IOCStatus status value */
 682 #define MPI2_IOCSTATUS_MASK                     (0x7FFF)
 683 
 684 /****************************************************************************
 685 * Common IOCStatus values for all replies
 686 ****************************************************************************/
 687 
 688 #define MPI2_IOCSTATUS_SUCCESS                      (0x0000)
 689 #define MPI2_IOCSTATUS_INVALID_FUNCTION             (0x0001)
 690 #define MPI2_IOCSTATUS_BUSY                         (0x0002)
 691 #define MPI2_IOCSTATUS_INVALID_SGL                  (0x0003)
 692 #define MPI2_IOCSTATUS_INTERNAL_ERROR               (0x0004)
 693 #define MPI2_IOCSTATUS_INVALID_VPID                 (0x0005)
 694 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES       (0x0006)
 695 #define MPI2_IOCSTATUS_INVALID_FIELD                (0x0007)
 696 #define MPI2_IOCSTATUS_INVALID_STATE                (0x0008)
 697 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED       (0x0009)
 698 /*MPI v2.6 and later */
 699 #define MPI2_IOCSTATUS_INSUFFICIENT_POWER           (0x000A)
 700 #define MPI2_IOCSTATUS_FAILURE                      (0x000F)
 701 
 702 /****************************************************************************
 703 * Config IOCStatus values
 704 ****************************************************************************/
 705 
 706 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION        (0x0020)
 707 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE          (0x0021)
 708 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE          (0x0022)
 709 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA          (0x0023)
 710 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS           (0x0024)
 711 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT           (0x0025)
 712 
 713 /****************************************************************************
 714 * SCSI IO Reply
 715 ****************************************************************************/
 716 
 717 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR         (0x0040)
 718 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE       (0x0042)
 719 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE        (0x0043)
 720 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN            (0x0044)
 721 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN           (0x0045)
 722 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR           (0x0046)
 723 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR          (0x0047)
 724 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED         (0x0048)
 725 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH       (0x0049)
 726 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED        (0x004A)
 727 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED          (0x004B)
 728 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED          (0x004C)
 729 
 730 /****************************************************************************
 731 * For use by SCSI Initiator and SCSI Target end-to-end data protection
 732 ****************************************************************************/
 733 
 734 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR             (0x004D)
 735 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR           (0x004E)
 736 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR           (0x004F)
 737 
 738 /****************************************************************************
 739 * SCSI Target values
 740 ****************************************************************************/
 741 
 742 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX      (0x0062)
 743 #define MPI2_IOCSTATUS_TARGET_ABORTED               (0x0063)
 744 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE     (0x0064)
 745 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION         (0x0065)
 746 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH   (0x006A)
 747 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR     (0x006D)
 748 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA   (0x006E)
 749 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT          (0x006F)
 750 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT       (0x0070)
 751 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED          (0x0071)
 752 
 753 /****************************************************************************
 754 * Serial Attached SCSI values
 755 ****************************************************************************/
 756 
 757 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED       (0x0090)
 758 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN         (0x0091)
 759 
 760 /****************************************************************************
 761 * Diagnostic Buffer Post / Diagnostic Release values
 762 ****************************************************************************/
 763 
 764 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED          (0x00A0)
 765 
 766 /****************************************************************************
 767 * RAID Accelerator values
 768 ****************************************************************************/
 769 
 770 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR             (0x00B0)
 771 
 772 /****************************************************************************
 773 * IOCStatus flag to indicate that log info is available
 774 ****************************************************************************/
 775 
 776 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE      (0x8000)
 777 
 778 /****************************************************************************
 779 * IOCLogInfo Types
 780 ****************************************************************************/
 781 
 782 #define MPI2_IOCLOGINFO_TYPE_MASK               (0xF0000000)
 783 #define MPI2_IOCLOGINFO_TYPE_SHIFT              (28)
 784 #define MPI2_IOCLOGINFO_TYPE_NONE               (0x0)
 785 #define MPI2_IOCLOGINFO_TYPE_SCSI               (0x1)
 786 #define MPI2_IOCLOGINFO_TYPE_FC                 (0x2)
 787 #define MPI2_IOCLOGINFO_TYPE_SAS                (0x3)
 788 #define MPI2_IOCLOGINFO_TYPE_ISCSI              (0x4)
 789 #define MPI2_IOCLOGINFO_LOG_DATA_MASK           (0x0FFFFFFF)
 790 
 791 /*****************************************************************************
 792 *
 793 *       Standard Message Structures
 794 *
 795 *****************************************************************************/
 796 
 797 /****************************************************************************
 798 *Request Message Header for all request messages
 799 ****************************************************************************/
 800 
 801 typedef struct _MPI2_REQUEST_HEADER {
 802         U16 FunctionDependent1; /*0x00 */
 803         U8 ChainOffset;         /*0x02 */
 804         U8 Function;            /*0x03 */
 805         U16 FunctionDependent2; /*0x04 */
 806         U8 FunctionDependent3;  /*0x06 */
 807         U8 MsgFlags;            /*0x07 */
 808         U8 VP_ID;               /*0x08 */
 809         U8 VF_ID;               /*0x09 */
 810         U16 Reserved1;          /*0x0A */
 811 } MPI2_REQUEST_HEADER, *PTR_MPI2_REQUEST_HEADER,
 812         MPI2RequestHeader_t, *pMPI2RequestHeader_t;
 813 
 814 /****************************************************************************
 815 * Default Reply
 816 ****************************************************************************/
 817 
 818 typedef struct _MPI2_DEFAULT_REPLY {
 819         U16 FunctionDependent1; /*0x00 */
 820         U8 MsgLength;           /*0x02 */
 821         U8 Function;            /*0x03 */
 822         U16 FunctionDependent2; /*0x04 */
 823         U8 FunctionDependent3;  /*0x06 */
 824         U8 MsgFlags;            /*0x07 */
 825         U8 VP_ID;               /*0x08 */
 826         U8 VF_ID;               /*0x09 */
 827         U16 Reserved1;          /*0x0A */
 828         U16 FunctionDependent5; /*0x0C */
 829         U16 IOCStatus;          /*0x0E */
 830         U32 IOCLogInfo;         /*0x10 */
 831 } MPI2_DEFAULT_REPLY, *PTR_MPI2_DEFAULT_REPLY,
 832         MPI2DefaultReply_t, *pMPI2DefaultReply_t;
 833 
 834 /*common version structure/union used in messages and configuration pages */
 835 
 836 typedef struct _MPI2_VERSION_STRUCT {
 837         U8 Dev;                 /*0x00 */
 838         U8 Unit;                /*0x01 */
 839         U8 Minor;               /*0x02 */
 840         U8 Major;               /*0x03 */
 841 } MPI2_VERSION_STRUCT;
 842 
 843 typedef union _MPI2_VERSION_UNION {
 844         MPI2_VERSION_STRUCT Struct;
 845         U32 Word;
 846 } MPI2_VERSION_UNION;
 847 
 848 /*LUN field defines, common to many structures */
 849 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING             (0x0000FFFF)
 850 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING            (0xFFFF0000)
 851 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING             (0x0000FFFF)
 852 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING            (0xFFFF0000)
 853 #define MPI2_LUN_LEVEL_1_WORD                       (0xFF00)
 854 #define MPI2_LUN_LEVEL_1_DWORD                      (0x0000FF00)
 855 
 856 /*****************************************************************************
 857 *
 858 *       Fusion-MPT MPI Scatter Gather Elements
 859 *
 860 *****************************************************************************/
 861 
 862 /****************************************************************************
 863 * MPI Simple Element structures
 864 ****************************************************************************/
 865 
 866 typedef struct _MPI2_SGE_SIMPLE32 {
 867         U32 FlagsLength;
 868         U32 Address;
 869 } MPI2_SGE_SIMPLE32, *PTR_MPI2_SGE_SIMPLE32,
 870         Mpi2SGESimple32_t, *pMpi2SGESimple32_t;
 871 
 872 typedef struct _MPI2_SGE_SIMPLE64 {
 873         U32 FlagsLength;
 874         U64 Address;
 875 } MPI2_SGE_SIMPLE64, *PTR_MPI2_SGE_SIMPLE64,
 876         Mpi2SGESimple64_t, *pMpi2SGESimple64_t;
 877 
 878 typedef struct _MPI2_SGE_SIMPLE_UNION {
 879         U32 FlagsLength;
 880         union {
 881                 U32 Address32;
 882                 U64 Address64;
 883         } u;
 884 } MPI2_SGE_SIMPLE_UNION,
 885         *PTR_MPI2_SGE_SIMPLE_UNION,
 886         Mpi2SGESimpleUnion_t,
 887         *pMpi2SGESimpleUnion_t;
 888 
 889 /****************************************************************************
 890 * MPI Chain Element structures - for MPI v2.0 products only
 891 ****************************************************************************/
 892 
 893 typedef struct _MPI2_SGE_CHAIN32 {
 894         U16 Length;
 895         U8 NextChainOffset;
 896         U8 Flags;
 897         U32 Address;
 898 } MPI2_SGE_CHAIN32, *PTR_MPI2_SGE_CHAIN32,
 899         Mpi2SGEChain32_t, *pMpi2SGEChain32_t;
 900 
 901 typedef struct _MPI2_SGE_CHAIN64 {
 902         U16 Length;
 903         U8 NextChainOffset;
 904         U8 Flags;
 905         U64 Address;
 906 } MPI2_SGE_CHAIN64, *PTR_MPI2_SGE_CHAIN64,
 907         Mpi2SGEChain64_t, *pMpi2SGEChain64_t;
 908 
 909 typedef struct _MPI2_SGE_CHAIN_UNION {
 910         U16 Length;
 911         U8 NextChainOffset;
 912         U8 Flags;
 913         union {
 914                 U32 Address32;
 915                 U64 Address64;
 916         } u;
 917 } MPI2_SGE_CHAIN_UNION,
 918         *PTR_MPI2_SGE_CHAIN_UNION,
 919         Mpi2SGEChainUnion_t,
 920         *pMpi2SGEChainUnion_t;
 921 
 922 /****************************************************************************
 923 * MPI Transaction Context Element structures - for MPI v2.0 products only
 924 ****************************************************************************/
 925 
 926 typedef struct _MPI2_SGE_TRANSACTION32 {
 927         U8 Reserved;
 928         U8 ContextSize;
 929         U8 DetailsLength;
 930         U8 Flags;
 931         U32 TransactionContext[1];
 932         U32 TransactionDetails[1];
 933 } MPI2_SGE_TRANSACTION32,
 934         *PTR_MPI2_SGE_TRANSACTION32,
 935         Mpi2SGETransaction32_t,
 936         *pMpi2SGETransaction32_t;
 937 
 938 typedef struct _MPI2_SGE_TRANSACTION64 {
 939         U8 Reserved;
 940         U8 ContextSize;
 941         U8 DetailsLength;
 942         U8 Flags;
 943         U32 TransactionContext[2];
 944         U32 TransactionDetails[1];
 945 } MPI2_SGE_TRANSACTION64,
 946         *PTR_MPI2_SGE_TRANSACTION64,
 947         Mpi2SGETransaction64_t,
 948         *pMpi2SGETransaction64_t;
 949 
 950 typedef struct _MPI2_SGE_TRANSACTION96 {
 951         U8 Reserved;
 952         U8 ContextSize;
 953         U8 DetailsLength;
 954         U8 Flags;
 955         U32 TransactionContext[3];
 956         U32 TransactionDetails[1];
 957 } MPI2_SGE_TRANSACTION96, *PTR_MPI2_SGE_TRANSACTION96,
 958         Mpi2SGETransaction96_t, *pMpi2SGETransaction96_t;
 959 
 960 typedef struct _MPI2_SGE_TRANSACTION128 {
 961         U8 Reserved;
 962         U8 ContextSize;
 963         U8 DetailsLength;
 964         U8 Flags;
 965         U32 TransactionContext[4];
 966         U32 TransactionDetails[1];
 967 } MPI2_SGE_TRANSACTION128, *PTR_MPI2_SGE_TRANSACTION128,
 968         Mpi2SGETransaction_t128, *pMpi2SGETransaction_t128;
 969 
 970 typedef struct _MPI2_SGE_TRANSACTION_UNION {
 971         U8 Reserved;
 972         U8 ContextSize;
 973         U8 DetailsLength;
 974         U8 Flags;
 975         union {
 976                 U32 TransactionContext32[1];
 977                 U32 TransactionContext64[2];
 978                 U32 TransactionContext96[3];
 979                 U32 TransactionContext128[4];
 980         } u;
 981         U32 TransactionDetails[1];
 982 } MPI2_SGE_TRANSACTION_UNION,
 983         *PTR_MPI2_SGE_TRANSACTION_UNION,
 984         Mpi2SGETransactionUnion_t,
 985         *pMpi2SGETransactionUnion_t;
 986 
 987 /****************************************************************************
 988 * MPI SGE union for IO SGL's - for MPI v2.0 products only
 989 ****************************************************************************/
 990 
 991 typedef struct _MPI2_MPI_SGE_IO_UNION {
 992         union {
 993                 MPI2_SGE_SIMPLE_UNION Simple;
 994                 MPI2_SGE_CHAIN_UNION Chain;
 995         } u;
 996 } MPI2_MPI_SGE_IO_UNION, *PTR_MPI2_MPI_SGE_IO_UNION,
 997         Mpi2MpiSGEIOUnion_t, *pMpi2MpiSGEIOUnion_t;
 998 
 999 /****************************************************************************
1000 * MPI SGE union for SGL's with Simple and Transaction elements - for MPI v2.0 products only
1001 ****************************************************************************/
1002 
1003 typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION {
1004         union {
1005                 MPI2_SGE_SIMPLE_UNION Simple;
1006                 MPI2_SGE_TRANSACTION_UNION Transaction;
1007         } u;
1008 } MPI2_SGE_TRANS_SIMPLE_UNION,
1009         *PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
1010         Mpi2SGETransSimpleUnion_t,
1011         *pMpi2SGETransSimpleUnion_t;
1012 
1013 /****************************************************************************
1014 * All MPI SGE types union
1015 ****************************************************************************/
1016 
1017 typedef struct _MPI2_MPI_SGE_UNION {
1018         union {
1019                 MPI2_SGE_SIMPLE_UNION Simple;
1020                 MPI2_SGE_CHAIN_UNION Chain;
1021                 MPI2_SGE_TRANSACTION_UNION Transaction;
1022         } u;
1023 } MPI2_MPI_SGE_UNION, *PTR_MPI2_MPI_SGE_UNION,
1024         Mpi2MpiSgeUnion_t, *pMpi2MpiSgeUnion_t;
1025 
1026 /****************************************************************************
1027 * MPI SGE field definition and masks
1028 ****************************************************************************/
1029 
1030 /*Flags field bit definitions */
1031 
1032 #define MPI2_SGE_FLAGS_LAST_ELEMENT             (0x80)
1033 #define MPI2_SGE_FLAGS_END_OF_BUFFER            (0x40)
1034 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK        (0x30)
1035 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS            (0x08)
1036 #define MPI2_SGE_FLAGS_DIRECTION                (0x04)
1037 #define MPI2_SGE_FLAGS_ADDRESS_SIZE             (0x02)
1038 #define MPI2_SGE_FLAGS_END_OF_LIST              (0x01)
1039 
1040 #define MPI2_SGE_FLAGS_SHIFT                    (24)
1041 
1042 #define MPI2_SGE_LENGTH_MASK                    (0x00FFFFFF)
1043 #define MPI2_SGE_CHAIN_LENGTH_MASK              (0x0000FFFF)
1044 
1045 /*Element Type */
1046 
1047 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT      (0x00)
1048 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT           (0x10)
1049 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT            (0x30)
1050 #define MPI2_SGE_FLAGS_ELEMENT_MASK             (0x30)
1051 
1052 /*Address location */
1053 
1054 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS           (0x00)
1055 
1056 /*Direction */
1057 
1058 #define MPI2_SGE_FLAGS_IOC_TO_HOST              (0x00)
1059 #define MPI2_SGE_FLAGS_HOST_TO_IOC              (0x04)
1060 
1061 #define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST)
1062 #define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC)
1063 
1064 /*Address Size */
1065 
1066 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING        (0x00)
1067 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING        (0x02)
1068 
1069 /*Context Size */
1070 
1071 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT           (0x00)
1072 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT           (0x02)
1073 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT           (0x04)
1074 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT          (0x06)
1075 
1076 #define MPI2_SGE_CHAIN_OFFSET_MASK              (0x00FF0000)
1077 #define MPI2_SGE_CHAIN_OFFSET_SHIFT             (16)
1078 
1079 /****************************************************************************
1080 * MPI SGE operation Macros
1081 ****************************************************************************/
1082 
1083 /*SIMPLE FlagsLength manipulations... */
1084 #define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
1085 #define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> \
1086                                         MPI2_SGE_FLAGS_SHIFT)
1087 #define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK)
1088 #define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
1089 
1090 #define MPI2_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_SGE_SET_FLAGS(f) | \
1091                                         MPI2_SGE_LENGTH(l))
1092 
1093 #define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
1094 #define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength)
1095 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \
1096                                         MPI2_SGE_SET_FLAGS_LENGTH(f, l))
1097 
1098 /*CAUTION - The following are READ-MODIFY-WRITE! */
1099 #define MPI2_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \
1100                                         MPI2_SGE_SET_FLAGS(f))
1101 #define MPI2_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \
1102                                         MPI2_SGE_LENGTH(l))
1103 
1104 #define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> \
1105                                         MPI2_SGE_CHAIN_OFFSET_SHIFT)
1106 
1107 /*****************************************************************************
1108 *
1109 *       Fusion-MPT IEEE Scatter Gather Elements
1110 *
1111 *****************************************************************************/
1112 
1113 /****************************************************************************
1114 * IEEE Simple Element structures
1115 ****************************************************************************/
1116 
1117 /*MPI2_IEEE_SGE_SIMPLE32 is for MPI v2.0 products only */
1118 typedef struct _MPI2_IEEE_SGE_SIMPLE32 {
1119         U32 Address;
1120         U32 FlagsLength;
1121 } MPI2_IEEE_SGE_SIMPLE32, *PTR_MPI2_IEEE_SGE_SIMPLE32,
1122         Mpi2IeeeSgeSimple32_t, *pMpi2IeeeSgeSimple32_t;
1123 
1124 typedef struct _MPI2_IEEE_SGE_SIMPLE64 {
1125         U64 Address;
1126         U32 Length;
1127         U16 Reserved1;
1128         U8 Reserved2;
1129         U8 Flags;
1130 } MPI2_IEEE_SGE_SIMPLE64, *PTR_MPI2_IEEE_SGE_SIMPLE64,
1131         Mpi2IeeeSgeSimple64_t, *pMpi2IeeeSgeSimple64_t;
1132 
1133 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION {
1134         MPI2_IEEE_SGE_SIMPLE32 Simple32;
1135         MPI2_IEEE_SGE_SIMPLE64 Simple64;
1136 } MPI2_IEEE_SGE_SIMPLE_UNION,
1137         *PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
1138         Mpi2IeeeSgeSimpleUnion_t,
1139         *pMpi2IeeeSgeSimpleUnion_t;
1140 
1141 /****************************************************************************
1142 * IEEE Chain Element structures
1143 ****************************************************************************/
1144 
1145 /*MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */
1146 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
1147 
1148 /*MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */
1149 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
1150 
1151 typedef union _MPI2_IEEE_SGE_CHAIN_UNION {
1152         MPI2_IEEE_SGE_CHAIN32 Chain32;
1153         MPI2_IEEE_SGE_CHAIN64 Chain64;
1154 } MPI2_IEEE_SGE_CHAIN_UNION,
1155         *PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1156         Mpi2IeeeSgeChainUnion_t,
1157         *pMpi2IeeeSgeChainUnion_t;
1158 
1159 /*MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 and later */
1160 typedef struct _MPI25_IEEE_SGE_CHAIN64 {
1161         U64 Address;
1162         U32 Length;
1163         U16 Reserved1;
1164         U8 NextChainOffset;
1165         U8 Flags;
1166 } MPI25_IEEE_SGE_CHAIN64,
1167         *PTR_MPI25_IEEE_SGE_CHAIN64,
1168         Mpi25IeeeSgeChain64_t,
1169         *pMpi25IeeeSgeChain64_t;
1170 
1171 /****************************************************************************
1172 * All IEEE SGE types union
1173 ****************************************************************************/
1174 
1175 /*MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */
1176 typedef struct _MPI2_IEEE_SGE_UNION {
1177         union {
1178                 MPI2_IEEE_SGE_SIMPLE_UNION Simple;
1179                 MPI2_IEEE_SGE_CHAIN_UNION Chain;
1180         } u;
1181 } MPI2_IEEE_SGE_UNION, *PTR_MPI2_IEEE_SGE_UNION,
1182         Mpi2IeeeSgeUnion_t, *pMpi2IeeeSgeUnion_t;
1183 
1184 /****************************************************************************
1185 * IEEE SGE union for IO SGL's
1186 ****************************************************************************/
1187 
1188 typedef union _MPI25_SGE_IO_UNION {
1189         MPI2_IEEE_SGE_SIMPLE64 IeeeSimple;
1190         MPI25_IEEE_SGE_CHAIN64 IeeeChain;
1191 } MPI25_SGE_IO_UNION, *PTR_MPI25_SGE_IO_UNION,
1192         Mpi25SGEIOUnion_t, *pMpi25SGEIOUnion_t;
1193 
1194 /****************************************************************************
1195 * IEEE SGE field definitions and masks
1196 ****************************************************************************/
1197 
1198 /*Flags field bit definitions */
1199 
1200 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK   (0x80)
1201 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST        (0x40)
1202 
1203 #define MPI2_IEEE32_SGE_FLAGS_SHIFT             (24)
1204 
1205 #define MPI2_IEEE32_SGE_LENGTH_MASK             (0x00FFFFFF)
1206 
1207 /*Element Type */
1208 
1209 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT      (0x00)
1210 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT       (0x80)
1211 
1212 /*Next Segment Format */
1213 
1214 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK           (0x1C)
1215 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE       (0x00)
1216 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP       (0x08)
1217 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL       (0x10)
1218 
1219 /*Data Location Address Space */
1220 
1221 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK           (0x03)
1222 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR         (0x00)
1223 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR         (0x01)
1224 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR         (0x02)
1225 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR      (0x03)
1226 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR   (0x03)
1227 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR \
1228          (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR)
1229 #define MPI26_IEEE_SGE_FLAGS_IOCCTL_ADDR        (0x02)
1230 
1231 /****************************************************************************
1232 * IEEE SGE operation Macros
1233 ****************************************************************************/
1234 
1235 /*SIMPLE FlagsLength manipulations... */
1236 #define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1237 #define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) \
1238                                  >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1239 #define MPI2_IEEE32_SGE_LENGTH(f)    ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1240 
1241 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) |\
1242                                                  MPI2_IEEE32_SGE_LENGTH(l))
1243 
1244 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) \
1245                         MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1246 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) \
1247                         MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1248 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \
1249                                         MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l))
1250 
1251 /*CAUTION - The following are READ-MODIFY-WRITE! */
1252 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \
1253                                         MPI2_IEEE32_SGE_SET_FLAGS(f))
1254 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \
1255                                         MPI2_IEEE32_SGE_LENGTH(l))
1256 
1257 /*****************************************************************************
1258 *
1259 *       Fusion-MPT MPI/IEEE Scatter Gather Unions
1260 *
1261 *****************************************************************************/
1262 
1263 typedef union _MPI2_SIMPLE_SGE_UNION {
1264         MPI2_SGE_SIMPLE_UNION MpiSimple;
1265         MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1266 } MPI2_SIMPLE_SGE_UNION, *PTR_MPI2_SIMPLE_SGE_UNION,
1267         Mpi2SimpleSgeUntion_t, *pMpi2SimpleSgeUntion_t;
1268 
1269 typedef union _MPI2_SGE_IO_UNION {
1270         MPI2_SGE_SIMPLE_UNION MpiSimple;
1271         MPI2_SGE_CHAIN_UNION MpiChain;
1272         MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1273         MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
1274 } MPI2_SGE_IO_UNION, *PTR_MPI2_SGE_IO_UNION,
1275         Mpi2SGEIOUnion_t, *pMpi2SGEIOUnion_t;
1276 
1277 /****************************************************************************
1278 *
1279 * Values for SGLFlags field, used in many request messages with an SGL
1280 *
1281 ****************************************************************************/
1282 
1283 /*values for MPI SGL Data Location Address Space subfield */
1284 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK            (0x0C)
1285 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE          (0x00)
1286 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE          (0x04)
1287 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE          (0x08)
1288 #define MPI26_SGLFLAGS_IOCPLB_ADDRESS_SPACE         (0x08)
1289 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE       (0x0C)
1290 /*values for SGL Type subfield */
1291 #define MPI2_SGLFLAGS_SGL_TYPE_MASK                 (0x03)
1292 #define MPI2_SGLFLAGS_SGL_TYPE_MPI                  (0x00)
1293 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32               (0x01)
1294 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64               (0x02)
1295 
1296 #endif
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