root/drivers/scsi/NCR5380.h

INCLUDED FROM

DEFINITIONS

1. NCR5380_to_scmd
2. NCR5380_poll_politely
3. NCR5380_dma_xfer_none
4. NCR5380_dma_setup_none
5. NCR5380_dma_residual_none

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* 
   3  * NCR 5380 defines
   4  *
   5  * Copyright 1993, Drew Eckhardt
   6  *      Visionary Computing
   7  *      (Unix consulting and custom programming)
   8  *      drew@colorado.edu
   9  *      +1 (303) 666-5836
  10  *
  11  * For more information, please consult 
  12  *
  13  * NCR 5380 Family
  14  * SCSI Protocol Controller
  15  * Databook
  16  * NCR Microelectronics
  17  * 1635 Aeroplaza Drive
  18  * Colorado Springs, CO 80916
  19  * 1+ (719) 578-3400
  20  * 1+ (800) 334-5454
  21  */
  22 
  23 #ifndef NCR5380_H
  24 #define NCR5380_H
  25 
  26 #include <linux/delay.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/list.h>
  29 #include <linux/workqueue.h>
  30 #include <scsi/scsi_dbg.h>
  31 #include <scsi/scsi_eh.h>
  32 #include <scsi/scsi_transport_spi.h>
  33 
  34 #define NDEBUG_ARBITRATION      0x1
  35 #define NDEBUG_AUTOSENSE        0x2
  36 #define NDEBUG_DMA              0x4
  37 #define NDEBUG_HANDSHAKE        0x8
  38 #define NDEBUG_INFORMATION      0x10
  39 #define NDEBUG_INIT             0x20
  40 #define NDEBUG_INTR             0x40
  41 #define NDEBUG_LINKED           0x80
  42 #define NDEBUG_MAIN             0x100
  43 #define NDEBUG_NO_DATAOUT       0x200
  44 #define NDEBUG_NO_WRITE         0x400
  45 #define NDEBUG_PIO              0x800
  46 #define NDEBUG_PSEUDO_DMA       0x1000
  47 #define NDEBUG_QUEUES           0x2000
  48 #define NDEBUG_RESELECTION      0x4000
  49 #define NDEBUG_SELECTION        0x8000
  50 #define NDEBUG_USLEEP           0x10000
  51 #define NDEBUG_LAST_BYTE_SENT   0x20000
  52 #define NDEBUG_RESTART_SELECT   0x40000
  53 #define NDEBUG_EXTENDED         0x80000
  54 #define NDEBUG_C400_PREAD       0x100000
  55 #define NDEBUG_C400_PWRITE      0x200000
  56 #define NDEBUG_LISTS            0x400000
  57 #define NDEBUG_ABORT            0x800000
  58 #define NDEBUG_TAGS             0x1000000
  59 #define NDEBUG_MERGING          0x2000000
  60 
  61 #define NDEBUG_ANY              0xFFFFFFFFUL
  62 
  63 /* 
  64  * The contents of the OUTPUT DATA register are asserted on the bus when
  65  * either arbitration is occurring or the phase-indicating signals (
  66  * IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA
  67  * bit in the INITIATOR COMMAND register is set.
  68  */
  69 
  70 #define OUTPUT_DATA_REG         0       /* wo DATA lines on SCSI bus */
  71 #define CURRENT_SCSI_DATA_REG   0       /* ro same */
  72 
  73 #define INITIATOR_COMMAND_REG   1       /* rw */
  74 #define ICR_ASSERT_RST          0x80    /* rw Set to assert RST  */
  75 #define ICR_ARBITRATION_PROGRESS 0x40   /* ro Indicates arbitration complete */
  76 #define ICR_TRI_STATE           0x40    /* wo Set to tri-state drivers */
  77 #define ICR_ARBITRATION_LOST    0x20    /* ro Indicates arbitration lost */
  78 #define ICR_DIFF_ENABLE         0x20    /* wo Set to enable diff. drivers */
  79 #define ICR_ASSERT_ACK          0x10    /* rw ini Set to assert ACK */
  80 #define ICR_ASSERT_BSY          0x08    /* rw Set to assert BSY */
  81 #define ICR_ASSERT_SEL          0x04    /* rw Set to assert SEL */
  82 #define ICR_ASSERT_ATN          0x02    /* rw Set to assert ATN */
  83 #define ICR_ASSERT_DATA         0x01    /* rw SCSI_DATA_REG is asserted */
  84 
  85 #define ICR_BASE                0
  86 
  87 #define MODE_REG                2
  88 /*
  89  * Note : BLOCK_DMA code will keep DRQ asserted for the duration of the 
  90  * transfer, causing the chip to hog the bus.  You probably don't want 
  91  * this.
  92  */
  93 #define MR_BLOCK_DMA_MODE       0x80    /* rw block mode DMA */
  94 #define MR_TARGET               0x40    /* rw target mode */
  95 #define MR_ENABLE_PAR_CHECK     0x20    /* rw enable parity checking */
  96 #define MR_ENABLE_PAR_INTR      0x10    /* rw enable bad parity interrupt */
  97 #define MR_ENABLE_EOP_INTR      0x08    /* rw enable eop interrupt */
  98 #define MR_MONITOR_BSY          0x04    /* rw enable int on unexpected bsy fail */
  99 #define MR_DMA_MODE             0x02    /* rw DMA / pseudo DMA mode */
 100 #define MR_ARBITRATE            0x01    /* rw start arbitration */
 101 
 102 #define MR_BASE                 0
 103 
 104 #define TARGET_COMMAND_REG      3
 105 #define TCR_LAST_BYTE_SENT      0x80    /* ro DMA done */
 106 #define TCR_ASSERT_REQ          0x08    /* tgt rw assert REQ */
 107 #define TCR_ASSERT_MSG          0x04    /* tgt rw assert MSG */
 108 #define TCR_ASSERT_CD           0x02    /* tgt rw assert CD */
 109 #define TCR_ASSERT_IO           0x01    /* tgt rw assert IO */
 110 
 111 #define STATUS_REG              4       /* ro */
 112 /*
 113  * Note : a set bit indicates an active signal, driven by us or another 
 114  * device.
 115  */
 116 #define SR_RST                  0x80
 117 #define SR_BSY                  0x40
 118 #define SR_REQ                  0x20
 119 #define SR_MSG                  0x10
 120 #define SR_CD                   0x08
 121 #define SR_IO                   0x04
 122 #define SR_SEL                  0x02
 123 #define SR_DBP                  0x01
 124 
 125 /*
 126  * Setting a bit in this register will cause an interrupt to be generated when 
 127  * BSY is false and SEL true and this bit is asserted  on the bus.
 128  */
 129 #define SELECT_ENABLE_REG       4       /* wo */
 130 
 131 #define BUS_AND_STATUS_REG      5       /* ro */
 132 #define BASR_END_DMA_TRANSFER   0x80    /* ro set on end of transfer */
 133 #define BASR_DRQ                0x40    /* ro mirror of DRQ pin */
 134 #define BASR_PARITY_ERROR       0x20    /* ro parity error detected */
 135 #define BASR_IRQ                0x10    /* ro mirror of IRQ pin */
 136 #define BASR_PHASE_MATCH        0x08    /* ro Set when MSG CD IO match TCR */
 137 #define BASR_BUSY_ERROR         0x04    /* ro Unexpected change to inactive state */
 138 #define BASR_ATN                0x02    /* ro BUS status */
 139 #define BASR_ACK                0x01    /* ro BUS status */
 140 
 141 /* Write any value to this register to start a DMA send */
 142 #define START_DMA_SEND_REG      5       /* wo */
 143 
 144 /* 
 145  * Used in DMA transfer mode, data is latched from the SCSI bus on
 146  * the falling edge of REQ (ini) or ACK (tgt)
 147  */
 148 #define INPUT_DATA_REG                  6       /* ro */
 149 
 150 /* Write any value to this register to start a DMA receive */
 151 #define START_DMA_TARGET_RECEIVE_REG    6       /* wo */
 152 
 153 /* Read this register to clear interrupt conditions */
 154 #define RESET_PARITY_INTERRUPT_REG      7       /* ro */
 155 
 156 /* Write any value to this register to start an ini mode DMA receive */
 157 #define START_DMA_INITIATOR_RECEIVE_REG 7       /* wo */
 158 
 159 /* NCR 53C400(A) Control Status Register bits: */
 160 #define CSR_RESET              0x80     /* wo  Resets 53c400 */
 161 #define CSR_53C80_REG          0x80     /* ro  5380 registers busy */
 162 #define CSR_TRANS_DIR          0x40     /* rw  Data transfer direction */
 163 #define CSR_SCSI_BUFF_INTR     0x20     /* rw  Enable int on transfer ready */
 164 #define CSR_53C80_INTR         0x10     /* rw  Enable 53c80 interrupts */
 165 #define CSR_SHARED_INTR        0x08     /* rw  Interrupt sharing */
 166 #define CSR_HOST_BUF_NOT_RDY   0x04     /* ro  Is Host buffer ready */
 167 #define CSR_SCSI_BUF_RDY       0x02     /* ro  SCSI buffer read */
 168 #define CSR_GATED_53C80_IRQ    0x01     /* ro  Last block xferred */
 169 
 170 #define CSR_BASE CSR_53C80_INTR
 171 
 172 /* Note : PHASE_* macros are based on the values of the STATUS register */
 173 #define PHASE_MASK      (SR_MSG | SR_CD | SR_IO)
 174 
 175 #define PHASE_DATAOUT           0
 176 #define PHASE_DATAIN            SR_IO
 177 #define PHASE_CMDOUT            SR_CD
 178 #define PHASE_STATIN            (SR_CD | SR_IO)
 179 #define PHASE_MSGOUT            (SR_MSG | SR_CD)
 180 #define PHASE_MSGIN             (SR_MSG | SR_CD | SR_IO)
 181 #define PHASE_UNKNOWN           0xff
 182 
 183 /* 
 184  * Convert status register phase to something we can use to set phase in 
 185  * the target register so we can get phase mismatch interrupts on DMA 
 186  * transfers.
 187  */
 188 
 189 #define PHASE_SR_TO_TCR(phase) ((phase) >> 2)
 190 
 191 #ifndef NO_IRQ
 192 #define NO_IRQ          0
 193 #endif
 194 
 195 #define FLAG_DMA_FIXUP                  1       /* Use DMA errata workarounds */
 196 #define FLAG_NO_PSEUDO_DMA              8       /* Inhibit DMA */
 197 #define FLAG_LATE_DMA_SETUP             32      /* Setup NCR before DMA H/W */
 198 #define FLAG_TOSHIBA_DELAY              128     /* Allow for borken CD-ROMs */
 199 
 200 struct NCR5380_hostdata {
 201         NCR5380_implementation_fields;          /* Board-specific data */
 202         u8 __iomem *io;                         /* Remapped 5380 address */
 203         u8 __iomem *pdma_io;                    /* Remapped PDMA address */
 204         unsigned long poll_loops;               /* Register polling limit */
 205         spinlock_t lock;                        /* Protects this struct */
 206         struct scsi_cmnd *connected;            /* Currently connected cmnd */
 207         struct list_head disconnected;          /* Waiting for reconnect */
 208         struct Scsi_Host *host;                 /* SCSI host backpointer */
 209         struct workqueue_struct *work_q;        /* SCSI host work queue */
 210         struct work_struct main_task;           /* Work item for main loop */
 211         int flags;                              /* Board-specific quirks */
 212         int dma_len;                            /* Requested length of DMA */
 213         int read_overruns;      /* Transfer size reduction for DMA erratum */
 214         unsigned long io_port;                  /* Device IO port */
 215         unsigned long base;                     /* Device base address */
 216         struct list_head unissued;              /* Waiting to be issued */
 217         struct scsi_cmnd *selecting;            /* Cmnd to be connected */
 218         struct list_head autosense;             /* Priority cmnd queue */
 219         struct scsi_cmnd *sensing;              /* Cmnd needing autosense */
 220         struct scsi_eh_save ses;                /* Cmnd state saved for EH */
 221         unsigned char busy[8];                  /* Index = target, bit = lun */
 222         unsigned char id_mask;                  /* 1 << Host ID */
 223         unsigned char id_higher_mask;           /* All bits above id_mask */
 224         unsigned char last_message;             /* Last Message Out */
 225         unsigned long region_size;              /* Size of address/port range */
 226         char info[168];                         /* Host banner message */
 227 };
 228 
 229 struct NCR5380_cmd {
 230         struct list_head list;
 231 };
 232 
 233 #define NCR5380_CMD_SIZE                (sizeof(struct NCR5380_cmd))
 234 
 235 #define NCR5380_PIO_CHUNK_SIZE          256
 236 
 237 /* Time limit (ms) to poll registers when IRQs are disabled, e.g. during PDMA */
 238 #define NCR5380_REG_POLL_TIME           10
 239 
 240 static inline struct scsi_cmnd *NCR5380_to_scmd(struct NCR5380_cmd *ncmd_ptr)
 241 {
 242         return ((struct scsi_cmnd *)ncmd_ptr) - 1;
 243 }
 244 
 245 #ifndef NDEBUG
 246 #define NDEBUG (0)
 247 #endif
 248 
 249 #define dprintk(flg, fmt, ...) \
 250         do { if ((NDEBUG) & (flg)) \
 251                 printk(KERN_DEBUG fmt, ## __VA_ARGS__); } while (0)
 252 
 253 #define dsprintk(flg, host, fmt, ...) \
 254         do { if ((NDEBUG) & (flg)) \
 255                 shost_printk(KERN_DEBUG, host, fmt, ## __VA_ARGS__); \
 256         } while (0)
 257 
 258 #if NDEBUG
 259 #define NCR5380_dprint(flg, arg) \
 260         do { if ((NDEBUG) & (flg)) NCR5380_print(arg); } while (0)
 261 #define NCR5380_dprint_phase(flg, arg) \
 262         do { if ((NDEBUG) & (flg)) NCR5380_print_phase(arg); } while (0)
 263 static void NCR5380_print_phase(struct Scsi_Host *instance);
 264 static void NCR5380_print(struct Scsi_Host *instance);
 265 #else
 266 #define NCR5380_dprint(flg, arg)       do {} while (0)
 267 #define NCR5380_dprint_phase(flg, arg) do {} while (0)
 268 #endif
 269 
 270 static int NCR5380_init(struct Scsi_Host *instance, int flags);
 271 static int NCR5380_maybe_reset_bus(struct Scsi_Host *);
 272 static void NCR5380_exit(struct Scsi_Host *instance);
 273 static void NCR5380_information_transfer(struct Scsi_Host *instance);
 274 static irqreturn_t NCR5380_intr(int irq, void *dev_id);
 275 static void NCR5380_main(struct work_struct *work);
 276 static const char *NCR5380_info(struct Scsi_Host *instance);
 277 static void NCR5380_reselect(struct Scsi_Host *instance);
 278 static bool NCR5380_select(struct Scsi_Host *, struct scsi_cmnd *);
 279 static int NCR5380_transfer_dma(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);
 280 static int NCR5380_transfer_pio(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);
 281 static int NCR5380_poll_politely2(struct NCR5380_hostdata *,
 282                                   unsigned int, u8, u8,
 283                                   unsigned int, u8, u8, unsigned long);
 284 
 285 static inline int NCR5380_poll_politely(struct NCR5380_hostdata *hostdata,
 286                                         unsigned int reg, u8 bit, u8 val,
 287                                         unsigned long wait)
 288 {
 289         if ((NCR5380_read(reg) & bit) == val)
 290                 return 0;
 291 
 292         return NCR5380_poll_politely2(hostdata, reg, bit, val,
 293                                                 reg, bit, val, wait);
 294 }
 295 
 296 static int NCR5380_dma_xfer_len(struct NCR5380_hostdata *,
 297                                 struct scsi_cmnd *);
 298 static int NCR5380_dma_send_setup(struct NCR5380_hostdata *,
 299                                   unsigned char *, int);
 300 static int NCR5380_dma_recv_setup(struct NCR5380_hostdata *,
 301                                   unsigned char *, int);
 302 static int NCR5380_dma_residual(struct NCR5380_hostdata *);
 303 
 304 static inline int NCR5380_dma_xfer_none(struct NCR5380_hostdata *hostdata,
 305                                         struct scsi_cmnd *cmd)
 306 {
 307         return 0;
 308 }
 309 
 310 static inline int NCR5380_dma_setup_none(struct NCR5380_hostdata *hostdata,
 311                                          unsigned char *data, int count)
 312 {
 313         return 0;
 314 }
 315 
 316 static inline int NCR5380_dma_residual_none(struct NCR5380_hostdata *hostdata)
 317 {
 318         return 0;
 319 }
 320 
 321 #endif                          /* NCR5380_H */