This source file includes following definitions.
- hisi_sas_read32
- hisi_sas_read32_relaxed
- hisi_sas_write32
- hisi_sas_phy_write32
- hisi_sas_phy_read32
- slot_index_alloc_quirk_v2_hw
- sata_index_alloc_v2_hw
- alloc_dev_quirk_v2_hw
- config_phy_opt_mode_v2_hw
- config_id_frame_v2_hw
- setup_itct_v2_hw
- clear_itct_v2_hw
- free_device_v2_hw
- reset_hw_v2_hw
- phys_reject_stp_links_v2_hw
- phys_try_accept_stp_links_v2_hw
- init_reg_v2_hw
- link_timeout_enable_link
- link_timeout_disable_link
- set_link_timer_quirk
- hw_init_v2_hw
- enable_phy_v2_hw
- is_sata_phy_v2_hw
- tx_fifo_is_empty_v2_hw
- axi_bus_is_idle_v2_hw
- wait_io_done_v2_hw
- allowed_disable_phy_v2_hw
- disable_phy_v2_hw
- start_phy_v2_hw
- phy_hard_reset_v2_hw
- phy_get_events_v2_hw
- phys_init_v2_hw
- sl_notify_ssp_v2_hw
- phy_get_max_linkrate_v2_hw
- phy_set_linkrate_v2_hw
- get_wideport_bitmap_v2_hw
- start_delivery_v2_hw
- prep_prd_sge_v2_hw
- prep_smp_v2_hw
- prep_ssp_v2_hw
- parse_trans_tx_err_code_v2_hw
- parse_trans_rx_err_code_v2_hw
- parse_dma_tx_err_code_v2_hw
- parse_sipc_rx_err_code_v2_hw
- parse_dma_rx_err_code_v2_hw
- slot_err_v2_hw
- slot_complete_v2_hw
- prep_ata_v2_hw
- hisi_sas_internal_abort_quirk_timeout
- prep_abort_v2_hw
- phy_up_v2_hw
- check_any_wideports_v2_hw
- phy_down_v2_hw
- int_phy_updown_v2_hw
- phy_bcast_v2_hw
- int_chnl_int_v2_hw
- one_bit_ecc_error_process_v2_hw
- multi_bit_ecc_error_process_v2_hw
- fatal_ecc_int_v2_hw
- fatal_axi_int_v2_hw
- cq_tasklet_v2_hw
- cq_interrupt_v2_hw
- sata_int_v2_hw
- interrupt_init_v2_hw
- hisi_sas_v2_init
- interrupt_disable_v2_hw
- get_phys_state_v2_hw
- soft_reset_v2_hw
- write_gpio_v2_hw
- wait_cmds_complete_timeout_v2_hw
- hisi_sas_v2_probe
- hisi_sas_v2_remove
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6
7 #include "hisi_sas.h"
8 #define DRV_NAME "hisi_sas_v2_hw"
9
10
11 #define DLVRY_QUEUE_ENABLE 0x0
12 #define IOST_BASE_ADDR_LO 0x8
13 #define IOST_BASE_ADDR_HI 0xc
14 #define ITCT_BASE_ADDR_LO 0x10
15 #define ITCT_BASE_ADDR_HI 0x14
16 #define IO_BROKEN_MSG_ADDR_LO 0x18
17 #define IO_BROKEN_MSG_ADDR_HI 0x1c
18 #define PHY_CONTEXT 0x20
19 #define PHY_STATE 0x24
20 #define PHY_PORT_NUM_MA 0x28
21 #define PORT_STATE 0x2c
22 #define PORT_STATE_PHY8_PORT_NUM_OFF 16
23 #define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
24 #define PORT_STATE_PHY8_CONN_RATE_OFF 20
25 #define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
26 #define PHY_CONN_RATE 0x30
27 #define HGC_TRANS_TASK_CNT_LIMIT 0x38
28 #define AXI_AHB_CLK_CFG 0x3c
29 #define ITCT_CLR 0x44
30 #define ITCT_CLR_EN_OFF 16
31 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
32 #define ITCT_DEV_OFF 0
33 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
34 #define AXI_USER1 0x48
35 #define AXI_USER2 0x4c
36 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
37 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
38 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
39 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
40 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
41 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
42 #define HGC_GET_ITV_TIME 0x90
43 #define DEVICE_MSG_WORK_MODE 0x94
44 #define OPENA_WT_CONTI_TIME 0x9c
45 #define I_T_NEXUS_LOSS_TIME 0xa0
46 #define MAX_CON_TIME_LIMIT_TIME 0xa4
47 #define BUS_INACTIVE_LIMIT_TIME 0xa8
48 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
49 #define CFG_AGING_TIME 0xbc
50 #define HGC_DFX_CFG2 0xc0
51 #define HGC_IOMB_PROC1_STATUS 0x104
52 #define CFG_1US_TIMER_TRSH 0xcc
53 #define HGC_LM_DFX_STATUS2 0x128
54 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0
55 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \
56 HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
57 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12
58 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \
59 HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
60 #define HGC_CQE_ECC_ADDR 0x13c
61 #define HGC_CQE_ECC_1B_ADDR_OFF 0
62 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
63 #define HGC_CQE_ECC_MB_ADDR_OFF 8
64 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
65 #define HGC_IOST_ECC_ADDR 0x140
66 #define HGC_IOST_ECC_1B_ADDR_OFF 0
67 #define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
68 #define HGC_IOST_ECC_MB_ADDR_OFF 16
69 #define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
70 #define HGC_DQE_ECC_ADDR 0x144
71 #define HGC_DQE_ECC_1B_ADDR_OFF 0
72 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
73 #define HGC_DQE_ECC_MB_ADDR_OFF 16
74 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
75 #define HGC_INVLD_DQE_INFO 0x148
76 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9
77 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
78 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18
79 #define HGC_ITCT_ECC_ADDR 0x150
80 #define HGC_ITCT_ECC_1B_ADDR_OFF 0
81 #define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \
82 HGC_ITCT_ECC_1B_ADDR_OFF)
83 #define HGC_ITCT_ECC_MB_ADDR_OFF 16
84 #define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \
85 HGC_ITCT_ECC_MB_ADDR_OFF)
86 #define HGC_AXI_FIFO_ERR_INFO 0x154
87 #define AXI_ERR_INFO_OFF 0
88 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF)
89 #define FIFO_ERR_INFO_OFF 8
90 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF)
91 #define INT_COAL_EN 0x19c
92 #define OQ_INT_COAL_TIME 0x1a0
93 #define OQ_INT_COAL_CNT 0x1a4
94 #define ENT_INT_COAL_TIME 0x1a8
95 #define ENT_INT_COAL_CNT 0x1ac
96 #define OQ_INT_SRC 0x1b0
97 #define OQ_INT_SRC_MSK 0x1b4
98 #define ENT_INT_SRC1 0x1b8
99 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
100 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
101 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
102 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
103 #define ENT_INT_SRC2 0x1bc
104 #define ENT_INT_SRC3 0x1c0
105 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
106 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
107 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
108 #define ENT_INT_SRC3_AXI_OFF 11
109 #define ENT_INT_SRC3_FIFO_OFF 12
110 #define ENT_INT_SRC3_LM_OFF 14
111 #define ENT_INT_SRC3_ITC_INT_OFF 15
112 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
113 #define ENT_INT_SRC3_ABT_OFF 16
114 #define ENT_INT_SRC_MSK1 0x1c4
115 #define ENT_INT_SRC_MSK2 0x1c8
116 #define ENT_INT_SRC_MSK3 0x1cc
117 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
118 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
119 #define SAS_ECC_INTR 0x1e8
120 #define SAS_ECC_INTR_DQE_ECC_1B_OFF 0
121 #define SAS_ECC_INTR_DQE_ECC_MB_OFF 1
122 #define SAS_ECC_INTR_IOST_ECC_1B_OFF 2
123 #define SAS_ECC_INTR_IOST_ECC_MB_OFF 3
124 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF 4
125 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF 5
126 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 6
127 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 7
128 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 8
129 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 9
130 #define SAS_ECC_INTR_CQE_ECC_1B_OFF 10
131 #define SAS_ECC_INTR_CQE_ECC_MB_OFF 11
132 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 12
133 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 13
134 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 14
135 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 15
136 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 16
137 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 17
138 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 18
139 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 19
140 #define SAS_ECC_INTR_MSK 0x1ec
141 #define HGC_ERR_STAT_EN 0x238
142 #define CQE_SEND_CNT 0x248
143 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
144 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
145 #define DLVRY_Q_0_DEPTH 0x268
146 #define DLVRY_Q_0_WR_PTR 0x26c
147 #define DLVRY_Q_0_RD_PTR 0x270
148 #define HYPER_STREAM_ID_EN_CFG 0xc80
149 #define OQ0_INT_SRC_MSK 0xc90
150 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
151 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
152 #define COMPL_Q_0_DEPTH 0x4e8
153 #define COMPL_Q_0_WR_PTR 0x4ec
154 #define COMPL_Q_0_RD_PTR 0x4f0
155 #define HGC_RXM_DFX_STATUS14 0xae8
156 #define HGC_RXM_DFX_STATUS14_MEM0_OFF 0
157 #define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \
158 HGC_RXM_DFX_STATUS14_MEM0_OFF)
159 #define HGC_RXM_DFX_STATUS14_MEM1_OFF 9
160 #define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \
161 HGC_RXM_DFX_STATUS14_MEM1_OFF)
162 #define HGC_RXM_DFX_STATUS14_MEM2_OFF 18
163 #define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \
164 HGC_RXM_DFX_STATUS14_MEM2_OFF)
165 #define HGC_RXM_DFX_STATUS15 0xaec
166 #define HGC_RXM_DFX_STATUS15_MEM3_OFF 0
167 #define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \
168 HGC_RXM_DFX_STATUS15_MEM3_OFF)
169
170 #define PORT_BASE (0x2000)
171
172 #define PHY_CFG (PORT_BASE + 0x0)
173 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
174 #define PHY_CFG_ENA_OFF 0
175 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
176 #define PHY_CFG_DC_OPT_OFF 2
177 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
178 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
179 #define PROG_PHY_LINK_RATE_MAX_OFF 0
180 #define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
181 #define PHY_CTRL (PORT_BASE + 0x14)
182 #define PHY_CTRL_RESET_OFF 0
183 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
184 #define SAS_PHY_CTRL (PORT_BASE + 0x20)
185 #define SL_CFG (PORT_BASE + 0x84)
186 #define PHY_PCN (PORT_BASE + 0x44)
187 #define SL_TOUT_CFG (PORT_BASE + 0x8c)
188 #define SL_CONTROL (PORT_BASE + 0x94)
189 #define SL_CONTROL_NOTIFY_EN_OFF 0
190 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
191 #define SL_CONTROL_CTA_OFF 17
192 #define SL_CONTROL_CTA_MSK (0x1 << SL_CONTROL_CTA_OFF)
193 #define RX_PRIMS_STATUS (PORT_BASE + 0x98)
194 #define RX_BCAST_CHG_OFF 1
195 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF)
196 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
197 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
198 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
199 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
200 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
201 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
202 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
203 #define TXID_AUTO (PORT_BASE + 0xb8)
204 #define TXID_AUTO_CT3_OFF 1
205 #define TXID_AUTO_CT3_MSK (0x1 << TXID_AUTO_CT3_OFF)
206 #define TXID_AUTO_CTB_OFF 11
207 #define TXID_AUTO_CTB_MSK (0x1 << TXID_AUTO_CTB_OFF)
208 #define TX_HARDRST_OFF 2
209 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
210 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
211 #define RX_IDAF_DWORD1 (PORT_BASE + 0xc8)
212 #define RX_IDAF_DWORD2 (PORT_BASE + 0xcc)
213 #define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
214 #define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
215 #define RX_IDAF_DWORD5 (PORT_BASE + 0xd8)
216 #define RX_IDAF_DWORD6 (PORT_BASE + 0xdc)
217 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
218 #define CON_CONTROL (PORT_BASE + 0x118)
219 #define CON_CONTROL_CFG_OPEN_ACC_STP_OFF 0
220 #define CON_CONTROL_CFG_OPEN_ACC_STP_MSK \
221 (0x01 << CON_CONTROL_CFG_OPEN_ACC_STP_OFF)
222 #define DONE_RECEIVED_TIME (PORT_BASE + 0x11c)
223 #define CHL_INT0 (PORT_BASE + 0x1b4)
224 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
225 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
226 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
227 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
228 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
229 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
230 #define CHL_INT0_NOT_RDY_OFF 4
231 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
232 #define CHL_INT0_PHY_RDY_OFF 5
233 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
234 #define CHL_INT1 (PORT_BASE + 0x1b8)
235 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
236 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
237 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
238 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
239 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19
240 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20
241 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21
242 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22
243 #define CHL_INT2 (PORT_BASE + 0x1bc)
244 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0
245 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
246 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
247 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
248 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
249 #define DMA_TX_DFX0 (PORT_BASE + 0x200)
250 #define DMA_TX_DFX1 (PORT_BASE + 0x204)
251 #define DMA_TX_DFX1_IPTT_OFF 0
252 #define DMA_TX_DFX1_IPTT_MSK (0xffff << DMA_TX_DFX1_IPTT_OFF)
253 #define DMA_TX_FIFO_DFX0 (PORT_BASE + 0x240)
254 #define PORT_DFX0 (PORT_BASE + 0x258)
255 #define LINK_DFX2 (PORT_BASE + 0X264)
256 #define LINK_DFX2_RCVR_HOLD_STS_OFF 9
257 #define LINK_DFX2_RCVR_HOLD_STS_MSK (0x1 << LINK_DFX2_RCVR_HOLD_STS_OFF)
258 #define LINK_DFX2_SEND_HOLD_STS_OFF 10
259 #define LINK_DFX2_SEND_HOLD_STS_MSK (0x1 << LINK_DFX2_SEND_HOLD_STS_OFF)
260 #define SAS_ERR_CNT4_REG (PORT_BASE + 0x290)
261 #define SAS_ERR_CNT6_REG (PORT_BASE + 0x298)
262 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
263 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
264 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
265 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
266 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
267 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
268 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
269 #define DMA_TX_STATUS_BUSY_OFF 0
270 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
271 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
272 #define DMA_RX_STATUS_BUSY_OFF 0
273 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
274
275 #define AXI_CFG (0x5100)
276 #define AM_CFG_MAX_TRANS (0x5010)
277 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
278
279 #define AXI_MASTER_CFG_BASE (0x5000)
280 #define AM_CTRL_GLOBAL (0x0)
281 #define AM_CURR_TRANS_RETURN (0x150)
282
283
284
285
286 #define CMD_HDR_ABORT_FLAG_OFF 0
287 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
288 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
289 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
290 #define CMD_HDR_RESP_REPORT_OFF 5
291 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
292 #define CMD_HDR_TLR_CTRL_OFF 6
293 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
294 #define CMD_HDR_PHY_ID_OFF 8
295 #define CMD_HDR_PHY_ID_MSK (0x1ff << CMD_HDR_PHY_ID_OFF)
296 #define CMD_HDR_FORCE_PHY_OFF 17
297 #define CMD_HDR_FORCE_PHY_MSK (0x1 << CMD_HDR_FORCE_PHY_OFF)
298 #define CMD_HDR_PORT_OFF 18
299 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
300 #define CMD_HDR_PRIORITY_OFF 27
301 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
302 #define CMD_HDR_CMD_OFF 29
303 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
304
305 #define CMD_HDR_DIR_OFF 5
306 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
307 #define CMD_HDR_RESET_OFF 7
308 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
309 #define CMD_HDR_VDTL_OFF 10
310 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
311 #define CMD_HDR_FRAME_TYPE_OFF 11
312 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
313 #define CMD_HDR_DEV_ID_OFF 16
314 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
315
316 #define CMD_HDR_CFL_OFF 0
317 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
318 #define CMD_HDR_NCQ_TAG_OFF 10
319 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
320 #define CMD_HDR_MRFL_OFF 15
321 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
322 #define CMD_HDR_SG_MOD_OFF 24
323 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
324 #define CMD_HDR_FIRST_BURST_OFF 26
325 #define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF)
326
327 #define CMD_HDR_IPTT_OFF 0
328 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
329
330 #define CMD_HDR_DIF_SGL_LEN_OFF 0
331 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
332 #define CMD_HDR_DATA_SGL_LEN_OFF 16
333 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
334 #define CMD_HDR_ABORT_IPTT_OFF 16
335 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
336
337
338
339 #define CMPLT_HDR_ERR_PHASE_OFF 2
340 #define CMPLT_HDR_ERR_PHASE_MSK (0xff << CMPLT_HDR_ERR_PHASE_OFF)
341 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
342 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
343 #define CMPLT_HDR_ERX_OFF 12
344 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
345 #define CMPLT_HDR_ABORT_STAT_OFF 13
346 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
347
348 #define STAT_IO_NOT_VALID 0x1
349 #define STAT_IO_NO_DEVICE 0x2
350 #define STAT_IO_COMPLETE 0x3
351 #define STAT_IO_ABORTED 0x4
352
353 #define CMPLT_HDR_IPTT_OFF 0
354 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
355 #define CMPLT_HDR_DEV_ID_OFF 16
356 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
357
358
359
360 #define ITCT_HDR_DEV_TYPE_OFF 0
361 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
362 #define ITCT_HDR_VALID_OFF 2
363 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
364 #define ITCT_HDR_MCR_OFF 5
365 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
366 #define ITCT_HDR_VLN_OFF 9
367 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
368 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
369 #define ITCT_HDR_SMP_TIMEOUT_8US 1
370 #define ITCT_HDR_SMP_TIMEOUT (ITCT_HDR_SMP_TIMEOUT_8US * \
371 250)
372 #define ITCT_HDR_AWT_CONTINUE_OFF 25
373 #define ITCT_HDR_PORT_ID_OFF 28
374 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
375
376 #define ITCT_HDR_INLT_OFF 0
377 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
378 #define ITCT_HDR_BITLT_OFF 16
379 #define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF)
380 #define ITCT_HDR_MCTLT_OFF 32
381 #define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF)
382 #define ITCT_HDR_RTOLT_OFF 48
383 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
384
385 #define HISI_SAS_FATAL_INT_NR 2
386
387 struct hisi_sas_complete_v2_hdr {
388 __le32 dw0;
389 __le32 dw1;
390 __le32 act;
391 __le32 dw3;
392 };
393
394 struct hisi_sas_err_record_v2 {
395
396 __le32 trans_tx_fail_type;
397
398
399 __le32 trans_rx_fail_type;
400
401
402 __le16 dma_tx_err_type;
403 __le16 sipc_rx_err_type;
404
405
406 __le32 dma_rx_err_type;
407 };
408
409 struct signal_attenuation_s {
410 u32 de_emphasis;
411 u32 preshoot;
412 u32 boost;
413 };
414
415 struct sig_atten_lu_s {
416 const struct signal_attenuation_s *att;
417 u32 sas_phy_ctrl;
418 };
419
420 static const struct hisi_sas_hw_error one_bit_ecc_errors[] = {
421 {
422 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF),
423 .msk = HGC_DQE_ECC_1B_ADDR_MSK,
424 .shift = HGC_DQE_ECC_1B_ADDR_OFF,
425 .msg = "hgc_dqe_ecc1b_intr",
426 .reg = HGC_DQE_ECC_ADDR,
427 },
428 {
429 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF),
430 .msk = HGC_IOST_ECC_1B_ADDR_MSK,
431 .shift = HGC_IOST_ECC_1B_ADDR_OFF,
432 .msg = "hgc_iost_ecc1b_intr",
433 .reg = HGC_IOST_ECC_ADDR,
434 },
435 {
436 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF),
437 .msk = HGC_ITCT_ECC_1B_ADDR_MSK,
438 .shift = HGC_ITCT_ECC_1B_ADDR_OFF,
439 .msg = "hgc_itct_ecc1b_intr",
440 .reg = HGC_ITCT_ECC_ADDR,
441 },
442 {
443 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF),
444 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
445 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
446 .msg = "hgc_iostl_ecc1b_intr",
447 .reg = HGC_LM_DFX_STATUS2,
448 },
449 {
450 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF),
451 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
452 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
453 .msg = "hgc_itctl_ecc1b_intr",
454 .reg = HGC_LM_DFX_STATUS2,
455 },
456 {
457 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF),
458 .msk = HGC_CQE_ECC_1B_ADDR_MSK,
459 .shift = HGC_CQE_ECC_1B_ADDR_OFF,
460 .msg = "hgc_cqe_ecc1b_intr",
461 .reg = HGC_CQE_ECC_ADDR,
462 },
463 {
464 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF),
465 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
466 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
467 .msg = "rxm_mem0_ecc1b_intr",
468 .reg = HGC_RXM_DFX_STATUS14,
469 },
470 {
471 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF),
472 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
473 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
474 .msg = "rxm_mem1_ecc1b_intr",
475 .reg = HGC_RXM_DFX_STATUS14,
476 },
477 {
478 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF),
479 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
480 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
481 .msg = "rxm_mem2_ecc1b_intr",
482 .reg = HGC_RXM_DFX_STATUS14,
483 },
484 {
485 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF),
486 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
487 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
488 .msg = "rxm_mem3_ecc1b_intr",
489 .reg = HGC_RXM_DFX_STATUS15,
490 },
491 };
492
493 static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
494 {
495 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
496 .msk = HGC_DQE_ECC_MB_ADDR_MSK,
497 .shift = HGC_DQE_ECC_MB_ADDR_OFF,
498 .msg = "hgc_dqe_eccbad_intr",
499 .reg = HGC_DQE_ECC_ADDR,
500 },
501 {
502 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
503 .msk = HGC_IOST_ECC_MB_ADDR_MSK,
504 .shift = HGC_IOST_ECC_MB_ADDR_OFF,
505 .msg = "hgc_iost_eccbad_intr",
506 .reg = HGC_IOST_ECC_ADDR,
507 },
508 {
509 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
510 .msk = HGC_ITCT_ECC_MB_ADDR_MSK,
511 .shift = HGC_ITCT_ECC_MB_ADDR_OFF,
512 .msg = "hgc_itct_eccbad_intr",
513 .reg = HGC_ITCT_ECC_ADDR,
514 },
515 {
516 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
517 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
518 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
519 .msg = "hgc_iostl_eccbad_intr",
520 .reg = HGC_LM_DFX_STATUS2,
521 },
522 {
523 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
524 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
525 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
526 .msg = "hgc_itctl_eccbad_intr",
527 .reg = HGC_LM_DFX_STATUS2,
528 },
529 {
530 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
531 .msk = HGC_CQE_ECC_MB_ADDR_MSK,
532 .shift = HGC_CQE_ECC_MB_ADDR_OFF,
533 .msg = "hgc_cqe_eccbad_intr",
534 .reg = HGC_CQE_ECC_ADDR,
535 },
536 {
537 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
538 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
539 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
540 .msg = "rxm_mem0_eccbad_intr",
541 .reg = HGC_RXM_DFX_STATUS14,
542 },
543 {
544 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
545 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
546 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
547 .msg = "rxm_mem1_eccbad_intr",
548 .reg = HGC_RXM_DFX_STATUS14,
549 },
550 {
551 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
552 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
553 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
554 .msg = "rxm_mem2_eccbad_intr",
555 .reg = HGC_RXM_DFX_STATUS14,
556 },
557 {
558 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
559 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
560 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
561 .msg = "rxm_mem3_eccbad_intr",
562 .reg = HGC_RXM_DFX_STATUS15,
563 },
564 };
565
566 enum {
567 HISI_SAS_PHY_PHY_UPDOWN,
568 HISI_SAS_PHY_CHNL_INT,
569 HISI_SAS_PHY_INT_NR
570 };
571
572 enum {
573 TRANS_TX_FAIL_BASE = 0x0,
574 TRANS_RX_FAIL_BASE = 0x20,
575 DMA_TX_ERR_BASE = 0x40,
576 SIPC_RX_ERR_BASE = 0x50,
577 DMA_RX_ERR_BASE = 0x60,
578
579
580 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = TRANS_TX_FAIL_BASE,
581 TRANS_TX_ERR_PHY_NOT_ENABLE,
582 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION,
583 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION,
584 TRANS_TX_OPEN_CNX_ERR_BY_OTHER,
585 RESERVED0,
586 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT,
587 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY,
588 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED,
589 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED,
590 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION,
591 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD,
592 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER,
593 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED,
594 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT,
595 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION,
596 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED,
597 TRANS_TX_ERR_FRAME_TXED,
598 TRANS_TX_ERR_WITH_BREAK_TIMEOUT,
599 TRANS_TX_ERR_WITH_BREAK_REQUEST,
600 TRANS_TX_ERR_WITH_BREAK_RECEVIED,
601 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT,
602 TRANS_TX_ERR_WITH_CLOSE_NORMAL,
603 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE,
604 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT,
605 TRANS_TX_ERR_WITH_CLOSE_COMINIT,
606 TRANS_TX_ERR_WITH_NAK_RECEVIED,
607 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT,
608
609 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT,
610
611 TRANS_TX_ERR_WITH_IPTT_CONFLICT,
612 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS,
613
614 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT,
615
616
617 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = TRANS_RX_FAIL_BASE,
618 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR,
619 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM,
620
621 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR,
622 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR,
623 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN,
624
625 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP,
626 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN,
627 TRANS_RX_ERR_WITH_BREAK_TIMEOUT,
628 TRANS_RX_ERR_WITH_BREAK_REQUEST,
629 TRANS_RX_ERR_WITH_BREAK_RECEVIED,
630 RESERVED1,
631 TRANS_RX_ERR_WITH_CLOSE_NORMAL,
632 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE,
633 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT,
634 TRANS_RX_ERR_WITH_CLOSE_COMINIT,
635 TRANS_RX_ERR_WITH_DATA_LEN0,
636 TRANS_RX_ERR_WITH_BAD_HASH,
637
638 TRANS_RX_XRDY_WLEN_ZERO_ERR,
639
640 TRANS_RX_SSP_FRM_LEN_ERR,
641
642 RESERVED2,
643 RESERVED3,
644 RESERVED4,
645 RESERVED5,
646 TRANS_RX_ERR_WITH_BAD_FRM_TYPE,
647 TRANS_RX_SMP_FRM_LEN_ERR,
648 TRANS_RX_SMP_RESP_TIMEOUT_ERR,
649 RESERVED6,
650 RESERVED7,
651 RESERVED8,
652 RESERVED9,
653 TRANS_RX_R_ERR,
654
655
656 DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE,
657 DMA_TX_DIF_APP_ERR,
658 DMA_TX_DIF_RPP_ERR,
659 DMA_TX_DATA_SGL_OVERFLOW,
660 DMA_TX_DIF_SGL_OVERFLOW,
661 DMA_TX_UNEXP_XFER_ERR,
662 DMA_TX_UNEXP_RETRANS_ERR,
663 DMA_TX_XFER_LEN_OVERFLOW,
664 DMA_TX_XFER_OFFSET_ERR,
665 DMA_TX_RAM_ECC_ERR,
666 DMA_TX_DIF_LEN_ALIGN_ERR,
667 DMA_TX_MAX_ERR_CODE,
668
669
670 SIPC_RX_FIS_STATUS_ERR_BIT_VLD = SIPC_RX_ERR_BASE,
671 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR,
672 SIPC_RX_FIS_STATUS_BSY_BIT_ERR,
673 SIPC_RX_WRSETUP_LEN_ODD_ERR,
674 SIPC_RX_WRSETUP_LEN_ZERO_ERR,
675 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR,
676 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR,
677 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR,
678 SIPC_RX_SATA_UNEXP_FIS_ERR,
679 SIPC_RX_WRSETUP_ESTATUS_ERR,
680 SIPC_RX_DATA_UNDERFLOW_ERR,
681 SIPC_RX_MAX_ERR_CODE,
682
683
684 DMA_RX_DIF_CRC_ERR = DMA_RX_ERR_BASE,
685 DMA_RX_DIF_APP_ERR,
686 DMA_RX_DIF_RPP_ERR,
687 DMA_RX_DATA_SGL_OVERFLOW,
688 DMA_RX_DIF_SGL_OVERFLOW,
689 DMA_RX_DATA_LEN_OVERFLOW,
690 DMA_RX_DATA_LEN_UNDERFLOW,
691 DMA_RX_DATA_OFFSET_ERR,
692 RESERVED10,
693 DMA_RX_SATA_FRAME_TYPE_ERR,
694 DMA_RX_RESP_BUF_OVERFLOW,
695 DMA_RX_UNEXP_RETRANS_RESP_ERR,
696 DMA_RX_UNEXP_NORM_RESP_ERR,
697 DMA_RX_UNEXP_RDFRAME_ERR,
698 DMA_RX_PIO_DATA_LEN_ERR,
699 DMA_RX_RDSETUP_STATUS_ERR,
700 DMA_RX_RDSETUP_STATUS_DRQ_ERR,
701 DMA_RX_RDSETUP_STATUS_BSY_ERR,
702 DMA_RX_RDSETUP_LEN_ODD_ERR,
703 DMA_RX_RDSETUP_LEN_ZERO_ERR,
704 DMA_RX_RDSETUP_LEN_OVER_ERR,
705 DMA_RX_RDSETUP_OFFSET_ERR,
706 DMA_RX_RDSETUP_ACTIVE_ERR,
707 DMA_RX_RDSETUP_ESTATUS_ERR,
708 DMA_RX_RAM_ECC_ERR,
709 DMA_RX_UNKNOWN_FRM_ERR,
710 DMA_RX_MAX_ERR_CODE,
711 };
712
713 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
714 #define HISI_MAX_SATA_SUPPORT_V2_HW (HISI_SAS_COMMAND_ENTRIES_V2_HW/64 - 1)
715
716 #define DIR_NO_DATA 0
717 #define DIR_TO_INI 1
718 #define DIR_TO_DEVICE 2
719 #define DIR_RESERVED 3
720
721 #define ERR_ON_TX_PHASE(err_phase) (err_phase == 0x2 || \
722 err_phase == 0x4 || err_phase == 0x8 ||\
723 err_phase == 0x6 || err_phase == 0xa)
724 #define ERR_ON_RX_PHASE(err_phase) (err_phase == 0x10 || \
725 err_phase == 0x20 || err_phase == 0x40)
726
727 static void link_timeout_disable_link(struct timer_list *t);
728
729 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
730 {
731 void __iomem *regs = hisi_hba->regs + off;
732
733 return readl(regs);
734 }
735
736 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
737 {
738 void __iomem *regs = hisi_hba->regs + off;
739
740 return readl_relaxed(regs);
741 }
742
743 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
744 {
745 void __iomem *regs = hisi_hba->regs + off;
746
747 writel(val, regs);
748 }
749
750 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
751 u32 off, u32 val)
752 {
753 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
754
755 writel(val, regs);
756 }
757
758 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
759 int phy_no, u32 off)
760 {
761 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
762
763 return readl(regs);
764 }
765
766
767 static int
768 slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba,
769 struct domain_device *device)
770 {
771 int sata_dev = dev_is_sata(device);
772 void *bitmap = hisi_hba->slot_index_tags;
773 struct hisi_sas_device *sas_dev = device->lldd_dev;
774 int sata_idx = sas_dev->sata_idx;
775 int start, end;
776 unsigned long flags;
777
778 if (!sata_dev) {
779
780
781
782
783
784 start = 1;
785 end = hisi_hba->slot_index_count;
786 } else {
787 if (sata_idx >= HISI_MAX_SATA_SUPPORT_V2_HW)
788 return -EINVAL;
789
790
791
792
793
794
795
796 start = 64 * (sata_idx + 1);
797 end = 64 * (sata_idx + 2);
798 }
799
800 spin_lock_irqsave(&hisi_hba->lock, flags);
801 while (1) {
802 start = find_next_zero_bit(bitmap,
803 hisi_hba->slot_index_count, start);
804 if (start >= end) {
805 spin_unlock_irqrestore(&hisi_hba->lock, flags);
806 return -SAS_QUEUE_FULL;
807 }
808
809
810
811 if (sata_dev ^ (start & 1))
812 break;
813 start++;
814 }
815
816 set_bit(start, bitmap);
817 spin_unlock_irqrestore(&hisi_hba->lock, flags);
818 return start;
819 }
820
821 static bool sata_index_alloc_v2_hw(struct hisi_hba *hisi_hba, int *idx)
822 {
823 unsigned int index;
824 struct device *dev = hisi_hba->dev;
825 void *bitmap = hisi_hba->sata_dev_bitmap;
826
827 index = find_first_zero_bit(bitmap, HISI_MAX_SATA_SUPPORT_V2_HW);
828 if (index >= HISI_MAX_SATA_SUPPORT_V2_HW) {
829 dev_warn(dev, "alloc sata index failed, index=%d\n", index);
830 return false;
831 }
832
833 set_bit(index, bitmap);
834 *idx = index;
835 return true;
836 }
837
838
839 static struct
840 hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device)
841 {
842 struct hisi_hba *hisi_hba = device->port->ha->lldd_ha;
843 struct hisi_sas_device *sas_dev = NULL;
844 int i, sata_dev = dev_is_sata(device);
845 int sata_idx = -1;
846 unsigned long flags;
847
848 spin_lock_irqsave(&hisi_hba->lock, flags);
849
850 if (sata_dev)
851 if (!sata_index_alloc_v2_hw(hisi_hba, &sata_idx))
852 goto out;
853
854 for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
855
856
857
858 if (sata_dev && (i & 1))
859 continue;
860 if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) {
861 int queue = i % hisi_hba->queue_count;
862 struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
863
864 hisi_hba->devices[i].device_id = i;
865 sas_dev = &hisi_hba->devices[i];
866 sas_dev->dev_status = HISI_SAS_DEV_INIT;
867 sas_dev->dev_type = device->dev_type;
868 sas_dev->hisi_hba = hisi_hba;
869 sas_dev->sas_device = device;
870 sas_dev->sata_idx = sata_idx;
871 sas_dev->dq = dq;
872 spin_lock_init(&sas_dev->lock);
873 INIT_LIST_HEAD(&hisi_hba->devices[i].list);
874 break;
875 }
876 }
877
878 out:
879 spin_unlock_irqrestore(&hisi_hba->lock, flags);
880
881 return sas_dev;
882 }
883
884 static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
885 {
886 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
887
888 cfg &= ~PHY_CFG_DC_OPT_MSK;
889 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
890 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
891 }
892
893 static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
894 {
895 struct sas_identify_frame identify_frame;
896 u32 *identify_buffer;
897
898 memset(&identify_frame, 0, sizeof(identify_frame));
899 identify_frame.dev_type = SAS_END_DEVICE;
900 identify_frame.frame_type = 0;
901 identify_frame._un1 = 1;
902 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
903 identify_frame.target_bits = SAS_PROTOCOL_NONE;
904 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
905 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
906 identify_frame.phy_id = phy_no;
907 identify_buffer = (u32 *)(&identify_frame);
908
909 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
910 __swab32(identify_buffer[0]));
911 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
912 __swab32(identify_buffer[1]));
913 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
914 __swab32(identify_buffer[2]));
915 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
916 __swab32(identify_buffer[3]));
917 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
918 __swab32(identify_buffer[4]));
919 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
920 __swab32(identify_buffer[5]));
921 }
922
923 static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
924 struct hisi_sas_device *sas_dev)
925 {
926 struct domain_device *device = sas_dev->sas_device;
927 struct device *dev = hisi_hba->dev;
928 u64 qw0, device_id = sas_dev->device_id;
929 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
930 struct domain_device *parent_dev = device->parent;
931 struct asd_sas_port *sas_port = device->port;
932 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
933 u64 sas_addr;
934
935 memset(itct, 0, sizeof(*itct));
936
937
938 qw0 = 0;
939 switch (sas_dev->dev_type) {
940 case SAS_END_DEVICE:
941 case SAS_EDGE_EXPANDER_DEVICE:
942 case SAS_FANOUT_EXPANDER_DEVICE:
943 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
944 break;
945 case SAS_SATA_DEV:
946 case SAS_SATA_PENDING:
947 if (parent_dev && dev_is_expander(parent_dev->dev_type))
948 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
949 else
950 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
951 break;
952 default:
953 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
954 sas_dev->dev_type);
955 }
956
957 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
958 (device->linkrate << ITCT_HDR_MCR_OFF) |
959 (1 << ITCT_HDR_VLN_OFF) |
960 (ITCT_HDR_SMP_TIMEOUT << ITCT_HDR_SMP_TIMEOUT_OFF) |
961 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
962 (port->id << ITCT_HDR_PORT_ID_OFF));
963 itct->qw0 = cpu_to_le64(qw0);
964
965
966 memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE);
967 itct->sas_addr = cpu_to_le64(__swab64(sas_addr));
968
969
970 if (!dev_is_sata(device))
971 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
972 (0x1ULL << ITCT_HDR_BITLT_OFF) |
973 (0x32ULL << ITCT_HDR_MCTLT_OFF) |
974 (0x1ULL << ITCT_HDR_RTOLT_OFF));
975 }
976
977 static void clear_itct_v2_hw(struct hisi_hba *hisi_hba,
978 struct hisi_sas_device *sas_dev)
979 {
980 DECLARE_COMPLETION_ONSTACK(completion);
981 u64 dev_id = sas_dev->device_id;
982 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
983 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
984 int i;
985
986 sas_dev->completion = &completion;
987
988
989 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
990 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
991 ENT_INT_SRC3_ITC_INT_MSK);
992
993 for (i = 0; i < 2; i++) {
994 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
995 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
996 wait_for_completion(sas_dev->completion);
997
998 memset(itct, 0, sizeof(struct hisi_sas_itct));
999 }
1000 }
1001
1002 static void free_device_v2_hw(struct hisi_sas_device *sas_dev)
1003 {
1004 struct hisi_hba *hisi_hba = sas_dev->hisi_hba;
1005
1006
1007 if (dev_is_sata(sas_dev->sas_device))
1008 clear_bit(sas_dev->sata_idx, hisi_hba->sata_dev_bitmap);
1009 }
1010
1011 static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
1012 {
1013 int i, reset_val;
1014 u32 val;
1015 unsigned long end_time;
1016 struct device *dev = hisi_hba->dev;
1017
1018
1019 if (hisi_hba->n_phy == 9)
1020 reset_val = 0x1fffff;
1021 else
1022 reset_val = 0x7ffff;
1023
1024 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
1025
1026
1027 for (i = 0; i < hisi_hba->n_phy; i++) {
1028 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
1029
1030 phy_cfg &= ~PHY_CTRL_RESET_MSK;
1031 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
1032 }
1033 udelay(50);
1034
1035
1036 for (i = 0; i < hisi_hba->n_phy; i++) {
1037 u32 dma_tx_status, dma_rx_status;
1038
1039 end_time = jiffies + msecs_to_jiffies(1000);
1040
1041 while (1) {
1042 dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
1043 DMA_TX_STATUS);
1044 dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
1045 DMA_RX_STATUS);
1046
1047 if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
1048 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
1049 break;
1050
1051 msleep(20);
1052 if (time_after(jiffies, end_time))
1053 return -EIO;
1054 }
1055 }
1056
1057
1058 end_time = jiffies + msecs_to_jiffies(1000);
1059 while (1) {
1060 u32 axi_status =
1061 hisi_sas_read32(hisi_hba, AXI_CFG);
1062
1063 if (axi_status == 0)
1064 break;
1065
1066 msleep(20);
1067 if (time_after(jiffies, end_time))
1068 return -EIO;
1069 }
1070
1071 if (ACPI_HANDLE(dev)) {
1072 acpi_status s;
1073
1074 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
1075 if (ACPI_FAILURE(s)) {
1076 dev_err(dev, "Reset failed\n");
1077 return -EIO;
1078 }
1079 } else if (hisi_hba->ctrl) {
1080
1081 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
1082 reset_val);
1083 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
1084 reset_val);
1085 msleep(1);
1086 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
1087 if (reset_val != (val & reset_val)) {
1088 dev_err(dev, "SAS reset fail.\n");
1089 return -EIO;
1090 }
1091
1092
1093 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
1094 reset_val);
1095 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
1096 reset_val);
1097 msleep(1);
1098 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
1099 &val);
1100 if (val & reset_val) {
1101 dev_err(dev, "SAS de-reset fail.\n");
1102 return -EIO;
1103 }
1104 } else {
1105 dev_err(dev, "no reset method\n");
1106 return -EINVAL;
1107 }
1108
1109 return 0;
1110 }
1111
1112
1113 static void phys_reject_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1114 {
1115 u32 cfg;
1116 int phy_no;
1117
1118 hisi_hba->reject_stp_links_msk = (1 << hisi_hba->n_phy) - 1;
1119 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1120 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, CON_CONTROL);
1121 if (!(cfg & CON_CONTROL_CFG_OPEN_ACC_STP_MSK))
1122 continue;
1123
1124 cfg &= ~CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1125 hisi_sas_phy_write32(hisi_hba, phy_no, CON_CONTROL, cfg);
1126 }
1127 }
1128
1129 static void phys_try_accept_stp_links_v2_hw(struct hisi_hba *hisi_hba)
1130 {
1131 int phy_no;
1132 u32 dma_tx_dfx1;
1133
1134 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1135 if (!(hisi_hba->reject_stp_links_msk & BIT(phy_no)))
1136 continue;
1137
1138 dma_tx_dfx1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1139 DMA_TX_DFX1);
1140 if (dma_tx_dfx1 & DMA_TX_DFX1_IPTT_MSK) {
1141 u32 cfg = hisi_sas_phy_read32(hisi_hba,
1142 phy_no, CON_CONTROL);
1143
1144 cfg |= CON_CONTROL_CFG_OPEN_ACC_STP_MSK;
1145 hisi_sas_phy_write32(hisi_hba, phy_no,
1146 CON_CONTROL, cfg);
1147 clear_bit(phy_no, &hisi_hba->reject_stp_links_msk);
1148 }
1149 }
1150 }
1151
1152 static const struct signal_attenuation_s x6000 = {9200, 0, 10476};
1153 static const struct sig_atten_lu_s sig_atten_lu[] = {
1154 { &x6000, 0x3016a68 },
1155 };
1156
1157 static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
1158 {
1159 struct device *dev = hisi_hba->dev;
1160 u32 sas_phy_ctrl = 0x30b9908;
1161 u32 signal[3];
1162 int i;
1163
1164
1165
1166
1167 if (device_property_present(dev, "hip06-sas-v2-quirk-amt")) {
1168 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
1169 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
1170 0x2020);
1171 }
1172
1173 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
1174 (u32)((1ULL << hisi_hba->queue_count) - 1));
1175 hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
1176 hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
1177 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x0);
1178 hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
1179 hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
1180 hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
1181 hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32);
1182 hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
1183 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
1184 hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
1185 hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
1186 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc);
1187 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x60);
1188 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x3);
1189 hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
1190 hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
1191 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
1192 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
1193 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
1194 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
1195 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
1196 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
1197 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffe20fe);
1198 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfff00c30);
1199 for (i = 0; i < hisi_hba->queue_count; i++)
1200 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
1201
1202 hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
1203 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
1204
1205
1206 if (!device_property_read_u32_array(dev, "hisilicon,signal-attenuation",
1207 signal, ARRAY_SIZE(signal))) {
1208 for (i = 0; i < ARRAY_SIZE(sig_atten_lu); i++) {
1209 const struct sig_atten_lu_s *lookup = &sig_atten_lu[i];
1210 const struct signal_attenuation_s *att = lookup->att;
1211
1212 if ((signal[0] == att->de_emphasis) &&
1213 (signal[1] == att->preshoot) &&
1214 (signal[2] == att->boost)) {
1215 sas_phy_ctrl = lookup->sas_phy_ctrl;
1216 break;
1217 }
1218 }
1219
1220 if (i == ARRAY_SIZE(sig_atten_lu))
1221 dev_warn(dev, "unknown signal attenuation values, using default PHY ctrl config\n");
1222 }
1223
1224 for (i = 0; i < hisi_hba->n_phy; i++) {
1225 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1226 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1227 u32 prog_phy_link_rate = 0x800;
1228
1229 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate <
1230 SAS_LINK_RATE_1_5_GBPS)) {
1231 prog_phy_link_rate = 0x855;
1232 } else {
1233 enum sas_linkrate max = sas_phy->phy->maximum_linkrate;
1234
1235 prog_phy_link_rate =
1236 hisi_sas_get_prog_phy_linkrate_mask(max) |
1237 0x800;
1238 }
1239 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,
1240 prog_phy_link_rate);
1241 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, sas_phy_ctrl);
1242 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
1243 hisi_sas_phy_write32(hisi_hba, i, SL_CONTROL, 0x0);
1244 hisi_sas_phy_write32(hisi_hba, i, TXID_AUTO, 0x2);
1245 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x8);
1246 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
1247 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
1248 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xfff87fff);
1249 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
1250 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xff857fff);
1251 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbfe);
1252 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x13f801fc);
1253 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
1254 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
1255 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
1256 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
1257 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
1258 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
1259 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
1260 if (hisi_hba->refclk_frequency_mhz == 66)
1261 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
1262
1263 }
1264
1265 for (i = 0; i < hisi_hba->queue_count; i++) {
1266
1267 hisi_sas_write32(hisi_hba,
1268 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
1269 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
1270
1271 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
1272 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
1273
1274 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
1275 HISI_SAS_QUEUE_SLOTS);
1276
1277
1278 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
1279 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
1280
1281 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
1282 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
1283
1284 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
1285 HISI_SAS_QUEUE_SLOTS);
1286 }
1287
1288
1289 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
1290 lower_32_bits(hisi_hba->itct_dma));
1291
1292 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
1293 upper_32_bits(hisi_hba->itct_dma));
1294
1295
1296 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
1297 lower_32_bits(hisi_hba->iost_dma));
1298
1299 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
1300 upper_32_bits(hisi_hba->iost_dma));
1301
1302
1303 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
1304 lower_32_bits(hisi_hba->breakpoint_dma));
1305
1306 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
1307 upper_32_bits(hisi_hba->breakpoint_dma));
1308
1309
1310 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
1311 lower_32_bits(hisi_hba->sata_breakpoint_dma));
1312
1313 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
1314 upper_32_bits(hisi_hba->sata_breakpoint_dma));
1315
1316
1317 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
1318 lower_32_bits(hisi_hba->initial_fis_dma));
1319
1320 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
1321 upper_32_bits(hisi_hba->initial_fis_dma));
1322 }
1323
1324 static void link_timeout_enable_link(struct timer_list *t)
1325 {
1326 struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
1327 int i, reg_val;
1328
1329 for (i = 0; i < hisi_hba->n_phy; i++) {
1330 if (hisi_hba->reject_stp_links_msk & BIT(i))
1331 continue;
1332
1333 reg_val = hisi_sas_phy_read32(hisi_hba, i, CON_CONTROL);
1334 if (!(reg_val & BIT(0))) {
1335 hisi_sas_phy_write32(hisi_hba, i,
1336 CON_CONTROL, 0x7);
1337 break;
1338 }
1339 }
1340
1341 hisi_hba->timer.function = link_timeout_disable_link;
1342 mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(900));
1343 }
1344
1345 static void link_timeout_disable_link(struct timer_list *t)
1346 {
1347 struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer);
1348 int i, reg_val;
1349
1350 reg_val = hisi_sas_read32(hisi_hba, PHY_STATE);
1351 for (i = 0; i < hisi_hba->n_phy && reg_val; i++) {
1352 if (hisi_hba->reject_stp_links_msk & BIT(i))
1353 continue;
1354
1355 if (reg_val & BIT(i)) {
1356 hisi_sas_phy_write32(hisi_hba, i,
1357 CON_CONTROL, 0x6);
1358 break;
1359 }
1360 }
1361
1362 hisi_hba->timer.function = link_timeout_enable_link;
1363 mod_timer(&hisi_hba->timer, jiffies + msecs_to_jiffies(100));
1364 }
1365
1366 static void set_link_timer_quirk(struct hisi_hba *hisi_hba)
1367 {
1368 hisi_hba->timer.function = link_timeout_disable_link;
1369 hisi_hba->timer.expires = jiffies + msecs_to_jiffies(1000);
1370 add_timer(&hisi_hba->timer);
1371 }
1372
1373 static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
1374 {
1375 struct device *dev = hisi_hba->dev;
1376 int rc;
1377
1378 rc = reset_hw_v2_hw(hisi_hba);
1379 if (rc) {
1380 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
1381 return rc;
1382 }
1383
1384 msleep(100);
1385 init_reg_v2_hw(hisi_hba);
1386
1387 return 0;
1388 }
1389
1390 static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1391 {
1392 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1393
1394 cfg |= PHY_CFG_ENA_MSK;
1395 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1396 }
1397
1398 static bool is_sata_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1399 {
1400 u32 context;
1401
1402 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1403 if (context & (1 << phy_no))
1404 return true;
1405
1406 return false;
1407 }
1408
1409 static bool tx_fifo_is_empty_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1410 {
1411 u32 dfx_val;
1412
1413 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1414
1415 if (dfx_val & BIT(16))
1416 return false;
1417
1418 return true;
1419 }
1420
1421 static bool axi_bus_is_idle_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1422 {
1423 int i, max_loop = 1000;
1424 struct device *dev = hisi_hba->dev;
1425 u32 status, axi_status, dfx_val, dfx_tx_val;
1426
1427 for (i = 0; i < max_loop; i++) {
1428 status = hisi_sas_read32_relaxed(hisi_hba,
1429 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
1430
1431 axi_status = hisi_sas_read32(hisi_hba, AXI_CFG);
1432 dfx_val = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX1);
1433 dfx_tx_val = hisi_sas_phy_read32(hisi_hba,
1434 phy_no, DMA_TX_FIFO_DFX0);
1435
1436 if ((status == 0x3) && (axi_status == 0x0) &&
1437 (dfx_val & BIT(20)) && (dfx_tx_val & BIT(10)))
1438 return true;
1439 udelay(10);
1440 }
1441 dev_err(dev, "bus is not idle phy%d, axi150:0x%x axi100:0x%x port204:0x%x port240:0x%x\n",
1442 phy_no, status, axi_status,
1443 dfx_val, dfx_tx_val);
1444 return false;
1445 }
1446
1447 static bool wait_io_done_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1448 {
1449 int i, max_loop = 1000;
1450 struct device *dev = hisi_hba->dev;
1451 u32 status, tx_dfx0;
1452
1453 for (i = 0; i < max_loop; i++) {
1454 status = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
1455 status = (status & 0x3fc0) >> 6;
1456
1457 if (status != 0x1)
1458 return true;
1459
1460 tx_dfx0 = hisi_sas_phy_read32(hisi_hba, phy_no, DMA_TX_DFX0);
1461 if ((tx_dfx0 & 0x1ff) == 0x2)
1462 return true;
1463 udelay(10);
1464 }
1465 dev_err(dev, "IO not done phy%d, port264:0x%x port200:0x%x\n",
1466 phy_no, status, tx_dfx0);
1467 return false;
1468 }
1469
1470 static bool allowed_disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1471 {
1472 if (tx_fifo_is_empty_v2_hw(hisi_hba, phy_no))
1473 return true;
1474
1475 if (!axi_bus_is_idle_v2_hw(hisi_hba, phy_no))
1476 return false;
1477
1478 if (!wait_io_done_v2_hw(hisi_hba, phy_no))
1479 return false;
1480
1481 return true;
1482 }
1483
1484
1485 static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1486 {
1487 u32 cfg, axi_val, dfx0_val, txid_auto;
1488 struct device *dev = hisi_hba->dev;
1489
1490
1491 axi_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
1492 AM_CTRL_GLOBAL);
1493 axi_val |= 0x1;
1494 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1495 AM_CTRL_GLOBAL, axi_val);
1496
1497 if (is_sata_phy_v2_hw(hisi_hba, phy_no)) {
1498 if (allowed_disable_phy_v2_hw(hisi_hba, phy_no))
1499 goto do_disable;
1500
1501
1502 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1503 return;
1504 }
1505
1506 dfx0_val = hisi_sas_phy_read32(hisi_hba, phy_no, PORT_DFX0);
1507 dfx0_val = (dfx0_val & 0x1fc0) >> 6;
1508 if (dfx0_val != 0x4)
1509 goto do_disable;
1510
1511 if (!tx_fifo_is_empty_v2_hw(hisi_hba, phy_no)) {
1512 dev_warn(dev, "phy%d, wait tx fifo need send break\n",
1513 phy_no);
1514 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
1515 TXID_AUTO);
1516 txid_auto |= TXID_AUTO_CTB_MSK;
1517 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1518 txid_auto);
1519 }
1520
1521 do_disable:
1522 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1523 cfg &= ~PHY_CFG_ENA_MSK;
1524 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1525
1526
1527 axi_val &= ~0x1;
1528 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
1529 AM_CTRL_GLOBAL, axi_val);
1530 }
1531
1532 static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1533 {
1534 config_id_frame_v2_hw(hisi_hba, phy_no);
1535 config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
1536 enable_phy_v2_hw(hisi_hba, phy_no);
1537 }
1538
1539 static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1540 {
1541 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1542 u32 txid_auto;
1543
1544 hisi_sas_phy_enable(hisi_hba, phy_no, 0);
1545 if (phy->identify.device_type == SAS_END_DEVICE) {
1546 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1547 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1548 txid_auto | TX_HARDRST_MSK);
1549 }
1550 msleep(100);
1551 hisi_sas_phy_enable(hisi_hba, phy_no, 1);
1552 }
1553
1554 static void phy_get_events_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1555 {
1556 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1557 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1558 struct sas_phy *sphy = sas_phy->phy;
1559 u32 err4_reg_val, err6_reg_val;
1560
1561
1562 err4_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT4_REG);
1563
1564
1565 err6_reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_ERR_CNT6_REG);
1566
1567 sphy->loss_of_dword_sync_count += (err4_reg_val >> 16) & 0xFFFF;
1568 sphy->phy_reset_problem_count += err4_reg_val & 0xFFFF;
1569 sphy->invalid_dword_count += (err6_reg_val & 0xFF0000) >> 16;
1570 sphy->running_disparity_error_count += err6_reg_val & 0xFF;
1571 }
1572
1573 static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
1574 {
1575 int i;
1576
1577 for (i = 0; i < hisi_hba->n_phy; i++) {
1578 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1579 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1580
1581 if (!sas_phy->phy->enabled)
1582 continue;
1583
1584 hisi_sas_phy_enable(hisi_hba, i, 1);
1585 }
1586 }
1587
1588 static void sl_notify_ssp_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
1589 {
1590 u32 sl_control;
1591
1592 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1593 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
1594 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1595 msleep(1);
1596 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1597 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
1598 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1599 }
1600
1601 static enum sas_linkrate phy_get_max_linkrate_v2_hw(void)
1602 {
1603 return SAS_LINK_RATE_12_0_GBPS;
1604 }
1605
1606 static void phy_set_linkrate_v2_hw(struct hisi_hba *hisi_hba, int phy_no,
1607 struct sas_phy_linkrates *r)
1608 {
1609 enum sas_linkrate max = r->maximum_linkrate;
1610 u32 prog_phy_link_rate = 0x800;
1611
1612 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
1613 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1614 prog_phy_link_rate);
1615 }
1616
1617 static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
1618 {
1619 int i, bitmap = 0;
1620 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1621 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1622
1623 for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++)
1624 if (phy_state & 1 << i)
1625 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
1626 bitmap |= 1 << i;
1627
1628 if (hisi_hba->n_phy == 9) {
1629 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
1630
1631 if (phy_state & 1 << 8)
1632 if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1633 PORT_STATE_PHY8_PORT_NUM_OFF) == port_id)
1634 bitmap |= 1 << 9;
1635 }
1636
1637 return bitmap;
1638 }
1639
1640
1641 static void start_delivery_v2_hw(struct hisi_sas_dq *dq)
1642 {
1643 struct hisi_hba *hisi_hba = dq->hisi_hba;
1644 struct hisi_sas_slot *s, *s1, *s2 = NULL;
1645 int dlvry_queue = dq->id;
1646 int wp;
1647
1648 list_for_each_entry_safe(s, s1, &dq->list, delivery) {
1649 if (!s->ready)
1650 break;
1651 s2 = s;
1652 list_del(&s->delivery);
1653 }
1654
1655 if (!s2)
1656 return;
1657
1658
1659
1660
1661 smp_rmb();
1662 wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;
1663
1664 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);
1665 }
1666
1667 static void prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
1668 struct hisi_sas_slot *slot,
1669 struct hisi_sas_cmd_hdr *hdr,
1670 struct scatterlist *scatter,
1671 int n_elem)
1672 {
1673 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
1674 struct scatterlist *sg;
1675 int i;
1676
1677 for_each_sg(scatter, sg, n_elem, i) {
1678 struct hisi_sas_sge *entry = &sge_page->sge[i];
1679
1680 entry->addr = cpu_to_le64(sg_dma_address(sg));
1681 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1682 entry->data_len = cpu_to_le32(sg_dma_len(sg));
1683 entry->data_off = 0;
1684 }
1685
1686 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
1687
1688 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1689 }
1690
1691 static void prep_smp_v2_hw(struct hisi_hba *hisi_hba,
1692 struct hisi_sas_slot *slot)
1693 {
1694 struct sas_task *task = slot->task;
1695 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1696 struct domain_device *device = task->dev;
1697 struct hisi_sas_port *port = slot->port;
1698 struct scatterlist *sg_req;
1699 struct hisi_sas_device *sas_dev = device->lldd_dev;
1700 dma_addr_t req_dma_addr;
1701 unsigned int req_len;
1702
1703
1704 sg_req = &task->smp_task.smp_req;
1705 req_dma_addr = sg_dma_address(sg_req);
1706 req_len = sg_dma_len(&task->smp_task.smp_req);
1707
1708
1709
1710 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1711 (1 << CMD_HDR_PRIORITY_OFF) |
1712 (2 << CMD_HDR_CMD_OFF));
1713
1714
1715 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1716 (1 << CMD_HDR_FRAME_TYPE_OFF) |
1717 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1718
1719
1720 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1721 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1722 CMD_HDR_MRFL_OFF));
1723
1724 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1725
1726 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1727 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1728 }
1729
1730 static void prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
1731 struct hisi_sas_slot *slot)
1732 {
1733 struct sas_task *task = slot->task;
1734 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1735 struct domain_device *device = task->dev;
1736 struct hisi_sas_device *sas_dev = device->lldd_dev;
1737 struct hisi_sas_port *port = slot->port;
1738 struct sas_ssp_task *ssp_task = &task->ssp_task;
1739 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1740 struct hisi_sas_tmf_task *tmf = slot->tmf;
1741 int has_data = 0, priority = !!tmf;
1742 u8 *buf_cmd;
1743 u32 dw1 = 0, dw2 = 0;
1744
1745 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1746 (2 << CMD_HDR_TLR_CTRL_OFF) |
1747 (port->id << CMD_HDR_PORT_OFF) |
1748 (priority << CMD_HDR_PRIORITY_OFF) |
1749 (1 << CMD_HDR_CMD_OFF));
1750
1751 dw1 = 1 << CMD_HDR_VDTL_OFF;
1752 if (tmf) {
1753 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1754 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1755 } else {
1756 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1757 switch (scsi_cmnd->sc_data_direction) {
1758 case DMA_TO_DEVICE:
1759 has_data = 1;
1760 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1761 break;
1762 case DMA_FROM_DEVICE:
1763 has_data = 1;
1764 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1765 break;
1766 default:
1767 dw1 &= ~CMD_HDR_DIR_MSK;
1768 }
1769 }
1770
1771
1772 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1773 hdr->dw1 = cpu_to_le32(dw1);
1774
1775 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1776 + 3) / 4) << CMD_HDR_CFL_OFF) |
1777 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1778 (2 << CMD_HDR_SG_MOD_OFF);
1779 hdr->dw2 = cpu_to_le32(dw2);
1780
1781 hdr->transfer_tags = cpu_to_le32(slot->idx);
1782
1783 if (has_data)
1784 prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
1785 slot->n_elem);
1786
1787 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1788 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1789 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1790
1791 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1792 sizeof(struct ssp_frame_hdr);
1793
1794 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1795 if (!tmf) {
1796 buf_cmd[9] = task->ssp_task.task_attr |
1797 (task->ssp_task.task_prio << 3);
1798 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
1799 task->ssp_task.cmd->cmd_len);
1800 } else {
1801 buf_cmd[10] = tmf->tmf;
1802 switch (tmf->tmf) {
1803 case TMF_ABORT_TASK:
1804 case TMF_QUERY_TASK:
1805 buf_cmd[12] =
1806 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1807 buf_cmd[13] =
1808 tmf->tag_of_task_to_be_managed & 0xff;
1809 break;
1810 default:
1811 break;
1812 }
1813 }
1814 }
1815
1816 #define TRANS_TX_ERR 0
1817 #define TRANS_RX_ERR 1
1818 #define DMA_TX_ERR 2
1819 #define SIPC_RX_ERR 3
1820 #define DMA_RX_ERR 4
1821
1822 #define DMA_TX_ERR_OFF 0
1823 #define DMA_TX_ERR_MSK (0xffff << DMA_TX_ERR_OFF)
1824 #define SIPC_RX_ERR_OFF 16
1825 #define SIPC_RX_ERR_MSK (0xffff << SIPC_RX_ERR_OFF)
1826
1827 static int parse_trans_tx_err_code_v2_hw(u32 err_msk)
1828 {
1829 static const u8 trans_tx_err_code_prio[] = {
1830 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS,
1831 TRANS_TX_ERR_PHY_NOT_ENABLE,
1832 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION,
1833 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION,
1834 TRANS_TX_OPEN_CNX_ERR_BY_OTHER,
1835 RESERVED0,
1836 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT,
1837 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY,
1838 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED,
1839 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED,
1840 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION,
1841 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD,
1842 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER,
1843 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED,
1844 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT,
1845 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION,
1846 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED,
1847 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE,
1848 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1849 TRANS_TX_ERR_WITH_CLOSE_COMINIT,
1850 TRANS_TX_ERR_WITH_BREAK_TIMEOUT,
1851 TRANS_TX_ERR_WITH_BREAK_REQUEST,
1852 TRANS_TX_ERR_WITH_BREAK_RECEVIED,
1853 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT,
1854 TRANS_TX_ERR_WITH_CLOSE_NORMAL,
1855 TRANS_TX_ERR_WITH_NAK_RECEVIED,
1856 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT,
1857 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT,
1858 TRANS_TX_ERR_WITH_IPTT_CONFLICT,
1859 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS,
1860 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT,
1861 };
1862 int index, i;
1863
1864 for (i = 0; i < ARRAY_SIZE(trans_tx_err_code_prio); i++) {
1865 index = trans_tx_err_code_prio[i] - TRANS_TX_FAIL_BASE;
1866 if (err_msk & (1 << index))
1867 return trans_tx_err_code_prio[i];
1868 }
1869 return -1;
1870 }
1871
1872 static int parse_trans_rx_err_code_v2_hw(u32 err_msk)
1873 {
1874 static const u8 trans_rx_err_code_prio[] = {
1875 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR,
1876 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR,
1877 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM,
1878 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR,
1879 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR,
1880 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN,
1881 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP,
1882 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN,
1883 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE,
1884 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT,
1885 TRANS_RX_ERR_WITH_CLOSE_COMINIT,
1886 TRANS_RX_ERR_WITH_BREAK_TIMEOUT,
1887 TRANS_RX_ERR_WITH_BREAK_REQUEST,
1888 TRANS_RX_ERR_WITH_BREAK_RECEVIED,
1889 RESERVED1,
1890 TRANS_RX_ERR_WITH_CLOSE_NORMAL,
1891 TRANS_RX_ERR_WITH_DATA_LEN0,
1892 TRANS_RX_ERR_WITH_BAD_HASH,
1893 TRANS_RX_XRDY_WLEN_ZERO_ERR,
1894 TRANS_RX_SSP_FRM_LEN_ERR,
1895 RESERVED2,
1896 RESERVED3,
1897 RESERVED4,
1898 RESERVED5,
1899 TRANS_RX_ERR_WITH_BAD_FRM_TYPE,
1900 TRANS_RX_SMP_FRM_LEN_ERR,
1901 TRANS_RX_SMP_RESP_TIMEOUT_ERR,
1902 RESERVED6,
1903 RESERVED7,
1904 RESERVED8,
1905 RESERVED9,
1906 TRANS_RX_R_ERR,
1907 };
1908 int index, i;
1909
1910 for (i = 0; i < ARRAY_SIZE(trans_rx_err_code_prio); i++) {
1911 index = trans_rx_err_code_prio[i] - TRANS_RX_FAIL_BASE;
1912 if (err_msk & (1 << index))
1913 return trans_rx_err_code_prio[i];
1914 }
1915 return -1;
1916 }
1917
1918 static int parse_dma_tx_err_code_v2_hw(u32 err_msk)
1919 {
1920 static const u8 dma_tx_err_code_prio[] = {
1921 DMA_TX_UNEXP_XFER_ERR,
1922 DMA_TX_UNEXP_RETRANS_ERR,
1923 DMA_TX_XFER_LEN_OVERFLOW,
1924 DMA_TX_XFER_OFFSET_ERR,
1925 DMA_TX_RAM_ECC_ERR,
1926 DMA_TX_DIF_LEN_ALIGN_ERR,
1927 DMA_TX_DIF_CRC_ERR,
1928 DMA_TX_DIF_APP_ERR,
1929 DMA_TX_DIF_RPP_ERR,
1930 DMA_TX_DATA_SGL_OVERFLOW,
1931 DMA_TX_DIF_SGL_OVERFLOW,
1932 };
1933 int index, i;
1934
1935 for (i = 0; i < ARRAY_SIZE(dma_tx_err_code_prio); i++) {
1936 index = dma_tx_err_code_prio[i] - DMA_TX_ERR_BASE;
1937 err_msk = err_msk & DMA_TX_ERR_MSK;
1938 if (err_msk & (1 << index))
1939 return dma_tx_err_code_prio[i];
1940 }
1941 return -1;
1942 }
1943
1944 static int parse_sipc_rx_err_code_v2_hw(u32 err_msk)
1945 {
1946 static const u8 sipc_rx_err_code_prio[] = {
1947 SIPC_RX_FIS_STATUS_ERR_BIT_VLD,
1948 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR,
1949 SIPC_RX_FIS_STATUS_BSY_BIT_ERR,
1950 SIPC_RX_WRSETUP_LEN_ODD_ERR,
1951 SIPC_RX_WRSETUP_LEN_ZERO_ERR,
1952 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR,
1953 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR,
1954 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR,
1955 SIPC_RX_SATA_UNEXP_FIS_ERR,
1956 SIPC_RX_WRSETUP_ESTATUS_ERR,
1957 SIPC_RX_DATA_UNDERFLOW_ERR,
1958 };
1959 int index, i;
1960
1961 for (i = 0; i < ARRAY_SIZE(sipc_rx_err_code_prio); i++) {
1962 index = sipc_rx_err_code_prio[i] - SIPC_RX_ERR_BASE;
1963 err_msk = err_msk & SIPC_RX_ERR_MSK;
1964 if (err_msk & (1 << (index + 0x10)))
1965 return sipc_rx_err_code_prio[i];
1966 }
1967 return -1;
1968 }
1969
1970 static int parse_dma_rx_err_code_v2_hw(u32 err_msk)
1971 {
1972 static const u8 dma_rx_err_code_prio[] = {
1973 DMA_RX_UNKNOWN_FRM_ERR,
1974 DMA_RX_DATA_LEN_OVERFLOW,
1975 DMA_RX_DATA_LEN_UNDERFLOW,
1976 DMA_RX_DATA_OFFSET_ERR,
1977 RESERVED10,
1978 DMA_RX_SATA_FRAME_TYPE_ERR,
1979 DMA_RX_RESP_BUF_OVERFLOW,
1980 DMA_RX_UNEXP_RETRANS_RESP_ERR,
1981 DMA_RX_UNEXP_NORM_RESP_ERR,
1982 DMA_RX_UNEXP_RDFRAME_ERR,
1983 DMA_RX_PIO_DATA_LEN_ERR,
1984 DMA_RX_RDSETUP_STATUS_ERR,
1985 DMA_RX_RDSETUP_STATUS_DRQ_ERR,
1986 DMA_RX_RDSETUP_STATUS_BSY_ERR,
1987 DMA_RX_RDSETUP_LEN_ODD_ERR,
1988 DMA_RX_RDSETUP_LEN_ZERO_ERR,
1989 DMA_RX_RDSETUP_LEN_OVER_ERR,
1990 DMA_RX_RDSETUP_OFFSET_ERR,
1991 DMA_RX_RDSETUP_ACTIVE_ERR,
1992 DMA_RX_RDSETUP_ESTATUS_ERR,
1993 DMA_RX_RAM_ECC_ERR,
1994 DMA_RX_DIF_CRC_ERR,
1995 DMA_RX_DIF_APP_ERR,
1996 DMA_RX_DIF_RPP_ERR,
1997 DMA_RX_DATA_SGL_OVERFLOW,
1998 DMA_RX_DIF_SGL_OVERFLOW,
1999 };
2000 int index, i;
2001
2002 for (i = 0; i < ARRAY_SIZE(dma_rx_err_code_prio); i++) {
2003 index = dma_rx_err_code_prio[i] - DMA_RX_ERR_BASE;
2004 if (err_msk & (1 << index))
2005 return dma_rx_err_code_prio[i];
2006 }
2007 return -1;
2008 }
2009
2010
2011 static void slot_err_v2_hw(struct hisi_hba *hisi_hba,
2012 struct sas_task *task,
2013 struct hisi_sas_slot *slot,
2014 int err_phase)
2015 {
2016 struct task_status_struct *ts = &task->task_status;
2017 struct hisi_sas_err_record_v2 *err_record =
2018 hisi_sas_status_buf_addr_mem(slot);
2019 u32 trans_tx_fail_type = le32_to_cpu(err_record->trans_tx_fail_type);
2020 u32 trans_rx_fail_type = le32_to_cpu(err_record->trans_rx_fail_type);
2021 u16 dma_tx_err_type = le16_to_cpu(err_record->dma_tx_err_type);
2022 u16 sipc_rx_err_type = le16_to_cpu(err_record->sipc_rx_err_type);
2023 u32 dma_rx_err_type = le32_to_cpu(err_record->dma_rx_err_type);
2024 int error = -1;
2025
2026 if (err_phase == 1) {
2027
2028 error = parse_dma_tx_err_code_v2_hw(dma_tx_err_type);
2029 if (error == -1)
2030 error = parse_trans_tx_err_code_v2_hw(
2031 trans_tx_fail_type);
2032 } else if (err_phase == 2) {
2033
2034 error = parse_trans_rx_err_code_v2_hw(trans_rx_fail_type);
2035 if (error == -1) {
2036 error = parse_dma_rx_err_code_v2_hw(
2037 dma_rx_err_type);
2038 if (error == -1)
2039 error = parse_sipc_rx_err_code_v2_hw(
2040 sipc_rx_err_type);
2041 }
2042 }
2043
2044 switch (task->task_proto) {
2045 case SAS_PROTOCOL_SSP:
2046 {
2047 switch (error) {
2048 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2049 {
2050 ts->stat = SAS_OPEN_REJECT;
2051 ts->open_rej_reason = SAS_OREJ_NO_DEST;
2052 break;
2053 }
2054 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2055 {
2056 ts->stat = SAS_OPEN_REJECT;
2057 ts->open_rej_reason = SAS_OREJ_EPROTO;
2058 break;
2059 }
2060 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2061 {
2062 ts->stat = SAS_OPEN_REJECT;
2063 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2064 break;
2065 }
2066 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2067 {
2068 ts->stat = SAS_OPEN_REJECT;
2069 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2070 break;
2071 }
2072 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2073 {
2074 ts->stat = SAS_OPEN_REJECT;
2075 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2076 break;
2077 }
2078 case DMA_RX_UNEXP_NORM_RESP_ERR:
2079 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2080 case DMA_RX_RESP_BUF_OVERFLOW:
2081 {
2082 ts->stat = SAS_OPEN_REJECT;
2083 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2084 break;
2085 }
2086 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2087 {
2088
2089 ts->stat = SAS_DEV_NO_RESPONSE;
2090 break;
2091 }
2092 case DMA_RX_DATA_LEN_OVERFLOW:
2093 {
2094 ts->stat = SAS_DATA_OVERRUN;
2095 ts->residual = 0;
2096 break;
2097 }
2098 case DMA_RX_DATA_LEN_UNDERFLOW:
2099 {
2100 ts->residual = trans_tx_fail_type;
2101 ts->stat = SAS_DATA_UNDERRUN;
2102 break;
2103 }
2104 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2105 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2106 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2107 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2108 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2109 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2110 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2111 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2112 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2113 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2114 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2115 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2116 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2117 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2118 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2119 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2120 case TRANS_TX_ERR_WITH_NAK_RECEVIED:
2121 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2122 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2123 case TRANS_TX_ERR_WITH_IPTT_CONFLICT:
2124 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR:
2125 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2126 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2127 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2128 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2129 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2130 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2131 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2132 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2133 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2134 case TRANS_TX_ERR_FRAME_TXED:
2135 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2136 case TRANS_RX_ERR_WITH_DATA_LEN0:
2137 case TRANS_RX_ERR_WITH_BAD_HASH:
2138 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2139 case TRANS_RX_SSP_FRM_LEN_ERR:
2140 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2141 case DMA_TX_DATA_SGL_OVERFLOW:
2142 case DMA_TX_UNEXP_XFER_ERR:
2143 case DMA_TX_UNEXP_RETRANS_ERR:
2144 case DMA_TX_XFER_LEN_OVERFLOW:
2145 case DMA_TX_XFER_OFFSET_ERR:
2146 case SIPC_RX_DATA_UNDERFLOW_ERR:
2147 case DMA_RX_DATA_SGL_OVERFLOW:
2148 case DMA_RX_DATA_OFFSET_ERR:
2149 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2150 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2151 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2152 case DMA_RX_SATA_FRAME_TYPE_ERR:
2153 case DMA_RX_UNKNOWN_FRM_ERR:
2154 {
2155
2156 ts->stat = SAS_QUEUE_FULL;
2157 slot->abort = 1;
2158 break;
2159 }
2160 default:
2161 break;
2162 }
2163 }
2164 break;
2165 case SAS_PROTOCOL_SMP:
2166 ts->stat = SAM_STAT_CHECK_CONDITION;
2167 break;
2168
2169 case SAS_PROTOCOL_SATA:
2170 case SAS_PROTOCOL_STP:
2171 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2172 {
2173 switch (error) {
2174 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION:
2175 {
2176 ts->stat = SAS_OPEN_REJECT;
2177 ts->open_rej_reason = SAS_OREJ_NO_DEST;
2178 break;
2179 }
2180 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER:
2181 {
2182 ts->resp = SAS_TASK_UNDELIVERED;
2183 ts->stat = SAS_DEV_NO_RESPONSE;
2184 break;
2185 }
2186 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED:
2187 {
2188 ts->stat = SAS_OPEN_REJECT;
2189 ts->open_rej_reason = SAS_OREJ_EPROTO;
2190 break;
2191 }
2192 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED:
2193 {
2194 ts->stat = SAS_OPEN_REJECT;
2195 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2196 break;
2197 }
2198 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION:
2199 {
2200 ts->stat = SAS_OPEN_REJECT;
2201 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2202 break;
2203 }
2204 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION:
2205 {
2206 ts->stat = SAS_OPEN_REJECT;
2207 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2208 break;
2209 }
2210 case DMA_RX_RESP_BUF_OVERFLOW:
2211 case DMA_RX_UNEXP_NORM_RESP_ERR:
2212 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION:
2213 {
2214 ts->stat = SAS_OPEN_REJECT;
2215 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2216 break;
2217 }
2218 case DMA_RX_DATA_LEN_OVERFLOW:
2219 {
2220 ts->stat = SAS_DATA_OVERRUN;
2221 ts->residual = 0;
2222 break;
2223 }
2224 case DMA_RX_DATA_LEN_UNDERFLOW:
2225 {
2226 ts->residual = trans_tx_fail_type;
2227 ts->stat = SAS_DATA_UNDERRUN;
2228 break;
2229 }
2230 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS:
2231 case TRANS_TX_ERR_PHY_NOT_ENABLE:
2232 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER:
2233 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT:
2234 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD:
2235 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED:
2236 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT:
2237 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED:
2238 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT:
2239 case TRANS_TX_ERR_WITH_BREAK_REQUEST:
2240 case TRANS_TX_ERR_WITH_BREAK_RECEVIED:
2241 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT:
2242 case TRANS_TX_ERR_WITH_CLOSE_NORMAL:
2243 case TRANS_TX_ERR_WITH_CLOSE_PHYDISALE:
2244 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2245 case TRANS_TX_ERR_WITH_CLOSE_COMINIT:
2246 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT:
2247 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT:
2248 case TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS:
2249 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT:
2250 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM:
2251 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR:
2252 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR:
2253 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR:
2254 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN:
2255 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP:
2256 case TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN:
2257 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT:
2258 case TRANS_RX_ERR_WITH_BREAK_REQUEST:
2259 case TRANS_RX_ERR_WITH_BREAK_RECEVIED:
2260 case TRANS_RX_ERR_WITH_CLOSE_NORMAL:
2261 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE:
2262 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT:
2263 case TRANS_RX_ERR_WITH_CLOSE_COMINIT:
2264 case TRANS_RX_ERR_WITH_DATA_LEN0:
2265 case TRANS_RX_ERR_WITH_BAD_HASH:
2266 case TRANS_RX_XRDY_WLEN_ZERO_ERR:
2267 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE:
2268 case DMA_TX_DATA_SGL_OVERFLOW:
2269 case DMA_TX_UNEXP_XFER_ERR:
2270 case DMA_TX_UNEXP_RETRANS_ERR:
2271 case DMA_TX_XFER_LEN_OVERFLOW:
2272 case DMA_TX_XFER_OFFSET_ERR:
2273 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD:
2274 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR:
2275 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR:
2276 case SIPC_RX_WRSETUP_LEN_ODD_ERR:
2277 case SIPC_RX_WRSETUP_LEN_ZERO_ERR:
2278 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR:
2279 case SIPC_RX_SATA_UNEXP_FIS_ERR:
2280 case DMA_RX_DATA_SGL_OVERFLOW:
2281 case DMA_RX_DATA_OFFSET_ERR:
2282 case DMA_RX_SATA_FRAME_TYPE_ERR:
2283 case DMA_RX_UNEXP_RDFRAME_ERR:
2284 case DMA_RX_PIO_DATA_LEN_ERR:
2285 case DMA_RX_RDSETUP_STATUS_ERR:
2286 case DMA_RX_RDSETUP_STATUS_DRQ_ERR:
2287 case DMA_RX_RDSETUP_STATUS_BSY_ERR:
2288 case DMA_RX_RDSETUP_LEN_ODD_ERR:
2289 case DMA_RX_RDSETUP_LEN_ZERO_ERR:
2290 case DMA_RX_RDSETUP_LEN_OVER_ERR:
2291 case DMA_RX_RDSETUP_OFFSET_ERR:
2292 case DMA_RX_RDSETUP_ACTIVE_ERR:
2293 case DMA_RX_RDSETUP_ESTATUS_ERR:
2294 case DMA_RX_UNKNOWN_FRM_ERR:
2295 case TRANS_RX_SSP_FRM_LEN_ERR:
2296 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY:
2297 {
2298 slot->abort = 1;
2299 ts->stat = SAS_PHY_DOWN;
2300 break;
2301 }
2302 default:
2303 {
2304 ts->stat = SAS_PROTO_RESPONSE;
2305 break;
2306 }
2307 }
2308 hisi_sas_sata_done(task, slot);
2309 }
2310 break;
2311 default:
2312 break;
2313 }
2314 }
2315
2316 static int
2317 slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
2318 {
2319 struct sas_task *task = slot->task;
2320 struct hisi_sas_device *sas_dev;
2321 struct device *dev = hisi_hba->dev;
2322 struct task_status_struct *ts;
2323 struct domain_device *device;
2324 struct sas_ha_struct *ha;
2325 enum exec_status sts;
2326 struct hisi_sas_complete_v2_hdr *complete_queue =
2327 hisi_hba->complete_hdr[slot->cmplt_queue];
2328 struct hisi_sas_complete_v2_hdr *complete_hdr =
2329 &complete_queue[slot->cmplt_queue_slot];
2330 unsigned long flags;
2331 bool is_internal = slot->is_internal;
2332 u32 dw0;
2333
2334 if (unlikely(!task || !task->lldd_task || !task->dev))
2335 return -EINVAL;
2336
2337 ts = &task->task_status;
2338 device = task->dev;
2339 ha = device->port->ha;
2340 sas_dev = device->lldd_dev;
2341
2342 spin_lock_irqsave(&task->task_state_lock, flags);
2343 task->task_state_flags &=
2344 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
2345 spin_unlock_irqrestore(&task->task_state_lock, flags);
2346
2347 memset(ts, 0, sizeof(*ts));
2348 ts->resp = SAS_TASK_COMPLETE;
2349
2350 if (unlikely(!sas_dev)) {
2351 dev_dbg(dev, "slot complete: port has no device\n");
2352 ts->stat = SAS_PHY_DOWN;
2353 goto out;
2354 }
2355
2356
2357 dw0 = le32_to_cpu(complete_hdr->dw0);
2358 switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >>
2359 CMPLT_HDR_ABORT_STAT_OFF) {
2360 case STAT_IO_ABORTED:
2361
2362 ts->stat = SAS_ABORTED_TASK;
2363 goto out;
2364 case STAT_IO_COMPLETE:
2365
2366 ts->stat = TMF_RESP_FUNC_SUCC;
2367 del_timer(&slot->internal_abort_timer);
2368 goto out;
2369 case STAT_IO_NO_DEVICE:
2370 ts->stat = TMF_RESP_FUNC_COMPLETE;
2371 del_timer(&slot->internal_abort_timer);
2372 goto out;
2373 case STAT_IO_NOT_VALID:
2374
2375
2376
2377 ts->stat = TMF_RESP_FUNC_FAILED;
2378 del_timer(&slot->internal_abort_timer);
2379 goto out;
2380 default:
2381 break;
2382 }
2383
2384 if ((dw0 & CMPLT_HDR_ERX_MSK) && (!(dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
2385 u32 err_phase = (dw0 & CMPLT_HDR_ERR_PHASE_MSK)
2386 >> CMPLT_HDR_ERR_PHASE_OFF;
2387 u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
2388
2389
2390 if (ERR_ON_TX_PHASE(err_phase))
2391 slot_err_v2_hw(hisi_hba, task, slot, 1);
2392 else if (ERR_ON_RX_PHASE(err_phase))
2393 slot_err_v2_hw(hisi_hba, task, slot, 2);
2394
2395 if (ts->stat != SAS_DATA_UNDERRUN)
2396 dev_info(dev, "erroneous completion iptt=%d task=%pK dev id=%d CQ hdr: 0x%x 0x%x 0x%x 0x%x Error info: 0x%x 0x%x 0x%x 0x%x\n",
2397 slot->idx, task, sas_dev->device_id,
2398 complete_hdr->dw0, complete_hdr->dw1,
2399 complete_hdr->act, complete_hdr->dw3,
2400 error_info[0], error_info[1],
2401 error_info[2], error_info[3]);
2402
2403 if (unlikely(slot->abort))
2404 return ts->stat;
2405 goto out;
2406 }
2407
2408 switch (task->task_proto) {
2409 case SAS_PROTOCOL_SSP:
2410 {
2411 struct hisi_sas_status_buffer *status_buffer =
2412 hisi_sas_status_buf_addr_mem(slot);
2413 struct ssp_response_iu *iu = (struct ssp_response_iu *)
2414 &status_buffer->iu[0];
2415
2416 sas_ssp_task_response(dev, task, iu);
2417 break;
2418 }
2419 case SAS_PROTOCOL_SMP:
2420 {
2421 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
2422 void *to = page_address(sg_page(sg_resp));
2423
2424 ts->stat = SAM_STAT_GOOD;
2425
2426 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
2427 DMA_TO_DEVICE);
2428 memcpy(to + sg_resp->offset,
2429 hisi_sas_status_buf_addr_mem(slot) +
2430 sizeof(struct hisi_sas_err_record),
2431 sg_resp->length);
2432 break;
2433 }
2434 case SAS_PROTOCOL_SATA:
2435 case SAS_PROTOCOL_STP:
2436 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2437 {
2438 ts->stat = SAM_STAT_GOOD;
2439 hisi_sas_sata_done(task, slot);
2440 break;
2441 }
2442 default:
2443 ts->stat = SAM_STAT_CHECK_CONDITION;
2444 break;
2445 }
2446
2447 if (!slot->port->port_attached) {
2448 dev_warn(dev, "slot complete: port %d has removed\n",
2449 slot->port->sas_port.id);
2450 ts->stat = SAS_PHY_DOWN;
2451 }
2452
2453 out:
2454 sts = ts->stat;
2455 spin_lock_irqsave(&task->task_state_lock, flags);
2456 if (task->task_state_flags & SAS_TASK_STATE_ABORTED) {
2457 spin_unlock_irqrestore(&task->task_state_lock, flags);
2458 dev_info(dev, "slot complete: task(%pK) aborted\n", task);
2459 return SAS_ABORTED_TASK;
2460 }
2461 task->task_state_flags |= SAS_TASK_STATE_DONE;
2462 spin_unlock_irqrestore(&task->task_state_lock, flags);
2463 hisi_sas_slot_task_free(hisi_hba, task, slot);
2464
2465 if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) {
2466 spin_lock_irqsave(&device->done_lock, flags);
2467 if (test_bit(SAS_HA_FROZEN, &ha->state)) {
2468 spin_unlock_irqrestore(&device->done_lock, flags);
2469 dev_info(dev, "slot complete: task(%pK) ignored\n",
2470 task);
2471 return sts;
2472 }
2473 spin_unlock_irqrestore(&device->done_lock, flags);
2474 }
2475
2476 if (task->task_done)
2477 task->task_done(task);
2478
2479 return sts;
2480 }
2481
2482 static void prep_ata_v2_hw(struct hisi_hba *hisi_hba,
2483 struct hisi_sas_slot *slot)
2484 {
2485 struct sas_task *task = slot->task;
2486 struct domain_device *device = task->dev;
2487 struct domain_device *parent_dev = device->parent;
2488 struct hisi_sas_device *sas_dev = device->lldd_dev;
2489 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2490 struct asd_sas_port *sas_port = device->port;
2491 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
2492 struct hisi_sas_tmf_task *tmf = slot->tmf;
2493 u8 *buf_cmd;
2494 int has_data = 0, hdr_tag = 0;
2495 u32 dw0, dw1 = 0, dw2 = 0;
2496
2497
2498
2499 dw0 = port->id << CMD_HDR_PORT_OFF;
2500 if (parent_dev && dev_is_expander(parent_dev->dev_type))
2501 dw0 |= 3 << CMD_HDR_CMD_OFF;
2502 else
2503 dw0 |= 4 << CMD_HDR_CMD_OFF;
2504
2505 if (tmf && tmf->force_phy) {
2506 dw0 |= CMD_HDR_FORCE_PHY_MSK;
2507 dw0 |= (1 << tmf->phy_id) << CMD_HDR_PHY_ID_OFF;
2508 }
2509
2510 hdr->dw0 = cpu_to_le32(dw0);
2511
2512
2513 switch (task->data_dir) {
2514 case DMA_TO_DEVICE:
2515 has_data = 1;
2516 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
2517 break;
2518 case DMA_FROM_DEVICE:
2519 has_data = 1;
2520 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
2521 break;
2522 default:
2523 dw1 &= ~CMD_HDR_DIR_MSK;
2524 }
2525
2526 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
2527 (task->ata_task.fis.control & ATA_SRST))
2528 dw1 |= 1 << CMD_HDR_RESET_OFF;
2529
2530 dw1 |= (hisi_sas_get_ata_protocol(
2531 &task->ata_task.fis, task->data_dir))
2532 << CMD_HDR_FRAME_TYPE_OFF;
2533 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
2534 hdr->dw1 = cpu_to_le32(dw1);
2535
2536
2537 if (task->ata_task.use_ncq) {
2538 struct ata_queued_cmd *qc = task->uldd_task;
2539
2540 hdr_tag = qc->tag;
2541 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
2542 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
2543 }
2544
2545 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
2546 2 << CMD_HDR_SG_MOD_OFF;
2547 hdr->dw2 = cpu_to_le32(dw2);
2548
2549
2550 hdr->transfer_tags = cpu_to_le32(slot->idx);
2551
2552 if (has_data)
2553 prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
2554 slot->n_elem);
2555
2556 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
2557 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
2558 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
2559
2560 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
2561
2562 if (likely(!task->ata_task.device_control_reg_update))
2563 task->ata_task.fis.flags |= 0x80;
2564
2565 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
2566 }
2567
2568 static void hisi_sas_internal_abort_quirk_timeout(struct timer_list *t)
2569 {
2570 struct hisi_sas_slot *slot = from_timer(slot, t, internal_abort_timer);
2571 struct hisi_sas_port *port = slot->port;
2572 struct asd_sas_port *asd_sas_port;
2573 struct asd_sas_phy *sas_phy;
2574
2575 if (!port)
2576 return;
2577
2578 asd_sas_port = &port->sas_port;
2579
2580
2581 list_for_each_entry(sas_phy, &asd_sas_port->phy_list, port_phy_el) {
2582 struct hisi_sas_phy *phy = sas_phy->lldd_phy;
2583 struct hisi_hba *hisi_hba = phy->hisi_hba;
2584 int phy_no = sas_phy->id;
2585 u32 link_dfx2;
2586
2587 link_dfx2 = hisi_sas_phy_read32(hisi_hba, phy_no, LINK_DFX2);
2588 if ((link_dfx2 == LINK_DFX2_RCVR_HOLD_STS_MSK) ||
2589 (link_dfx2 & LINK_DFX2_SEND_HOLD_STS_MSK)) {
2590 u32 txid_auto;
2591
2592 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no,
2593 TXID_AUTO);
2594 txid_auto |= TXID_AUTO_CTB_MSK;
2595 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2596 txid_auto);
2597 return;
2598 }
2599 }
2600 }
2601
2602 static void prep_abort_v2_hw(struct hisi_hba *hisi_hba,
2603 struct hisi_sas_slot *slot,
2604 int device_id, int abort_flag, int tag_to_abort)
2605 {
2606 struct sas_task *task = slot->task;
2607 struct domain_device *dev = task->dev;
2608 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
2609 struct hisi_sas_port *port = slot->port;
2610 struct timer_list *timer = &slot->internal_abort_timer;
2611
2612
2613 timer_setup(timer, hisi_sas_internal_abort_quirk_timeout, 0);
2614
2615 mod_timer(timer, jiffies + msecs_to_jiffies(100));
2616
2617
2618 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) |
2619 (port->id << CMD_HDR_PORT_OFF) |
2620 (dev_is_sata(dev) <<
2621 CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
2622 (abort_flag << CMD_HDR_ABORT_FLAG_OFF));
2623
2624
2625 hdr->dw1 = cpu_to_le32(device_id << CMD_HDR_DEV_ID_OFF);
2626
2627
2628 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
2629 hdr->transfer_tags = cpu_to_le32(slot->idx);
2630 }
2631
2632 static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2633 {
2634 int i, res = IRQ_HANDLED;
2635 u32 port_id, link_rate;
2636 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2637 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2638 struct device *dev = hisi_hba->dev;
2639 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
2640 struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
2641 unsigned long flags;
2642
2643 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
2644
2645 if (is_sata_phy_v2_hw(hisi_hba, phy_no))
2646 goto end;
2647
2648 del_timer(&phy->timer);
2649
2650 if (phy_no == 8) {
2651 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2652
2653 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
2654 PORT_STATE_PHY8_PORT_NUM_OFF;
2655 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
2656 PORT_STATE_PHY8_CONN_RATE_OFF;
2657 } else {
2658 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
2659 port_id = (port_id >> (4 * phy_no)) & 0xf;
2660 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
2661 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
2662 }
2663
2664 if (port_id == 0xf) {
2665 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
2666 res = IRQ_NONE;
2667 goto end;
2668 }
2669
2670 for (i = 0; i < 6; i++) {
2671 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
2672 RX_IDAF_DWORD0 + (i * 4));
2673 frame_rcvd[i] = __swab32(idaf);
2674 }
2675
2676 sas_phy->linkrate = link_rate;
2677 sas_phy->oob_mode = SAS_OOB_MODE;
2678 memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
2679 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
2680 phy->port_id = port_id;
2681 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
2682 phy->phy_type |= PORT_TYPE_SAS;
2683 phy->phy_attached = 1;
2684 phy->identify.device_type = id->dev_type;
2685 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
2686 if (phy->identify.device_type == SAS_END_DEVICE)
2687 phy->identify.target_port_protocols =
2688 SAS_PROTOCOL_SSP;
2689 else if (phy->identify.device_type != SAS_PHY_UNUSED) {
2690 phy->identify.target_port_protocols =
2691 SAS_PROTOCOL_SMP;
2692 if (!timer_pending(&hisi_hba->timer))
2693 set_link_timer_quirk(hisi_hba);
2694 }
2695 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
2696 spin_lock_irqsave(&phy->lock, flags);
2697 if (phy->reset_completion) {
2698 phy->in_reset = 0;
2699 complete(phy->reset_completion);
2700 }
2701 spin_unlock_irqrestore(&phy->lock, flags);
2702
2703 end:
2704 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2705 CHL_INT0_SL_PHY_ENABLE_MSK);
2706 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
2707
2708 return res;
2709 }
2710
2711 static bool check_any_wideports_v2_hw(struct hisi_hba *hisi_hba)
2712 {
2713 u32 port_state;
2714
2715 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
2716 if (port_state & 0x1ff)
2717 return true;
2718
2719 return false;
2720 }
2721
2722 static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2723 {
2724 u32 phy_state, sl_ctrl, txid_auto;
2725 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2726 struct hisi_sas_port *port = phy->port;
2727 struct device *dev = hisi_hba->dev;
2728
2729 del_timer(&phy->timer);
2730 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
2731
2732 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
2733 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
2734 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
2735
2736 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
2737 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
2738 sl_ctrl & ~SL_CONTROL_CTA_MSK);
2739 if (port && !get_wideport_bitmap_v2_hw(hisi_hba, port->id))
2740 if (!check_any_wideports_v2_hw(hisi_hba) &&
2741 timer_pending(&hisi_hba->timer))
2742 del_timer(&hisi_hba->timer);
2743
2744 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
2745 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
2746 txid_auto | TXID_AUTO_CT3_MSK);
2747
2748 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
2749 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
2750
2751 return IRQ_HANDLED;
2752 }
2753
2754 static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
2755 {
2756 struct hisi_hba *hisi_hba = p;
2757 u32 irq_msk;
2758 int phy_no = 0;
2759 irqreturn_t res = IRQ_NONE;
2760
2761 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
2762 >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
2763 while (irq_msk) {
2764 if (irq_msk & 1) {
2765 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
2766 CHL_INT0);
2767
2768 switch (reg_value & (CHL_INT0_NOT_RDY_MSK |
2769 CHL_INT0_SL_PHY_ENABLE_MSK)) {
2770
2771 case CHL_INT0_SL_PHY_ENABLE_MSK:
2772
2773 if (phy_up_v2_hw(phy_no, hisi_hba) ==
2774 IRQ_HANDLED)
2775 res = IRQ_HANDLED;
2776 break;
2777
2778 case CHL_INT0_NOT_RDY_MSK:
2779
2780 if (phy_down_v2_hw(phy_no, hisi_hba) ==
2781 IRQ_HANDLED)
2782 res = IRQ_HANDLED;
2783 break;
2784
2785 case (CHL_INT0_NOT_RDY_MSK |
2786 CHL_INT0_SL_PHY_ENABLE_MSK):
2787 reg_value = hisi_sas_read32(hisi_hba,
2788 PHY_STATE);
2789 if (reg_value & BIT(phy_no)) {
2790
2791 if (phy_up_v2_hw(phy_no, hisi_hba) ==
2792 IRQ_HANDLED)
2793 res = IRQ_HANDLED;
2794 } else {
2795
2796 if (phy_down_v2_hw(phy_no, hisi_hba) ==
2797 IRQ_HANDLED)
2798 res = IRQ_HANDLED;
2799 }
2800 break;
2801
2802 default:
2803 break;
2804 }
2805
2806 }
2807 irq_msk >>= 1;
2808 phy_no++;
2809 }
2810
2811 return res;
2812 }
2813
2814 static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
2815 {
2816 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2817 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2818 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
2819 u32 bcast_status;
2820
2821 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
2822 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
2823 if ((bcast_status & RX_BCAST_CHG_MSK) &&
2824 !test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags))
2825 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
2826 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
2827 CHL_INT0_SL_RX_BCST_ACK_MSK);
2828 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
2829 }
2830
2831 static const struct hisi_sas_hw_error port_ecc_axi_error[] = {
2832 {
2833 .irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_ERR_OFF),
2834 .msg = "dmac_tx_ecc_bad_err",
2835 },
2836 {
2837 .irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_ERR_OFF),
2838 .msg = "dmac_rx_ecc_bad_err",
2839 },
2840 {
2841 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
2842 .msg = "dma_tx_axi_wr_err",
2843 },
2844 {
2845 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
2846 .msg = "dma_tx_axi_rd_err",
2847 },
2848 {
2849 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
2850 .msg = "dma_rx_axi_wr_err",
2851 },
2852 {
2853 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
2854 .msg = "dma_rx_axi_rd_err",
2855 },
2856 };
2857
2858 static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
2859 {
2860 struct hisi_hba *hisi_hba = p;
2861 struct device *dev = hisi_hba->dev;
2862 u32 ent_msk, ent_tmp, irq_msk;
2863 int phy_no = 0;
2864
2865 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2866 ent_tmp = ent_msk;
2867 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
2868 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
2869
2870 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >>
2871 HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff;
2872
2873 while (irq_msk) {
2874 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
2875 CHL_INT0);
2876 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
2877 CHL_INT1);
2878 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
2879 CHL_INT2);
2880
2881 if ((irq_msk & (1 << phy_no)) && irq_value1) {
2882 int i;
2883
2884 for (i = 0; i < ARRAY_SIZE(port_ecc_axi_error); i++) {
2885 const struct hisi_sas_hw_error *error =
2886 &port_ecc_axi_error[i];
2887
2888 if (!(irq_value1 & error->irq_msk))
2889 continue;
2890
2891 dev_warn(dev, "%s error (phy%d 0x%x) found!\n",
2892 error->msg, phy_no, irq_value1);
2893 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2894 }
2895
2896 hisi_sas_phy_write32(hisi_hba, phy_no,
2897 CHL_INT1, irq_value1);
2898 }
2899
2900 if ((irq_msk & (1 << phy_no)) && irq_value2) {
2901 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2902
2903 if (irq_value2 & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
2904 dev_warn(dev, "phy%d identify timeout\n",
2905 phy_no);
2906 hisi_sas_notify_phy_event(phy,
2907 HISI_PHYE_LINK_RESET);
2908 }
2909
2910 hisi_sas_phy_write32(hisi_hba, phy_no,
2911 CHL_INT2, irq_value2);
2912 }
2913
2914 if ((irq_msk & (1 << phy_no)) && irq_value0) {
2915 if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
2916 phy_bcast_v2_hw(phy_no, hisi_hba);
2917
2918 if (irq_value0 & CHL_INT0_PHY_RDY_MSK)
2919 hisi_sas_phy_oob_ready(hisi_hba, phy_no);
2920
2921 hisi_sas_phy_write32(hisi_hba, phy_no,
2922 CHL_INT0, irq_value0
2923 & (~CHL_INT0_HOTPLUG_TOUT_MSK)
2924 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
2925 & (~CHL_INT0_NOT_RDY_MSK));
2926 }
2927 irq_msk &= ~(1 << phy_no);
2928 phy_no++;
2929 }
2930
2931 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
2932
2933 return IRQ_HANDLED;
2934 }
2935
2936 static void
2937 one_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba, u32 irq_value)
2938 {
2939 struct device *dev = hisi_hba->dev;
2940 const struct hisi_sas_hw_error *ecc_error;
2941 u32 val;
2942 int i;
2943
2944 for (i = 0; i < ARRAY_SIZE(one_bit_ecc_errors); i++) {
2945 ecc_error = &one_bit_ecc_errors[i];
2946 if (irq_value & ecc_error->irq_msk) {
2947 val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2948 val &= ecc_error->msk;
2949 val >>= ecc_error->shift;
2950 dev_warn(dev, "%s found: mem addr is 0x%08X\n",
2951 ecc_error->msg, val);
2952 }
2953 }
2954 }
2955
2956 static void multi_bit_ecc_error_process_v2_hw(struct hisi_hba *hisi_hba,
2957 u32 irq_value)
2958 {
2959 struct device *dev = hisi_hba->dev;
2960 const struct hisi_sas_hw_error *ecc_error;
2961 u32 val;
2962 int i;
2963
2964 for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) {
2965 ecc_error = &multi_bit_ecc_errors[i];
2966 if (irq_value & ecc_error->irq_msk) {
2967 val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2968 val &= ecc_error->msk;
2969 val >>= ecc_error->shift;
2970 dev_err(dev, "%s (0x%x) found: mem addr is 0x%08X\n",
2971 ecc_error->msg, irq_value, val);
2972 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2973 }
2974 }
2975
2976 return;
2977 }
2978
2979 static irqreturn_t fatal_ecc_int_v2_hw(int irq_no, void *p)
2980 {
2981 struct hisi_hba *hisi_hba = p;
2982 u32 irq_value, irq_msk;
2983
2984 irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
2985 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk | 0xffffffff);
2986
2987 irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
2988 if (irq_value) {
2989 one_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
2990 multi_bit_ecc_error_process_v2_hw(hisi_hba, irq_value);
2991 }
2992
2993 hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
2994 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
2995
2996 return IRQ_HANDLED;
2997 }
2998
2999 static const struct hisi_sas_hw_error axi_error[] = {
3000 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
3001 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
3002 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
3003 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
3004 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
3005 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
3006 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
3007 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
3008 {}
3009 };
3010
3011 static const struct hisi_sas_hw_error fifo_error[] = {
3012 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" },
3013 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" },
3014 { .msk = BIT(10), .msg = "GETDQE_FIFO" },
3015 { .msk = BIT(11), .msg = "CMDP_FIFO" },
3016 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
3017 {}
3018 };
3019
3020 static const struct hisi_sas_hw_error fatal_axi_errors[] = {
3021 {
3022 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
3023 .msg = "write pointer and depth",
3024 },
3025 {
3026 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
3027 .msg = "iptt no match slot",
3028 },
3029 {
3030 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
3031 .msg = "read pointer and depth",
3032 },
3033 {
3034 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
3035 .reg = HGC_AXI_FIFO_ERR_INFO,
3036 .sub = axi_error,
3037 },
3038 {
3039 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
3040 .reg = HGC_AXI_FIFO_ERR_INFO,
3041 .sub = fifo_error,
3042 },
3043 {
3044 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
3045 .msg = "LM add/fetch list",
3046 },
3047 {
3048 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
3049 .msg = "SAS_HGC_ABT fetch LM list",
3050 },
3051 };
3052
3053 static irqreturn_t fatal_axi_int_v2_hw(int irq_no, void *p)
3054 {
3055 struct hisi_hba *hisi_hba = p;
3056 u32 irq_value, irq_msk, err_value;
3057 struct device *dev = hisi_hba->dev;
3058 const struct hisi_sas_hw_error *axi_error;
3059 int i;
3060
3061 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
3062 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0xfffffffe);
3063
3064 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
3065
3066 for (i = 0; i < ARRAY_SIZE(fatal_axi_errors); i++) {
3067 axi_error = &fatal_axi_errors[i];
3068 if (!(irq_value & axi_error->irq_msk))
3069 continue;
3070
3071 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
3072 1 << axi_error->shift);
3073 if (axi_error->sub) {
3074 const struct hisi_sas_hw_error *sub = axi_error->sub;
3075
3076 err_value = hisi_sas_read32(hisi_hba, axi_error->reg);
3077 for (; sub->msk || sub->msg; sub++) {
3078 if (!(err_value & sub->msk))
3079 continue;
3080 dev_err(dev, "%s (0x%x) found!\n",
3081 sub->msg, irq_value);
3082 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3083 }
3084 } else {
3085 dev_err(dev, "%s (0x%x) found!\n",
3086 axi_error->msg, irq_value);
3087 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
3088 }
3089 }
3090
3091 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
3092 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
3093 u32 dev_id = reg_val & ITCT_DEV_MSK;
3094 struct hisi_sas_device *sas_dev = &hisi_hba->devices[dev_id];
3095
3096 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
3097 dev_dbg(dev, "clear ITCT ok\n");
3098 complete(sas_dev->completion);
3099 }
3100
3101 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value);
3102 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
3103
3104 return IRQ_HANDLED;
3105 }
3106
3107 static void cq_tasklet_v2_hw(unsigned long val)
3108 {
3109 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
3110 struct hisi_hba *hisi_hba = cq->hisi_hba;
3111 struct hisi_sas_slot *slot;
3112 struct hisi_sas_itct *itct;
3113 struct hisi_sas_complete_v2_hdr *complete_queue;
3114 u32 rd_point = cq->rd_point, wr_point, dev_id;
3115 int queue = cq->id;
3116
3117 if (unlikely(hisi_hba->reject_stp_links_msk))
3118 phys_try_accept_stp_links_v2_hw(hisi_hba);
3119
3120 complete_queue = hisi_hba->complete_hdr[queue];
3121
3122 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
3123 (0x14 * queue));
3124
3125 while (rd_point != wr_point) {
3126 struct hisi_sas_complete_v2_hdr *complete_hdr;
3127 int iptt;
3128
3129 complete_hdr = &complete_queue[rd_point];
3130
3131
3132 if (complete_hdr->act) {
3133 u32 act_tmp = le32_to_cpu(complete_hdr->act);
3134 int ncq_tag_count = ffs(act_tmp);
3135 u32 dw1 = le32_to_cpu(complete_hdr->dw1);
3136
3137 dev_id = (dw1 & CMPLT_HDR_DEV_ID_MSK) >>
3138 CMPLT_HDR_DEV_ID_OFF;
3139 itct = &hisi_hba->itct[dev_id];
3140
3141
3142 while (ncq_tag_count) {
3143 __le64 *_ncq_tag = &itct->qw4_15[0], __ncq_tag;
3144 u64 ncq_tag;
3145
3146 ncq_tag_count--;
3147 __ncq_tag = _ncq_tag[ncq_tag_count / 5];
3148 ncq_tag = le64_to_cpu(__ncq_tag);
3149 iptt = (ncq_tag >> (ncq_tag_count % 5) * 12) &
3150 0xfff;
3151
3152 slot = &hisi_hba->slot_info[iptt];
3153 slot->cmplt_queue_slot = rd_point;
3154 slot->cmplt_queue = queue;
3155 slot_complete_v2_hw(hisi_hba, slot);
3156
3157 act_tmp &= ~(1 << ncq_tag_count);
3158 ncq_tag_count = ffs(act_tmp);
3159 }
3160 } else {
3161 u32 dw1 = le32_to_cpu(complete_hdr->dw1);
3162
3163 iptt = dw1 & CMPLT_HDR_IPTT_MSK;
3164 slot = &hisi_hba->slot_info[iptt];
3165 slot->cmplt_queue_slot = rd_point;
3166 slot->cmplt_queue = queue;
3167 slot_complete_v2_hw(hisi_hba, slot);
3168 }
3169
3170 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
3171 rd_point = 0;
3172 }
3173
3174
3175 cq->rd_point = rd_point;
3176 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
3177 }
3178
3179 static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
3180 {
3181 struct hisi_sas_cq *cq = p;
3182 struct hisi_hba *hisi_hba = cq->hisi_hba;
3183 int queue = cq->id;
3184
3185 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
3186
3187 tasklet_schedule(&cq->tasklet);
3188
3189 return IRQ_HANDLED;
3190 }
3191
3192 static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
3193 {
3194 struct hisi_sas_phy *phy = p;
3195 struct hisi_hba *hisi_hba = phy->hisi_hba;
3196 struct asd_sas_phy *sas_phy = &phy->sas_phy;
3197 struct device *dev = hisi_hba->dev;
3198 struct hisi_sas_initial_fis *initial_fis;
3199 struct dev_to_host_fis *fis;
3200 u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate;
3201 irqreturn_t res = IRQ_HANDLED;
3202 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
3203 unsigned long flags;
3204 int phy_no, offset;
3205
3206 del_timer(&phy->timer);
3207
3208 phy_no = sas_phy->id;
3209 initial_fis = &hisi_hba->initial_fis[phy_no];
3210 fis = &initial_fis->fis;
3211
3212 offset = 4 * (phy_no / 4);
3213 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1 + offset);
3214 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset,
3215 ent_msk | 1 << ((phy_no % 4) * 8));
3216
3217 ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1 + offset);
3218 ent_tmp = ent_int & (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF *
3219 (phy_no % 4)));
3220 ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4);
3221 if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) {
3222 dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no);
3223 res = IRQ_NONE;
3224 goto end;
3225 }
3226
3227
3228 if (fis->status & ATA_ERR) {
3229 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", phy_no,
3230 fis->status);
3231 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
3232 res = IRQ_NONE;
3233 goto end;
3234 }
3235
3236 if (unlikely(phy_no == 8)) {
3237 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
3238
3239 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
3240 PORT_STATE_PHY8_PORT_NUM_OFF;
3241 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
3242 PORT_STATE_PHY8_CONN_RATE_OFF;
3243 } else {
3244 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
3245 port_id = (port_id >> (4 * phy_no)) & 0xf;
3246 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
3247 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
3248 }
3249
3250 if (port_id == 0xf) {
3251 dev_err(dev, "sata int: phy%d invalid portid\n", phy_no);
3252 res = IRQ_NONE;
3253 goto end;
3254 }
3255
3256 sas_phy->linkrate = link_rate;
3257 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
3258 HARD_PHY_LINKRATE);
3259 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
3260 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
3261
3262 sas_phy->oob_mode = SATA_OOB_MODE;
3263
3264 attached_sas_addr[0] = 0x50;
3265 attached_sas_addr[6] = hisi_hba->shost->host_no;
3266 attached_sas_addr[7] = phy_no;
3267 memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE);
3268 memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis));
3269 dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate);
3270 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
3271 phy->port_id = port_id;
3272 phy->phy_type |= PORT_TYPE_SATA;
3273 phy->phy_attached = 1;
3274 phy->identify.device_type = SAS_SATA_DEV;
3275 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3276 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3277 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP);
3278
3279 spin_lock_irqsave(&phy->lock, flags);
3280 if (phy->reset_completion) {
3281 phy->in_reset = 0;
3282 complete(phy->reset_completion);
3283 }
3284 spin_unlock_irqrestore(&phy->lock, flags);
3285 end:
3286 hisi_sas_write32(hisi_hba, ENT_INT_SRC1 + offset, ent_tmp);
3287 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, ent_msk);
3288
3289 return res;
3290 }
3291
3292 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
3293 int_phy_updown_v2_hw,
3294 int_chnl_int_v2_hw,
3295 };
3296
3297 static irq_handler_t fatal_interrupts[HISI_SAS_FATAL_INT_NR] = {
3298 fatal_ecc_int_v2_hw,
3299 fatal_axi_int_v2_hw
3300 };
3301
3302
3303
3304
3305
3306 static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
3307 {
3308 struct platform_device *pdev = hisi_hba->platform_dev;
3309 struct device *dev = &pdev->dev;
3310 int irq, rc = 0, irq_map[128];
3311 int i, phy_no, fatal_no, queue_no;
3312
3313 for (i = 0; i < 128; i++)
3314 irq_map[i] = platform_get_irq(pdev, i);
3315
3316 for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
3317 irq = irq_map[i + 1];
3318 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
3319 DRV_NAME " phy", hisi_hba);
3320 if (rc) {
3321 dev_err(dev, "irq init: could not request phy interrupt %d, rc=%d\n",
3322 irq, rc);
3323 rc = -ENOENT;
3324 goto err_out;
3325 }
3326 }
3327
3328 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
3329 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
3330
3331 irq = irq_map[phy_no + 72];
3332 rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0,
3333 DRV_NAME " sata", phy);
3334 if (rc) {
3335 dev_err(dev, "irq init: could not request sata interrupt %d, rc=%d\n",
3336 irq, rc);
3337 rc = -ENOENT;
3338 goto err_out;
3339 }
3340 }
3341
3342 for (fatal_no = 0; fatal_no < HISI_SAS_FATAL_INT_NR; fatal_no++) {
3343 irq = irq_map[fatal_no + 81];
3344 rc = devm_request_irq(dev, irq, fatal_interrupts[fatal_no], 0,
3345 DRV_NAME " fatal", hisi_hba);
3346 if (rc) {
3347 dev_err(dev, "irq init: could not request fatal interrupt %d, rc=%d\n",
3348 irq, rc);
3349 rc = -ENOENT;
3350 goto err_out;
3351 }
3352 }
3353
3354 for (queue_no = 0; queue_no < hisi_hba->queue_count; queue_no++) {
3355 struct hisi_sas_cq *cq = &hisi_hba->cq[queue_no];
3356 struct tasklet_struct *t = &cq->tasklet;
3357
3358 irq = irq_map[queue_no + 96];
3359 rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0,
3360 DRV_NAME " cq", cq);
3361 if (rc) {
3362 dev_err(dev, "irq init: could not request cq interrupt %d, rc=%d\n",
3363 irq, rc);
3364 rc = -ENOENT;
3365 goto err_out;
3366 }
3367 tasklet_init(t, cq_tasklet_v2_hw, (unsigned long)cq);
3368 }
3369
3370 hisi_hba->cq_nvecs = hisi_hba->queue_count;
3371
3372 err_out:
3373 return rc;
3374 }
3375
3376 static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
3377 {
3378 int rc;
3379
3380 memset(hisi_hba->sata_dev_bitmap, 0, sizeof(hisi_hba->sata_dev_bitmap));
3381
3382 rc = hw_init_v2_hw(hisi_hba);
3383 if (rc)
3384 return rc;
3385
3386 rc = interrupt_init_v2_hw(hisi_hba);
3387 if (rc)
3388 return rc;
3389
3390 return 0;
3391 }
3392
3393 static void interrupt_disable_v2_hw(struct hisi_hba *hisi_hba)
3394 {
3395 struct platform_device *pdev = hisi_hba->platform_dev;
3396 int i;
3397
3398 for (i = 0; i < hisi_hba->queue_count; i++)
3399 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
3400
3401 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
3402 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
3403 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
3404 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
3405
3406 for (i = 0; i < hisi_hba->n_phy; i++) {
3407 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
3408 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
3409 }
3410
3411 for (i = 0; i < 128; i++)
3412 synchronize_irq(platform_get_irq(pdev, i));
3413 }
3414
3415
3416 static u32 get_phys_state_v2_hw(struct hisi_hba *hisi_hba)
3417 {
3418 return hisi_sas_read32(hisi_hba, PHY_STATE);
3419 }
3420
3421 static int soft_reset_v2_hw(struct hisi_hba *hisi_hba)
3422 {
3423 struct device *dev = hisi_hba->dev;
3424 int rc, cnt;
3425
3426 interrupt_disable_v2_hw(hisi_hba);
3427 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
3428 hisi_sas_kill_tasklets(hisi_hba);
3429
3430 hisi_sas_stop_phys(hisi_hba);
3431
3432 mdelay(10);
3433
3434 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
3435
3436
3437 cnt = 0;
3438 while (1) {
3439 u32 status = hisi_sas_read32_relaxed(hisi_hba,
3440 AXI_MASTER_CFG_BASE + AM_CURR_TRANS_RETURN);
3441
3442 if (status == 0x3)
3443 break;
3444
3445 udelay(10);
3446 if (cnt++ > 10) {
3447 dev_err(dev, "wait axi bus state to idle timeout!\n");
3448 return -1;
3449 }
3450 }
3451
3452 hisi_sas_init_mem(hisi_hba);
3453
3454 rc = hw_init_v2_hw(hisi_hba);
3455 if (rc)
3456 return rc;
3457
3458 phys_reject_stp_links_v2_hw(hisi_hba);
3459
3460 return 0;
3461 }
3462
3463 static int write_gpio_v2_hw(struct hisi_hba *hisi_hba, u8 reg_type,
3464 u8 reg_index, u8 reg_count, u8 *write_data)
3465 {
3466 struct device *dev = hisi_hba->dev;
3467 int phy_no, count;
3468
3469 if (!hisi_hba->sgpio_regs)
3470 return -EOPNOTSUPP;
3471
3472 switch (reg_type) {
3473 case SAS_GPIO_REG_TX:
3474 count = reg_count * 4;
3475 count = min(count, hisi_hba->n_phy);
3476
3477 for (phy_no = 0; phy_no < count; phy_no++) {
3478
3479
3480
3481
3482
3483
3484 void __iomem *reg_addr = hisi_hba->sgpio_regs +
3485 reg_index * 4 + phy_no;
3486 int data_idx = phy_no + 3 - (phy_no % 4) * 2;
3487
3488 writeb(write_data[data_idx], reg_addr);
3489 }
3490
3491 break;
3492 default:
3493 dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
3494 reg_type);
3495 return -EINVAL;
3496 }
3497
3498 return 0;
3499 }
3500
3501 static void wait_cmds_complete_timeout_v2_hw(struct hisi_hba *hisi_hba,
3502 int delay_ms, int timeout_ms)
3503 {
3504 struct device *dev = hisi_hba->dev;
3505 int entries, entries_old = 0, time;
3506
3507 for (time = 0; time < timeout_ms; time += delay_ms) {
3508 entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT);
3509 if (entries == entries_old)
3510 break;
3511
3512 entries_old = entries;
3513 msleep(delay_ms);
3514 }
3515
3516 if (time >= timeout_ms) {
3517 dev_dbg(dev, "Wait commands complete timeout!\n");
3518 return;
3519 }
3520
3521 dev_dbg(dev, "wait commands complete %dms\n", time);
3522
3523 }
3524
3525 static struct device_attribute *host_attrs_v2_hw[] = {
3526 &dev_attr_phy_event_threshold,
3527 NULL
3528 };
3529
3530 static struct scsi_host_template sht_v2_hw = {
3531 .name = DRV_NAME,
3532 .module = THIS_MODULE,
3533 .queuecommand = sas_queuecommand,
3534 .target_alloc = sas_target_alloc,
3535 .slave_configure = hisi_sas_slave_configure,
3536 .scan_finished = hisi_sas_scan_finished,
3537 .scan_start = hisi_sas_scan_start,
3538 .change_queue_depth = sas_change_queue_depth,
3539 .bios_param = sas_bios_param,
3540 .this_id = -1,
3541 .sg_tablesize = HISI_SAS_SGE_PAGE_CNT,
3542 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
3543 .eh_device_reset_handler = sas_eh_device_reset_handler,
3544 .eh_target_reset_handler = sas_eh_target_reset_handler,
3545 .target_destroy = sas_target_destroy,
3546 .ioctl = sas_ioctl,
3547 .shost_attrs = host_attrs_v2_hw,
3548 .host_reset = hisi_sas_host_reset,
3549 };
3550
3551 static const struct hisi_sas_hw hisi_sas_v2_hw = {
3552 .hw_init = hisi_sas_v2_init,
3553 .setup_itct = setup_itct_v2_hw,
3554 .slot_index_alloc = slot_index_alloc_quirk_v2_hw,
3555 .alloc_dev = alloc_dev_quirk_v2_hw,
3556 .sl_notify_ssp = sl_notify_ssp_v2_hw,
3557 .get_wideport_bitmap = get_wideport_bitmap_v2_hw,
3558 .clear_itct = clear_itct_v2_hw,
3559 .free_device = free_device_v2_hw,
3560 .prep_smp = prep_smp_v2_hw,
3561 .prep_ssp = prep_ssp_v2_hw,
3562 .prep_stp = prep_ata_v2_hw,
3563 .prep_abort = prep_abort_v2_hw,
3564 .start_delivery = start_delivery_v2_hw,
3565 .phys_init = phys_init_v2_hw,
3566 .phy_start = start_phy_v2_hw,
3567 .phy_disable = disable_phy_v2_hw,
3568 .phy_hard_reset = phy_hard_reset_v2_hw,
3569 .get_events = phy_get_events_v2_hw,
3570 .phy_set_linkrate = phy_set_linkrate_v2_hw,
3571 .phy_get_max_linkrate = phy_get_max_linkrate_v2_hw,
3572 .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
3573 .soft_reset = soft_reset_v2_hw,
3574 .get_phys_state = get_phys_state_v2_hw,
3575 .write_gpio = write_gpio_v2_hw,
3576 .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v2_hw,
3577 .sht = &sht_v2_hw,
3578 };
3579
3580 static int hisi_sas_v2_probe(struct platform_device *pdev)
3581 {
3582
3583
3584
3585
3586 int ret = platform_get_irq(pdev, 0);
3587
3588 if (ret < 0) {
3589 if (ret != -EPROBE_DEFER)
3590 dev_err(&pdev->dev, "cannot obtain irq\n");
3591 return ret;
3592 }
3593
3594 return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
3595 }
3596
3597 static int hisi_sas_v2_remove(struct platform_device *pdev)
3598 {
3599 struct sas_ha_struct *sha = platform_get_drvdata(pdev);
3600 struct hisi_hba *hisi_hba = sha->lldd_ha;
3601
3602 hisi_sas_kill_tasklets(hisi_hba);
3603
3604 return hisi_sas_remove(pdev);
3605 }
3606
3607 static const struct of_device_id sas_v2_of_match[] = {
3608 { .compatible = "hisilicon,hip06-sas-v2",},
3609 { .compatible = "hisilicon,hip07-sas-v2",},
3610 {},
3611 };
3612 MODULE_DEVICE_TABLE(of, sas_v2_of_match);
3613
3614 static const struct acpi_device_id sas_v2_acpi_match[] = {
3615 { "HISI0162", 0 },
3616 { }
3617 };
3618
3619 MODULE_DEVICE_TABLE(acpi, sas_v2_acpi_match);
3620
3621 static struct platform_driver hisi_sas_v2_driver = {
3622 .probe = hisi_sas_v2_probe,
3623 .remove = hisi_sas_v2_remove,
3624 .driver = {
3625 .name = DRV_NAME,
3626 .of_match_table = sas_v2_of_match,
3627 .acpi_match_table = ACPI_PTR(sas_v2_acpi_match),
3628 },
3629 };
3630
3631 module_platform_driver(hisi_sas_v2_driver);
3632
3633 MODULE_LICENSE("GPL");
3634 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
3635 MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
3636 MODULE_ALIAS("platform:" DRV_NAME);