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8 #ifndef __QL483XX_H
9 #define __QL483XX_H
10
11
12 #define QLA83XX_FLASH_SPI_STATUS 0x2808E010
13 #define QLA83XX_FLASH_SPI_CONTROL 0x2808E014
14 #define QLA83XX_FLASH_STATUS 0x42100004
15 #define QLA83XX_FLASH_CONTROL 0x42110004
16 #define QLA83XX_FLASH_ADDR 0x42110008
17 #define QLA83XX_FLASH_WRDATA 0x4211000C
18 #define QLA83XX_FLASH_RDDATA 0x42110018
19 #define QLA83XX_FLASH_DIRECT_WINDOW 0x42110030
20 #define QLA83XX_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA))
21
22
23
24
25 #define QLA83XX_FLASH_LOCK 0x3850
26 #define QLA83XX_FLASH_UNLOCK 0x3854
27 #define QLA83XX_FLASH_LOCK_ID 0x3500
28
29
30 #define QLA83XX_DRV_LOCK 0x3868
31 #define QLA83XX_DRV_UNLOCK 0x386C
32 #define QLA83XX_DRV_LOCK_ID 0x3504
33 #define QLA83XX_DRV_LOCKRECOVERY 0x379C
34
35
36 #define QLA83XX_IDC_VER_MAJ_VALUE 0x1
37 #define QLA83XX_IDC_VER_MIN_VALUE 0x0
38
39
40 #define QLA83XX_CRB_IDC_VER_MAJOR 0x3780
41 #define QLA83XX_CRB_IDC_VER_MINOR 0x3798
42 #define QLA83XX_IDC_DRV_CTRL 0x3790
43 #define QLA83XX_IDC_DRV_AUDIT 0x3794
44 #define QLA83XX_SRE_SHIM_CONTROL 0x0D200284
45 #define QLA83XX_PORT0_RXB_PAUSE_THRS 0x0B2003A4
46 #define QLA83XX_PORT1_RXB_PAUSE_THRS 0x0B2013A4
47 #define QLA83XX_PORT0_RXB_TC_MAX_CELL 0x0B200388
48 #define QLA83XX_PORT1_RXB_TC_MAX_CELL 0x0B201388
49 #define QLA83XX_PORT0_RXB_TC_STATS 0x0B20039C
50 #define QLA83XX_PORT1_RXB_TC_STATS 0x0B20139C
51 #define QLA83XX_PORT2_IFB_PAUSE_THRS 0x0B200704
52 #define QLA83XX_PORT3_IFB_PAUSE_THRS 0x0B201704
53
54
55 #define QLA83XX_SET_PAUSE_VAL 0x0
56 #define QLA83XX_SET_TC_MAX_CELL_VAL 0x03FF03FF
57
58 #define QLA83XX_RESET_CONTROL 0x28084E50
59 #define QLA83XX_RESET_REG 0x28084E60
60 #define QLA83XX_RESET_PORT0 0x28084E70
61 #define QLA83XX_RESET_PORT1 0x28084E80
62 #define QLA83XX_RESET_PORT2 0x28084E90
63 #define QLA83XX_RESET_PORT3 0x28084EA0
64 #define QLA83XX_RESET_SRE_SHIM 0x28084EB0
65 #define QLA83XX_RESET_EPG_SHIM 0x28084EC0
66 #define QLA83XX_RESET_ETHER_PCS 0x28084ED0
67
68
69 #define QLA83XX_PEG_HALT_STATUS1 0x34A8
70 #define QLA83XX_PEG_HALT_STATUS2 0x34AC
71 #define QLA83XX_PEG_ALIVE_COUNTER 0x34B0
72 #define QLA83XX_FW_CAPABILITIES 0x3528
73 #define QLA83XX_CRB_DRV_ACTIVE 0x3788
74 #define QLA83XX_CRB_DEV_STATE 0x3784
75 #define QLA83XX_CRB_DRV_STATE 0x378C
76 #define QLA83XX_CRB_DRV_SCRATCH 0x3548
77 #define QLA83XX_CRB_DEV_PART_INFO1 0x37E0
78 #define QLA83XX_CRB_DEV_PART_INFO2 0x37E4
79
80 #define QLA83XX_FW_VER_MAJOR 0x3550
81 #define QLA83XX_FW_VER_MINOR 0x3554
82 #define QLA83XX_FW_VER_SUB 0x3558
83 #define QLA83XX_NPAR_STATE 0x359C
84 #define QLA83XX_FW_IMAGE_VALID 0x35FC
85 #define QLA83XX_CMDPEG_STATE 0x3650
86 #define QLA83XX_ASIC_TEMP 0x37B4
87 #define QLA83XX_FW_API 0x356C
88 #define QLA83XX_DRV_OP_MODE 0x3570
89
90 static const uint32_t qla4_83xx_reg_tbl[] = {
91 QLA83XX_PEG_HALT_STATUS1,
92 QLA83XX_PEG_HALT_STATUS2,
93 QLA83XX_PEG_ALIVE_COUNTER,
94 QLA83XX_CRB_DRV_ACTIVE,
95 QLA83XX_CRB_DEV_STATE,
96 QLA83XX_CRB_DRV_STATE,
97 QLA83XX_CRB_DRV_SCRATCH,
98 QLA83XX_CRB_DEV_PART_INFO1,
99 QLA83XX_CRB_IDC_VER_MAJOR,
100 QLA83XX_FW_VER_MAJOR,
101 QLA83XX_FW_VER_MINOR,
102 QLA83XX_FW_VER_SUB,
103 QLA83XX_CMDPEG_STATE,
104 QLA83XX_ASIC_TEMP,
105 };
106
107 #define QLA83XX_CRB_WIN_BASE 0x3800
108 #define QLA83XX_CRB_WIN_FUNC(f) (QLA83XX_CRB_WIN_BASE+((f)*4))
109 #define QLA83XX_SEM_LOCK_BASE 0x3840
110 #define QLA83XX_SEM_UNLOCK_BASE 0x3844
111 #define QLA83XX_SEM_LOCK_FUNC(f) (QLA83XX_SEM_LOCK_BASE+((f)*8))
112 #define QLA83XX_SEM_UNLOCK_FUNC(f) (QLA83XX_SEM_UNLOCK_BASE+((f)*8))
113 #define QLA83XX_LINK_STATE(f) (0x3698+((f) > 7 ? 4 : 0))
114 #define QLA83XX_LINK_SPEED(f) (0x36E0+(((f) >> 2) * 4))
115 #define QLA83XX_MAX_LINK_SPEED(f) (0x36F0+(((f) / 4) * 4))
116 #define QLA83XX_LINK_SPEED_FACTOR 10
117
118
119 #define QLA83xx_FLASH_MAX_WAIT_USEC 100
120 #define QLA83XX_FLASH_LOCK_TIMEOUT 10000
121 #define QLA83XX_FLASH_SECTOR_SIZE 65536
122 #define QLA83XX_DRV_LOCK_TIMEOUT 2000
123 #define QLA83XX_FLASH_SECTOR_ERASE_CMD 0xdeadbeef
124 #define QLA83XX_FLASH_WRITE_CMD 0xdacdacda
125 #define QLA83XX_FLASH_BUFFER_WRITE_CMD 0xcadcadca
126 #define QLA83XX_FLASH_READ_RETRY_COUNT 2000
127 #define QLA83XX_FLASH_STATUS_READY 0x6
128 #define QLA83XX_FLASH_BUFFER_WRITE_MIN 2
129 #define QLA83XX_FLASH_BUFFER_WRITE_MAX 64
130 #define QLA83XX_FLASH_STATUS_REG_POLL_DELAY 1
131 #define QLA83XX_ERASE_MODE 1
132 #define QLA83XX_WRITE_MODE 2
133 #define QLA83XX_DWORD_WRITE_MODE 3
134
135 #define QLA83XX_GLOBAL_RESET 0x38CC
136 #define QLA83XX_WILDCARD 0x38F0
137 #define QLA83XX_INFORMANT 0x38FC
138 #define QLA83XX_HOST_MBX_CTRL 0x3038
139 #define QLA83XX_FW_MBX_CTRL 0x303C
140 #define QLA83XX_BOOTLOADER_ADDR 0x355C
141 #define QLA83XX_BOOTLOADER_SIZE 0x3560
142 #define QLA83XX_FW_IMAGE_ADDR 0x3564
143 #define QLA83XX_MBX_INTR_ENABLE 0x1000
144 #define QLA83XX_MBX_INTR_MASK 0x1200
145
146
147 #define DONTRESET_BIT0 0x1
148 #define GRACEFUL_RESET_BIT1 0x2
149
150 #define QLA83XX_HALT_STATUS_INFORMATIONAL (0x1 << 29)
151 #define QLA83XX_HALT_STATUS_FW_RESET (0x2 << 29)
152 #define QLA83XX_HALT_STATUS_UNRECOVERABLE (0x4 << 29)
153
154
155 #define QLA83XX_BOOTLOADER_FLASH_ADDR 0x10000
156 #define QLA83XX_BOOT_FROM_FLASH 0
157
158 #define QLA83XX_IDC_PARAM_ADDR 0x3e8020
159
160 #define QLA83XX_MAX_RESET_SEQ_ENTRIES 16
161 #define QLA83XX_RESTART_TEMPLATE_SIZE 0x2000
162 #define QLA83XX_RESET_TEMPLATE_ADDR 0x4F0000
163 #define QLA83XX_RESET_SEQ_VERSION 0x0101
164
165
166 #define OPCODE_NOP 0x0000
167 #define OPCODE_WRITE_LIST 0x0001
168 #define OPCODE_READ_WRITE_LIST 0x0002
169 #define OPCODE_POLL_LIST 0x0004
170 #define OPCODE_POLL_WRITE_LIST 0x0008
171 #define OPCODE_READ_MODIFY_WRITE 0x0010
172 #define OPCODE_SEQ_PAUSE 0x0020
173 #define OPCODE_SEQ_END 0x0040
174 #define OPCODE_TMPL_END 0x0080
175 #define OPCODE_POLL_READ_LIST 0x0100
176
177
178 #define RESET_TMPLT_HDR_SIGNATURE 0xCAFE
179 struct qla4_83xx_reset_template_hdr {
180 __le16 version;
181 __le16 signature;
182 __le16 size;
183 __le16 entries;
184 __le16 hdr_size;
185 __le16 checksum;
186 __le16 init_seq_offset;
187 __le16 start_seq_offset;
188 } __packed;
189
190
191 struct qla4_83xx_reset_entry_hdr {
192 __le16 cmd;
193 __le16 size;
194 __le16 count;
195 __le16 delay;
196 } __packed;
197
198
199 struct qla4_83xx_poll {
200 __le32 test_mask;
201 __le32 test_value;
202 } __packed;
203
204
205 struct qla4_83xx_rmw {
206 __le32 test_mask;
207 __le32 xor_value;
208 __le32 or_value;
209 uint8_t shl;
210 uint8_t shr;
211 uint8_t index_a;
212 uint8_t rsvd;
213 } __packed;
214
215
216 struct qla4_83xx_entry {
217 __le32 arg1;
218 __le32 arg2;
219 } __packed;
220
221
222 struct qla4_83xx_quad_entry {
223 __le32 dr_addr;
224 __le32 dr_value;
225 __le32 ar_addr;
226 __le32 ar_value;
227 } __packed;
228
229 struct qla4_83xx_reset_template {
230 int seq_index;
231 int seq_error;
232 int array_index;
233 uint32_t array[QLA83XX_MAX_RESET_SEQ_ENTRIES];
234 uint8_t *buff;
235 uint8_t *stop_offset;
236 uint8_t *start_offset;
237 uint8_t *init_offset;
238 struct qla4_83xx_reset_template_hdr *hdr;
239 uint8_t seq_end;
240 uint8_t template_end;
241 };
242
243
244 struct qla83xx_minidump_entry_pollrd {
245 struct qla8xxx_minidump_entry_hdr h;
246 uint32_t select_addr;
247 uint32_t read_addr;
248 uint32_t select_value;
249 uint16_t select_value_stride;
250 uint16_t op_count;
251 uint32_t poll_wait;
252 uint32_t poll_mask;
253 uint32_t data_size;
254 uint32_t rsvd_1;
255 };
256
257 struct qla8044_minidump_entry_rddfe {
258 struct qla8xxx_minidump_entry_hdr h;
259 uint32_t addr_1;
260 uint32_t value;
261 uint8_t stride;
262 uint8_t stride2;
263 uint16_t count;
264 uint32_t poll;
265 uint32_t mask;
266 uint32_t modify_mask;
267 uint32_t data_size;
268 uint32_t rsvd;
269
270 } __packed;
271
272 struct qla8044_minidump_entry_rdmdio {
273 struct qla8xxx_minidump_entry_hdr h;
274
275 uint32_t addr_1;
276 uint32_t addr_2;
277 uint32_t value_1;
278 uint8_t stride_1;
279 uint8_t stride_2;
280 uint16_t count;
281 uint32_t poll;
282 uint32_t mask;
283 uint32_t value_2;
284 uint32_t data_size;
285
286 } __packed;
287
288 struct qla8044_minidump_entry_pollwr {
289 struct qla8xxx_minidump_entry_hdr h;
290 uint32_t addr_1;
291 uint32_t addr_2;
292 uint32_t value_1;
293 uint32_t value_2;
294 uint32_t poll;
295 uint32_t mask;
296 uint32_t data_size;
297 uint32_t rsvd;
298
299 } __packed;
300
301
302 struct qla83xx_minidump_entry_rdmux2 {
303 struct qla8xxx_minidump_entry_hdr h;
304 uint32_t select_addr_1;
305 uint32_t select_addr_2;
306 uint32_t select_value_1;
307 uint32_t select_value_2;
308 uint32_t op_count;
309 uint32_t select_value_mask;
310 uint32_t read_addr;
311 uint8_t select_value_stride;
312 uint8_t data_size;
313 uint8_t rsvd[2];
314 };
315
316
317 struct qla83xx_minidump_entry_pollrdmwr {
318 struct qla8xxx_minidump_entry_hdr h;
319 uint32_t addr_1;
320 uint32_t addr_2;
321 uint32_t value_1;
322 uint32_t value_2;
323 uint32_t poll_wait;
324 uint32_t poll_mask;
325 uint32_t modify_mask;
326 uint32_t data_size;
327 };
328
329
330 struct qla4_83xx_idc_information {
331 uint32_t request_desc;
332 uint32_t info1;
333 uint32_t info2;
334 uint32_t info3;
335 };
336
337 #define QLA83XX_PEX_DMA_ENGINE_INDEX 8
338 #define QLA83XX_PEX_DMA_BASE_ADDRESS 0x77320000
339 #define QLA83XX_PEX_DMA_NUM_OFFSET 0x10000
340 #define QLA83XX_PEX_DMA_CMD_ADDR_LOW 0x0
341 #define QLA83XX_PEX_DMA_CMD_ADDR_HIGH 0x04
342 #define QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL 0x08
343
344 #define QLA83XX_PEX_DMA_READ_SIZE (16 * 1024)
345 #define QLA83XX_PEX_DMA_MAX_WAIT (100 * 100)
346
347
348 struct qla4_83xx_minidump_entry_rdmem_pex_dma {
349 struct qla8xxx_minidump_entry_hdr h;
350 uint32_t desc_card_addr;
351 uint16_t dma_desc_cmd;
352 uint8_t rsvd[2];
353 uint32_t start_dma_cmd;
354 uint8_t rsvd2[12];
355 uint32_t read_addr;
356 uint32_t read_data_size;
357 };
358
359 struct qla4_83xx_pex_dma_descriptor {
360 struct {
361 uint32_t read_data_size;
362 uint8_t rsvd[2];
363 uint16_t dma_desc_cmd;
364 } cmd;
365 uint64_t src_addr;
366 uint64_t dma_bus_addr;
367
368 uint8_t rsvd[24];
369 } __packed;
370
371 #endif