This source file includes following definitions.
- dma_addr_writeql
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14 #ifndef _MYRS_H
15 #define _MYRS_H
16
17 #define MYRS_MAILBOX_TIMEOUT 1000000
18
19 #define MYRS_DCMD_TAG 1
20 #define MYRS_MCMD_TAG 2
21
22 #define MYRS_LINE_BUFFER_SIZE 128
23
24 #define MYRS_PRIMARY_MONITOR_INTERVAL (10 * HZ)
25 #define MYRS_SECONDARY_MONITOR_INTERVAL (60 * HZ)
26
27
28 #define MYRS_SG_LIMIT 128
29
30
31
32
33
34 #define MYRS_MAX_CMD_MBOX 512
35 #define MYRS_MAX_STAT_MBOX 512
36
37 #define MYRS_DCDB_SIZE 16
38 #define MYRS_SENSE_SIZE 14
39
40
41
42
43 enum myrs_cmd_opcode {
44 MYRS_CMD_OP_MEMCOPY = 0x01,
45 MYRS_CMD_OP_SCSI_10_PASSTHRU = 0x02,
46 MYRS_CMD_OP_SCSI_255_PASSTHRU = 0x03,
47 MYRS_CMD_OP_SCSI_10 = 0x04,
48 MYRS_CMD_OP_SCSI_256 = 0x05,
49 MYRS_CMD_OP_IOCTL = 0x20,
50 } __packed;
51
52
53
54
55 enum myrs_ioctl_opcode {
56 MYRS_IOCTL_GET_CTLR_INFO = 0x01,
57 MYRS_IOCTL_GET_LDEV_INFO_VALID = 0x03,
58 MYRS_IOCTL_GET_PDEV_INFO_VALID = 0x05,
59 MYRS_IOCTL_GET_HEALTH_STATUS = 0x11,
60 MYRS_IOCTL_GET_EVENT = 0x15,
61 MYRS_IOCTL_START_DISCOVERY = 0x81,
62 MYRS_IOCTL_SET_DEVICE_STATE = 0x82,
63 MYRS_IOCTL_INIT_PDEV_START = 0x84,
64 MYRS_IOCTL_INIT_PDEV_STOP = 0x85,
65 MYRS_IOCTL_INIT_LDEV_START = 0x86,
66 MYRS_IOCTL_INIT_LDEV_STOP = 0x87,
67 MYRS_IOCTL_RBLD_DEVICE_START = 0x88,
68 MYRS_IOCTL_RBLD_DEVICE_STOP = 0x89,
69 MYRS_IOCTL_MAKE_CONSISTENT_START = 0x8A,
70 MYRS_IOCTL_MAKE_CONSISTENT_STOP = 0x8B,
71 MYRS_IOCTL_CC_START = 0x8C,
72 MYRS_IOCTL_CC_STOP = 0x8D,
73 MYRS_IOCTL_SET_MEM_MBOX = 0x8E,
74 MYRS_IOCTL_RESET_DEVICE = 0x90,
75 MYRS_IOCTL_FLUSH_DEVICE_DATA = 0x91,
76 MYRS_IOCTL_PAUSE_DEVICE = 0x92,
77 MYRS_IOCTL_UNPAUS_EDEVICE = 0x93,
78 MYRS_IOCTL_LOCATE_DEVICE = 0x94,
79 MYRS_IOCTL_CREATE_CONFIGURATION = 0xC0,
80 MYRS_IOCTL_DELETE_LDEV = 0xC1,
81 MYRS_IOCTL_REPLACE_INTERNALDEVICE = 0xC2,
82 MYRS_IOCTL_RENAME_LDEV = 0xC3,
83 MYRS_IOCTL_ADD_CONFIGURATION = 0xC4,
84 MYRS_IOCTL_XLATE_PDEV_TO_LDEV = 0xC5,
85 MYRS_IOCTL_CLEAR_CONFIGURATION = 0xCA,
86 } __packed;
87
88
89
90
91 #define MYRS_STATUS_SUCCESS 0x00
92 #define MYRS_STATUS_FAILED 0x02
93 #define MYRS_STATUS_DEVICE_BUSY 0x08
94 #define MYRS_STATUS_DEVICE_NON_RESPONSIVE 0x0E
95 #define MYRS_STATUS_DEVICE_NON_RESPONSIVE2 0x0F
96 #define MYRS_STATUS_RESERVATION_CONFLICT 0x18
97
98
99
100
101 struct myrs_mem_type {
102 enum {
103 MYRS_MEMTYPE_RESERVED = 0x00,
104 MYRS_MEMTYPE_DRAM = 0x01,
105 MYRS_MEMTYPE_EDRAM = 0x02,
106 MYRS_MEMTYPE_EDO = 0x03,
107 MYRS_MEMTYPE_SDRAM = 0x04,
108 MYRS_MEMTYPE_LAST = 0x1F,
109 } __packed mem_type:5;
110 unsigned rsvd:1;
111 unsigned mem_parity:1;
112 unsigned mem_ecc:1;
113 };
114
115
116
117
118 enum myrs_cpu_type {
119 MYRS_CPUTYPE_i960CA = 0x01,
120 MYRS_CPUTYPE_i960RD = 0x02,
121 MYRS_CPUTYPE_i960RN = 0x03,
122 MYRS_CPUTYPE_i960RP = 0x04,
123 MYRS_CPUTYPE_NorthBay = 0x05,
124 MYRS_CPUTYPE_StrongArm = 0x06,
125 MYRS_CPUTYPE_i960RM = 0x07,
126 } __packed;
127
128
129
130
131 struct myrs_ctlr_info {
132 unsigned char rsvd1;
133 enum {
134 MYRS_SCSI_BUS = 0x00,
135 MYRS_Fibre_BUS = 0x01,
136 MYRS_PCI_BUS = 0x03
137 } __packed bus;
138 enum {
139 MYRS_CTLR_DAC960E = 0x01,
140 MYRS_CTLR_DAC960M = 0x08,
141 MYRS_CTLR_DAC960PD = 0x10,
142 MYRS_CTLR_DAC960PL = 0x11,
143 MYRS_CTLR_DAC960PU = 0x12,
144 MYRS_CTLR_DAC960PE = 0x13,
145 MYRS_CTLR_DAC960PG = 0x14,
146 MYRS_CTLR_DAC960PJ = 0x15,
147 MYRS_CTLR_DAC960PTL0 = 0x16,
148 MYRS_CTLR_DAC960PR = 0x17,
149 MYRS_CTLR_DAC960PRL = 0x18,
150 MYRS_CTLR_DAC960PT = 0x19,
151 MYRS_CTLR_DAC1164P = 0x1A,
152 MYRS_CTLR_DAC960PTL1 = 0x1B,
153 MYRS_CTLR_EXR2000P = 0x1C,
154 MYRS_CTLR_EXR3000P = 0x1D,
155 MYRS_CTLR_ACCELERAID352 = 0x1E,
156 MYRS_CTLR_ACCELERAID170 = 0x1F,
157 MYRS_CTLR_ACCELERAID160 = 0x20,
158 MYRS_CTLR_DAC960S = 0x60,
159 MYRS_CTLR_DAC960SU = 0x61,
160 MYRS_CTLR_DAC960SX = 0x62,
161 MYRS_CTLR_DAC960SF = 0x63,
162 MYRS_CTLR_DAC960SS = 0x64,
163 MYRS_CTLR_DAC960FL = 0x65,
164 MYRS_CTLR_DAC960LL = 0x66,
165 MYRS_CTLR_DAC960FF = 0x67,
166 MYRS_CTLR_DAC960HP = 0x68,
167 MYRS_CTLR_RAIDBRICK = 0x69,
168 MYRS_CTLR_METEOR_FL = 0x6A,
169 MYRS_CTLR_METEOR_FF = 0x6B
170 } __packed ctlr_type;
171 unsigned char rsvd2;
172 unsigned short bus_speed_mhz;
173 unsigned char bus_width;
174 unsigned char flash_code;
175 unsigned char ports_present;
176 unsigned char rsvd3[7];
177 unsigned char bus_name[16];
178 unsigned char ctlr_name[16];
179 unsigned char rsvd4[16];
180
181 unsigned char fw_major_version;
182 unsigned char fw_minor_version;
183 unsigned char fw_turn_number;
184 unsigned char fw_build_number;
185 unsigned char fw_release_day;
186 unsigned char fw_release_month;
187 unsigned char fw_release_year_hi;
188 unsigned char fw_release_year_lo;
189
190 unsigned char hw_rev;
191 unsigned char rsvd5[3];
192 unsigned char hw_release_day;
193 unsigned char hw_release_month;
194 unsigned char hw_release_year_hi;
195 unsigned char hw_release_year_lo;
196
197 unsigned char manuf_batch_num;
198 unsigned char rsvd6;
199 unsigned char manuf_plant_num;
200 unsigned char rsvd7;
201 unsigned char hw_manuf_day;
202 unsigned char hw_manuf_month;
203 unsigned char hw_manuf_year_hi;
204 unsigned char hw_manuf_year_lo;
205 unsigned char max_pd_per_xld;
206 unsigned char max_ild_per_xld;
207 unsigned short nvram_size_kb;
208 unsigned char max_xld;
209 unsigned char rsvd8[3];
210
211 unsigned char serial_number[16];
212 unsigned char rsvd9[16];
213
214 unsigned char rsvd10[3];
215 unsigned char oem_code;
216 unsigned char vendor[16];
217
218 unsigned char bbu_present:1;
219 unsigned char cluster_mode:1;
220 unsigned char rsvd11:6;
221 unsigned char rsvd12[3];
222
223 unsigned char pscan_active:1;
224 unsigned char rsvd13:7;
225 unsigned char pscan_chan;
226 unsigned char pscan_target;
227 unsigned char pscan_lun;
228
229 unsigned short max_transfer_size;
230 unsigned short max_sge;
231
232 unsigned short ldev_present;
233 unsigned short ldev_critical;
234 unsigned short ldev_offline;
235 unsigned short pdev_present;
236 unsigned short pdisk_present;
237 unsigned short pdisk_critical;
238 unsigned short pdisk_offline;
239 unsigned short max_tcq;
240
241 unsigned char physchan_present;
242 unsigned char virtchan_present;
243 unsigned char physchan_max;
244 unsigned char virtchan_max;
245 unsigned char max_targets[16];
246 unsigned char rsvd14[12];
247
248 unsigned short mem_size_mb;
249 unsigned short cache_size_mb;
250 unsigned int valid_cache_bytes;
251 unsigned int dirty_cache_bytes;
252 unsigned short mem_speed_mhz;
253 unsigned char mem_data_width;
254 struct myrs_mem_type mem_type;
255 unsigned char cache_mem_type_name[16];
256
257 unsigned short exec_mem_size_mb;
258 unsigned short exec_l2_cache_size_mb;
259 unsigned char rsvd15[8];
260 unsigned short exec_mem_speed_mhz;
261 unsigned char exec_mem_data_width;
262 struct myrs_mem_type exec_mem_type;
263 unsigned char exec_mem_type_name[16];
264
265 struct {
266 unsigned short cpu_speed_mhz;
267 enum myrs_cpu_type cpu_type;
268 unsigned char cpu_count;
269 unsigned char rsvd16[12];
270 unsigned char cpu_name[16];
271 } __packed cpu[2];
272
273 unsigned short cur_prof_page_num;
274 unsigned short num_prof_waiters;
275 unsigned short cur_trace_page_num;
276 unsigned short num_trace_waiters;
277 unsigned char rsvd18[8];
278
279 unsigned short pdev_bus_resets;
280 unsigned short pdev_parity_errors;
281 unsigned short pdev_soft_errors;
282 unsigned short pdev_cmds_failed;
283 unsigned short pdev_misc_errors;
284 unsigned short pdev_cmd_timeouts;
285 unsigned short pdev_sel_timeouts;
286 unsigned short pdev_retries_done;
287 unsigned short pdev_aborts_done;
288 unsigned short pdev_host_aborts_done;
289 unsigned short pdev_predicted_failures;
290 unsigned short pdev_host_cmds_failed;
291 unsigned short pdev_hard_errors;
292 unsigned char rsvd19[6];
293
294 unsigned short ldev_soft_errors;
295 unsigned short ldev_cmds_failed;
296 unsigned short ldev_host_aborts_done;
297 unsigned char rsvd20[2];
298
299 unsigned short ctlr_mem_errors;
300 unsigned short ctlr_host_aborts_done;
301 unsigned char rsvd21[4];
302
303 unsigned short bg_init_active;
304 unsigned short ldev_init_active;
305 unsigned short pdev_init_active;
306 unsigned short cc_active;
307 unsigned short rbld_active;
308 unsigned short exp_active;
309 unsigned short patrol_active;
310 unsigned char rsvd22[2];
311
312 unsigned char flash_type;
313 unsigned char rsvd23;
314 unsigned short flash_size_MB;
315 unsigned int flash_limit;
316 unsigned int flash_count;
317 unsigned char rsvd24[4];
318 unsigned char flash_type_name[16];
319
320 unsigned char rbld_rate;
321 unsigned char bg_init_rate;
322 unsigned char fg_init_rate;
323 unsigned char cc_rate;
324 unsigned char rsvd25[4];
325 unsigned int max_dp;
326 unsigned int free_dp;
327 unsigned int max_iop;
328 unsigned int free_iop;
329 unsigned short max_combined_len;
330 unsigned short num_cfg_groups;
331 unsigned installation_abort_status:1;
332 unsigned maint_mode_status:1;
333 unsigned rsvd26:6;
334 unsigned char rsvd27[6];
335 unsigned char rsvd28[512];
336 };
337
338
339
340
341 enum myrs_devstate {
342 MYRS_DEVICE_UNCONFIGURED = 0x00,
343 MYRS_DEVICE_ONLINE = 0x01,
344 MYRS_DEVICE_REBUILD = 0x03,
345 MYRS_DEVICE_MISSING = 0x04,
346 MYRS_DEVICE_SUSPECTED_CRITICAL = 0x05,
347 MYRS_DEVICE_OFFLINE = 0x08,
348 MYRS_DEVICE_CRITICAL = 0x09,
349 MYRS_DEVICE_SUSPECTED_DEAD = 0x0C,
350 MYRS_DEVICE_COMMANDED_OFFLINE = 0x10,
351 MYRS_DEVICE_STANDBY = 0x21,
352 MYRS_DEVICE_INVALID_STATE = 0xFF,
353 } __packed;
354
355
356
357
358 enum myrs_raid_level {
359 MYRS_RAID_LEVEL0 = 0x0,
360 MYRS_RAID_LEVEL1 = 0x1,
361 MYRS_RAID_LEVEL3 = 0x3,
362 MYRS_RAID_LEVEL5 = 0x5,
363 MYRS_RAID_LEVEL6 = 0x6,
364 MYRS_RAID_JBOD = 0x7,
365 MYRS_RAID_NEWSPAN = 0x8,
366 MYRS_RAID_LEVEL3F = 0x9,
367 MYRS_RAID_LEVEL3L = 0xb,
368 MYRS_RAID_SPAN = 0xc,
369 MYRS_RAID_LEVEL5L = 0xd,
370 MYRS_RAID_LEVELE = 0xe,
371 MYRS_RAID_PHYSICAL = 0xf,
372 } __packed;
373
374 enum myrs_stripe_size {
375 MYRS_STRIPE_SIZE_0 = 0x0,
376 MYRS_STRIPE_SIZE_512B = 0x1,
377 MYRS_STRIPE_SIZE_1K = 0x2,
378 MYRS_STRIPE_SIZE_2K = 0x3,
379 MYRS_STRIPE_SIZE_4K = 0x4,
380 MYRS_STRIPE_SIZE_8K = 0x5,
381 MYRS_STRIPE_SIZE_16K = 0x6,
382 MYRS_STRIPE_SIZE_32K = 0x7,
383 MYRS_STRIPE_SIZE_64K = 0x8,
384 MYRS_STRIPE_SIZE_128K = 0x9,
385 MYRS_STRIPE_SIZE_256K = 0xa,
386 MYRS_STRIPE_SIZE_512K = 0xb,
387 MYRS_STRIPE_SIZE_1M = 0xc,
388 } __packed;
389
390 enum myrs_cacheline_size {
391 MYRS_CACHELINE_ZERO = 0x0,
392 MYRS_CACHELINE_512B = 0x1,
393 MYRS_CACHELINE_1K = 0x2,
394 MYRS_CACHELINE_2K = 0x3,
395 MYRS_CACHELINE_4K = 0x4,
396 MYRS_CACHELINE_8K = 0x5,
397 MYRS_CACHELINE_16K = 0x6,
398 MYRS_CACHELINE_32K = 0x7,
399 MYRS_CACHELINE_64K = 0x8,
400 } __packed;
401
402
403
404
405 struct myrs_ldev_info {
406 unsigned char ctlr;
407 unsigned char channel;
408 unsigned char target;
409 unsigned char lun;
410 enum myrs_devstate dev_state;
411 unsigned char raid_level;
412 enum myrs_stripe_size stripe_size;
413 enum myrs_cacheline_size cacheline_size;
414 struct {
415 enum {
416 MYRS_READCACHE_DISABLED = 0x0,
417 MYRS_READCACHE_ENABLED = 0x1,
418 MYRS_READAHEAD_ENABLED = 0x2,
419 MYRS_INTELLIGENT_READAHEAD_ENABLED = 0x3,
420 MYRS_READCACHE_LAST = 0x7,
421 } __packed rce:3;
422 enum {
423 MYRS_WRITECACHE_DISABLED = 0x0,
424 MYRS_LOGICALDEVICE_RO = 0x1,
425 MYRS_WRITECACHE_ENABLED = 0x2,
426 MYRS_INTELLIGENT_WRITECACHE_ENABLED = 0x3,
427 MYRS_WRITECACHE_LAST = 0x7,
428 } __packed wce:3;
429 unsigned rsvd1:1;
430 unsigned ldev_init_done:1;
431 } ldev_control;
432
433 unsigned char cc_active:1;
434 unsigned char rbld_active:1;
435 unsigned char bg_init_active:1;
436 unsigned char fg_init_active:1;
437 unsigned char migration_active:1;
438 unsigned char patrol_active:1;
439 unsigned char rsvd2:2;
440 unsigned char raid5_writeupdate;
441 unsigned char raid5_algo;
442 unsigned short ldev_num;
443
444 unsigned char bios_disabled:1;
445 unsigned char cdrom_boot:1;
446 unsigned char drv_coercion:1;
447 unsigned char write_same_disabled:1;
448 unsigned char hba_mode:1;
449 enum {
450 MYRS_GEOMETRY_128_32 = 0x0,
451 MYRS_GEOMETRY_255_63 = 0x1,
452 MYRS_GEOMETRY_RSVD1 = 0x2,
453 MYRS_GEOMETRY_RSVD2 = 0x3
454 } __packed drv_geom:2;
455 unsigned char super_ra_enabled:1;
456 unsigned char rsvd3;
457
458 unsigned short soft_errs;
459 unsigned short cmds_failed;
460 unsigned short cmds_aborted;
461 unsigned short deferred_write_errs;
462 unsigned int rsvd4;
463 unsigned int rsvd5;
464
465 unsigned short rsvd6;
466 unsigned short devsize_bytes;
467 unsigned int orig_devsize;
468 unsigned int cfg_devsize;
469 unsigned int rsvd7;
470 unsigned char ldev_name[32];
471 unsigned char inquiry[36];
472 unsigned char rsvd8[12];
473 u64 last_read_lba;
474 u64 last_write_lba;
475 u64 cc_lba;
476 u64 rbld_lba;
477 u64 bg_init_lba;
478 u64 fg_init_lba;
479 u64 migration_lba;
480 u64 patrol_lba;
481 unsigned char rsvd9[64];
482 };
483
484
485
486
487 struct myrs_pdev_info {
488 unsigned char rsvd1;
489 unsigned char channel;
490 unsigned char target;
491 unsigned char lun;
492
493 unsigned char pdev_fault_tolerant:1;
494 unsigned char pdev_connected:1;
495 unsigned char pdev_local_to_ctlr:1;
496 unsigned char rsvd2:5;
497
498 unsigned char remote_host_dead:1;
499 unsigned char remove_ctlr_dead:1;
500 unsigned char rsvd3:6;
501 enum myrs_devstate dev_state;
502 unsigned char nego_data_width;
503 unsigned short nego_sync_rate;
504
505 unsigned char num_ports;
506 unsigned char drv_access_bitmap;
507 unsigned int rsvd4;
508 unsigned char ip_address[16];
509 unsigned short max_tags;
510
511 unsigned char cc_in_progress:1;
512 unsigned char rbld_in_progress:1;
513 unsigned char makecc_in_progress:1;
514 unsigned char pdevinit_in_progress:1;
515 unsigned char migration_in_progress:1;
516 unsigned char patrol_in_progress:1;
517 unsigned char rsvd5:2;
518 unsigned char long_op_status;
519 unsigned char parity_errs;
520 unsigned char soft_errs;
521 unsigned char hard_errs;
522 unsigned char misc_errs;
523 unsigned char cmd_timeouts;
524 unsigned char retries;
525 unsigned char aborts;
526 unsigned char pred_failures;
527 unsigned int rsvd6;
528 unsigned short rsvd7;
529 unsigned short devsize_bytes;
530 unsigned int orig_devsize;
531 unsigned int cfg_devsize;
532 unsigned int rsvd8;
533 unsigned char pdev_name[16];
534 unsigned char rsvd9[16];
535 unsigned char rsvd10[32];
536 unsigned char inquiry[36];
537 unsigned char rsvd11[20];
538 unsigned char rsvd12[8];
539 u64 last_read_lba;
540 u64 last_write_lba;
541 u64 cc_lba;
542 u64 rbld_lba;
543 u64 makecc_lba;
544 u64 devinit_lba;
545 u64 migration_lba;
546 u64 patrol_lba;
547 unsigned char rsvd13[256];
548 };
549
550
551
552
553 struct myrs_fwstat {
554 unsigned int uptime_usecs;
555 unsigned int uptime_msecs;
556 unsigned int seconds;
557 unsigned char rsvd1[4];
558 unsigned int epoch;
559 unsigned char rsvd2[4];
560 unsigned int dbg_msgbuf_idx;
561 unsigned int coded_msgbuf_idx;
562 unsigned int cur_timetrace_page;
563 unsigned int cur_prof_page;
564 unsigned int next_evseq;
565 unsigned char rsvd3[4];
566 unsigned char rsvd4[16];
567 unsigned char rsvd5[64];
568 };
569
570
571
572
573 struct myrs_event {
574 unsigned int ev_seq;
575 unsigned int ev_time;
576 unsigned int ev_code;
577 unsigned char rsvd1;
578 unsigned char channel;
579 unsigned char target;
580 unsigned char lun;
581 unsigned int rsvd2;
582 unsigned int ev_parm;
583 unsigned char sense_data[40];
584 };
585
586
587
588
589 struct myrs_cmd_ctrl {
590 unsigned char fua:1;
591 unsigned char disable_pgout:1;
592 unsigned char rsvd1:1;
593 unsigned char add_sge_mem:1;
594 unsigned char dma_ctrl_to_host:1;
595 unsigned char rsvd2:1;
596 unsigned char no_autosense:1;
597 unsigned char disc_prohibited:1;
598 };
599
600
601
602
603 struct myrs_cmd_tmo {
604 unsigned char tmo_val:6;
605 enum {
606 MYRS_TMO_SCALE_SECONDS = 0,
607 MYRS_TMO_SCALE_MINUTES = 1,
608 MYRS_TMO_SCALE_HOURS = 2,
609 MYRS_TMO_SCALE_RESERVED = 3
610 } __packed tmo_scale:2;
611 };
612
613
614
615
616 struct myrs_pdev {
617 unsigned char lun;
618 unsigned char target;
619 unsigned char channel:3;
620 unsigned char ctlr:5;
621 } __packed;
622
623
624
625
626 struct myrs_ldev {
627 unsigned short ldev_num;
628 unsigned char rsvd:3;
629 unsigned char ctlr:5;
630 } __packed;
631
632
633
634
635 enum myrs_opdev {
636 MYRS_PHYSICAL_DEVICE = 0x00,
637 MYRS_RAID_DEVICE = 0x01,
638 MYRS_PHYSICAL_CHANNEL = 0x02,
639 MYRS_RAID_CHANNEL = 0x03,
640 MYRS_PHYSICAL_CONTROLLER = 0x04,
641 MYRS_RAID_CONTROLLER = 0x05,
642 MYRS_CONFIGURATION_GROUP = 0x10,
643 MYRS_ENCLOSURE = 0x11,
644 } __packed;
645
646
647
648
649 struct myrs_devmap {
650 unsigned short ldev_num;
651 unsigned short rsvd;
652 unsigned char prev_boot_ctlr;
653 unsigned char prev_boot_channel;
654 unsigned char prev_boot_target;
655 unsigned char prev_boot_lun;
656 };
657
658
659
660
661 struct myrs_sge {
662 u64 sge_addr;
663 u64 sge_count;
664 };
665
666
667
668
669 union myrs_sgl {
670 struct myrs_sge sge[2];
671 struct {
672 unsigned short sge0_len;
673 unsigned short sge1_len;
674 unsigned short sge2_len;
675 unsigned short rsvd;
676 u64 sge0_addr;
677 u64 sge1_addr;
678 u64 sge2_addr;
679 } ext;
680 };
681
682
683
684
685 union myrs_cmd_mbox {
686 unsigned int words[16];
687 struct {
688 unsigned short id;
689 enum myrs_cmd_opcode opcode;
690 struct myrs_cmd_ctrl control;
691 u32 dma_size:24;
692 unsigned char dma_num;
693 u64 sense_addr;
694 unsigned int rsvd1:24;
695 struct myrs_cmd_tmo tmo;
696 unsigned char sense_len;
697 enum myrs_ioctl_opcode ioctl_opcode;
698 unsigned char rsvd2[10];
699 union myrs_sgl dma_addr;
700 } common;
701 struct {
702 unsigned short id;
703 enum myrs_cmd_opcode opcode;
704 struct myrs_cmd_ctrl control;
705 u32 dma_size;
706 u64 sense_addr;
707 struct myrs_pdev pdev;
708 struct myrs_cmd_tmo tmo;
709 unsigned char sense_len;
710 unsigned char cdb_len;
711 unsigned char cdb[10];
712 union myrs_sgl dma_addr;
713 } SCSI_10;
714 struct {
715 unsigned short id;
716 enum myrs_cmd_opcode opcode;
717 struct myrs_cmd_ctrl control;
718 u32 dma_size;
719 u64 sense_addr;
720 struct myrs_pdev pdev;
721 struct myrs_cmd_tmo tmo;
722 unsigned char sense_len;
723 unsigned char cdb_len;
724 unsigned short rsvd;
725 u64 cdb_addr;
726 union myrs_sgl dma_addr;
727 } SCSI_255;
728 struct {
729 unsigned short id;
730 enum myrs_cmd_opcode opcode;
731 struct myrs_cmd_ctrl control;
732 u32 dma_size:24;
733 unsigned char dma_num;
734 u64 sense_addr;
735 unsigned short rsvd1;
736 unsigned char ctlr_num;
737 struct myrs_cmd_tmo tmo;
738 unsigned char sense_len;
739 enum myrs_ioctl_opcode ioctl_opcode;
740 unsigned char rsvd2[10];
741 union myrs_sgl dma_addr;
742 } ctlr_info;
743 struct {
744 unsigned short id;
745 enum myrs_cmd_opcode opcode;
746 struct myrs_cmd_ctrl control;
747 u32 dma_size:24;
748 unsigned char dma_num;
749 u64 sense_addr;
750 struct myrs_ldev ldev;
751 struct myrs_cmd_tmo tmo;
752 unsigned char sense_len;
753 enum myrs_ioctl_opcode ioctl_opcode;
754 unsigned char rsvd[10];
755 union myrs_sgl dma_addr;
756 } ldev_info;
757 struct {
758 unsigned short id;
759 enum myrs_cmd_opcode opcode;
760 struct myrs_cmd_ctrl control;
761 u32 dma_size:24;
762 unsigned char dma_num;
763 u64 sense_addr;
764 struct myrs_pdev pdev;
765 struct myrs_cmd_tmo tmo;
766 unsigned char sense_len;
767 enum myrs_ioctl_opcode ioctl_opcode;
768 unsigned char rsvd[10];
769 union myrs_sgl dma_addr;
770 } pdev_info;
771 struct {
772 unsigned short id;
773 enum myrs_cmd_opcode opcode;
774 struct myrs_cmd_ctrl control;
775 u32 dma_size:24;
776 unsigned char dma_num;
777 u64 sense_addr;
778 unsigned short evnum_upper;
779 unsigned char ctlr_num;
780 struct myrs_cmd_tmo tmo;
781 unsigned char sense_len;
782 enum myrs_ioctl_opcode ioctl_opcode;
783 unsigned short evnum_lower;
784 unsigned char rsvd[8];
785 union myrs_sgl dma_addr;
786 } get_event;
787 struct {
788 unsigned short id;
789 enum myrs_cmd_opcode opcode;
790 struct myrs_cmd_ctrl control;
791 u32 dma_size:24;
792 unsigned char dma_num;
793 u64 sense_addr;
794 union {
795 struct myrs_ldev ldev;
796 struct myrs_pdev pdev;
797 };
798 struct myrs_cmd_tmo tmo;
799 unsigned char sense_len;
800 enum myrs_ioctl_opcode ioctl_opcode;
801 enum myrs_devstate state;
802 unsigned char rsvd[9];
803 union myrs_sgl dma_addr;
804 } set_devstate;
805 struct {
806 unsigned short id;
807 enum myrs_cmd_opcode opcode;
808 struct myrs_cmd_ctrl control;
809 u32 dma_size:24;
810 unsigned char dma_num;
811 u64 sense_addr;
812 struct myrs_ldev ldev;
813 struct myrs_cmd_tmo tmo;
814 unsigned char sense_len;
815 enum myrs_ioctl_opcode ioctl_opcode;
816 unsigned char restore_consistency:1;
817 unsigned char initialized_area_only:1;
818 unsigned char rsvd1:6;
819 unsigned char rsvd2[9];
820 union myrs_sgl dma_addr;
821 } cc;
822 struct {
823 unsigned short id;
824 enum myrs_cmd_opcode opcode;
825 struct myrs_cmd_ctrl control;
826 unsigned char first_cmd_mbox_size_kb;
827 unsigned char first_stat_mbox_size_kb;
828 unsigned char second_cmd_mbox_size_kb;
829 unsigned char second_stat_mbox_size_kb;
830 u64 sense_addr;
831 unsigned int rsvd1:24;
832 struct myrs_cmd_tmo tmo;
833 unsigned char sense_len;
834 enum myrs_ioctl_opcode ioctl_opcode;
835 unsigned char fwstat_buf_size_kb;
836 unsigned char rsvd2;
837 u64 fwstat_buf_addr;
838 u64 first_cmd_mbox_addr;
839 u64 first_stat_mbox_addr;
840 u64 second_cmd_mbox_addr;
841 u64 second_stat_mbox_addr;
842 } set_mbox;
843 struct {
844 unsigned short id;
845 enum myrs_cmd_opcode opcode;
846 struct myrs_cmd_ctrl control;
847 u32 dma_size:24;
848 unsigned char dma_num;
849 u64 sense_addr;
850 struct myrs_pdev pdev;
851 struct myrs_cmd_tmo tmo;
852 unsigned char sense_len;
853 enum myrs_ioctl_opcode ioctl_opcode;
854 enum myrs_opdev opdev;
855 unsigned char rsvd[9];
856 union myrs_sgl dma_addr;
857 } dev_op;
858 };
859
860
861
862
863 struct myrs_stat_mbox {
864 unsigned short id;
865 unsigned char status;
866 unsigned char sense_len;
867 int residual;
868 };
869
870 struct myrs_cmdblk {
871 union myrs_cmd_mbox mbox;
872 unsigned char status;
873 unsigned char sense_len;
874 int residual;
875 struct completion *complete;
876 struct myrs_sge *sgl;
877 dma_addr_t sgl_addr;
878 unsigned char *dcdb;
879 dma_addr_t dcdb_dma;
880 unsigned char *sense;
881 dma_addr_t sense_addr;
882 };
883
884
885
886
887 struct myrs_hba {
888 void __iomem *io_base;
889 void __iomem *mmio_base;
890 phys_addr_t io_addr;
891 phys_addr_t pci_addr;
892 unsigned int irq;
893
894 unsigned char model_name[28];
895 unsigned char fw_version[12];
896
897 struct Scsi_Host *host;
898 struct pci_dev *pdev;
899
900 unsigned int epoch;
901 unsigned int next_evseq;
902
903 bool needs_update;
904 bool disable_enc_msg;
905
906 struct workqueue_struct *work_q;
907 char work_q_name[20];
908 struct delayed_work monitor_work;
909 unsigned long primary_monitor_time;
910 unsigned long secondary_monitor_time;
911
912 spinlock_t queue_lock;
913
914 struct dma_pool *sg_pool;
915 struct dma_pool *sense_pool;
916 struct dma_pool *dcdb_pool;
917
918 void (*write_cmd_mbox)(union myrs_cmd_mbox *next_mbox,
919 union myrs_cmd_mbox *cmd_mbox);
920 void (*get_cmd_mbox)(void __iomem *base);
921 void (*disable_intr)(void __iomem *base);
922 void (*reset)(void __iomem *base);
923
924 dma_addr_t cmd_mbox_addr;
925 size_t cmd_mbox_size;
926 union myrs_cmd_mbox *first_cmd_mbox;
927 union myrs_cmd_mbox *last_cmd_mbox;
928 union myrs_cmd_mbox *next_cmd_mbox;
929 union myrs_cmd_mbox *prev_cmd_mbox1;
930 union myrs_cmd_mbox *prev_cmd_mbox2;
931
932 dma_addr_t stat_mbox_addr;
933 size_t stat_mbox_size;
934 struct myrs_stat_mbox *first_stat_mbox;
935 struct myrs_stat_mbox *last_stat_mbox;
936 struct myrs_stat_mbox *next_stat_mbox;
937
938 struct myrs_cmdblk dcmd_blk;
939 struct myrs_cmdblk mcmd_blk;
940 struct mutex dcmd_mutex;
941
942 struct myrs_fwstat *fwstat_buf;
943 dma_addr_t fwstat_addr;
944
945 struct myrs_ctlr_info *ctlr_info;
946 struct mutex cinfo_mutex;
947
948 struct myrs_event *event_buf;
949 };
950
951 typedef unsigned char (*enable_mbox_t)(void __iomem *base, dma_addr_t addr);
952 typedef int (*myrs_hwinit_t)(struct pci_dev *pdev,
953 struct myrs_hba *c, void __iomem *base);
954
955 struct myrs_privdata {
956 myrs_hwinit_t hw_init;
957 irq_handler_t irq_handler;
958 unsigned int mmio_size;
959 };
960
961
962
963
964
965 #define DAC960_GEM_mmio_size 0x600
966
967 enum DAC960_GEM_reg_offset {
968 DAC960_GEM_IDB_READ_OFFSET = 0x214,
969 DAC960_GEM_IDB_CLEAR_OFFSET = 0x218,
970 DAC960_GEM_ODB_READ_OFFSET = 0x224,
971 DAC960_GEM_ODB_CLEAR_OFFSET = 0x228,
972 DAC960_GEM_IRQSTS_OFFSET = 0x208,
973 DAC960_GEM_IRQMASK_READ_OFFSET = 0x22C,
974 DAC960_GEM_IRQMASK_CLEAR_OFFSET = 0x230,
975 DAC960_GEM_CMDMBX_OFFSET = 0x510,
976 DAC960_GEM_CMDSTS_OFFSET = 0x518,
977 DAC960_GEM_ERRSTS_READ_OFFSET = 0x224,
978 DAC960_GEM_ERRSTS_CLEAR_OFFSET = 0x228,
979 };
980
981
982
983
984 #define DAC960_GEM_IDB_HWMBOX_NEW_CMD 0x01
985 #define DAC960_GEM_IDB_HWMBOX_ACK_STS 0x02
986 #define DAC960_GEM_IDB_GEN_IRQ 0x04
987 #define DAC960_GEM_IDB_CTRL_RESET 0x08
988 #define DAC960_GEM_IDB_MMBOX_NEW_CMD 0x10
989
990 #define DAC960_GEM_IDB_HWMBOX_FULL 0x01
991 #define DAC960_GEM_IDB_INIT_IN_PROGRESS 0x02
992
993
994
995
996 #define DAC960_GEM_ODB_HWMBOX_ACK_IRQ 0x01
997 #define DAC960_GEM_ODB_MMBOX_ACK_IRQ 0x02
998 #define DAC960_GEM_ODB_HWMBOX_STS_AVAIL 0x01
999 #define DAC960_GEM_ODB_MMBOX_STS_AVAIL 0x02
1000
1001
1002
1003
1004 #define DAC960_GEM_IRQMASK_HWMBOX_IRQ 0x01
1005 #define DAC960_GEM_IRQMASK_MMBOX_IRQ 0x02
1006
1007
1008
1009
1010 #define DAC960_GEM_ERRSTS_PENDING 0x20
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025 static inline
1026 void dma_addr_writeql(dma_addr_t addr, void __iomem *write_address)
1027 {
1028 union {
1029 u64 wq;
1030 uint wl[2];
1031 } u;
1032
1033 u.wq = addr;
1034
1035 writel(u.wl[0], write_address);
1036 writel(u.wl[1], write_address + 4);
1037 }
1038
1039
1040
1041
1042
1043 #define DAC960_BA_mmio_size 0x80
1044
1045 enum DAC960_BA_reg_offset {
1046 DAC960_BA_IRQSTS_OFFSET = 0x30,
1047 DAC960_BA_IRQMASK_OFFSET = 0x34,
1048 DAC960_BA_CMDMBX_OFFSET = 0x50,
1049 DAC960_BA_CMDSTS_OFFSET = 0x58,
1050 DAC960_BA_IDB_OFFSET = 0x60,
1051 DAC960_BA_ODB_OFFSET = 0x61,
1052 DAC960_BA_ERRSTS_OFFSET = 0x63,
1053 };
1054
1055
1056
1057
1058 #define DAC960_BA_IDB_HWMBOX_NEW_CMD 0x01
1059 #define DAC960_BA_IDB_HWMBOX_ACK_STS 0x02
1060 #define DAC960_BA_IDB_GEN_IRQ 0x04
1061 #define DAC960_BA_IDB_CTRL_RESET 0x08
1062 #define DAC960_BA_IDB_MMBOX_NEW_CMD 0x10
1063
1064 #define DAC960_BA_IDB_HWMBOX_EMPTY 0x01
1065 #define DAC960_BA_IDB_INIT_DONE 0x02
1066
1067
1068
1069
1070 #define DAC960_BA_ODB_HWMBOX_ACK_IRQ 0x01
1071 #define DAC960_BA_ODB_MMBOX_ACK_IRQ 0x02
1072
1073 #define DAC960_BA_ODB_HWMBOX_STS_AVAIL 0x01
1074 #define DAC960_BA_ODB_MMBOX_STS_AVAIL 0x02
1075
1076
1077
1078
1079 #define DAC960_BA_IRQMASK_DISABLE_IRQ 0x04
1080 #define DAC960_BA_IRQMASK_DISABLEW_I2O 0x08
1081
1082
1083
1084
1085 #define DAC960_BA_ERRSTS_PENDING 0x04
1086
1087
1088
1089
1090
1091 #define DAC960_LP_mmio_size 0x80
1092
1093 enum DAC960_LP_reg_offset {
1094 DAC960_LP_CMDMBX_OFFSET = 0x10,
1095 DAC960_LP_CMDSTS_OFFSET = 0x18,
1096 DAC960_LP_IDB_OFFSET = 0x20,
1097 DAC960_LP_ODB_OFFSET = 0x2C,
1098 DAC960_LP_ERRSTS_OFFSET = 0x2E,
1099 DAC960_LP_IRQSTS_OFFSET = 0x30,
1100 DAC960_LP_IRQMASK_OFFSET = 0x34,
1101 };
1102
1103
1104
1105
1106 #define DAC960_LP_IDB_HWMBOX_NEW_CMD 0x01
1107 #define DAC960_LP_IDB_HWMBOX_ACK_STS 0x02
1108 #define DAC960_LP_IDB_GEN_IRQ 0x04
1109 #define DAC960_LP_IDB_CTRL_RESET 0x08
1110 #define DAC960_LP_IDB_MMBOX_NEW_CMD 0x10
1111
1112 #define DAC960_LP_IDB_HWMBOX_FULL 0x01
1113 #define DAC960_LP_IDB_INIT_IN_PROGRESS 0x02
1114
1115
1116
1117
1118 #define DAC960_LP_ODB_HWMBOX_ACK_IRQ 0x01
1119 #define DAC960_LP_ODB_MMBOX_ACK_IRQ 0x02
1120
1121 #define DAC960_LP_ODB_HWMBOX_STS_AVAIL 0x01
1122 #define DAC960_LP_ODB_MMBOX_STS_AVAIL 0x02
1123
1124
1125
1126
1127 #define DAC960_LP_IRQMASK_DISABLE_IRQ 0x04
1128
1129
1130
1131
1132 #define DAC960_LP_ERRSTS_PENDING 0x04
1133
1134 #endif