root/drivers/scsi/ufs/ufs-qcom.h

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INCLUDED FROM

DEFINITIONS

This source file includes following definitions.
  1. ufs_qcom_get_controller_revision
  2. ufs_qcom_assert_reset
  3. ufs_qcom_deassert_reset
  4. ufs_qcom_get_debug_reg_offset
  5. ufs_qcom_cap_qunipro
   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
   3  */
   4 
   5 #ifndef UFS_QCOM_H_
   6 #define UFS_QCOM_H_
   7 
   8 #include <linux/reset-controller.h>
   9 
  10 #define MAX_UFS_QCOM_HOSTS      1
  11 #define MAX_U32                 (~(u32)0)
  12 #define MPHY_TX_FSM_STATE       0x41
  13 #define TX_FSM_HIBERN8          0x1
  14 #define HBRN8_POLL_TOUT_MS      100
  15 #define DEFAULT_CLK_RATE_HZ     1000000
  16 #define BUS_VECTOR_NAME_LEN     32
  17 
  18 #define UFS_HW_VER_MAJOR_SHFT   (28)
  19 #define UFS_HW_VER_MAJOR_MASK   (0x000F << UFS_HW_VER_MAJOR_SHFT)
  20 #define UFS_HW_VER_MINOR_SHFT   (16)
  21 #define UFS_HW_VER_MINOR_MASK   (0x0FFF << UFS_HW_VER_MINOR_SHFT)
  22 #define UFS_HW_VER_STEP_SHFT    (0)
  23 #define UFS_HW_VER_STEP_MASK    (0xFFFF << UFS_HW_VER_STEP_SHFT)
  24 
  25 /* vendor specific pre-defined parameters */
  26 #define SLOW 1
  27 #define FAST 2
  28 
  29 #define UFS_QCOM_LIMIT_NUM_LANES_RX     2
  30 #define UFS_QCOM_LIMIT_NUM_LANES_TX     2
  31 #define UFS_QCOM_LIMIT_HSGEAR_RX        UFS_HS_G3
  32 #define UFS_QCOM_LIMIT_HSGEAR_TX        UFS_HS_G3
  33 #define UFS_QCOM_LIMIT_PWMGEAR_RX       UFS_PWM_G4
  34 #define UFS_QCOM_LIMIT_PWMGEAR_TX       UFS_PWM_G4
  35 #define UFS_QCOM_LIMIT_RX_PWR_PWM       SLOW_MODE
  36 #define UFS_QCOM_LIMIT_TX_PWR_PWM       SLOW_MODE
  37 #define UFS_QCOM_LIMIT_RX_PWR_HS        FAST_MODE
  38 #define UFS_QCOM_LIMIT_TX_PWR_HS        FAST_MODE
  39 #define UFS_QCOM_LIMIT_HS_RATE          PA_HS_MODE_B
  40 #define UFS_QCOM_LIMIT_DESIRED_MODE     FAST
  41 
  42 /* QCOM UFS host controller vendor specific registers */
  43 enum {
  44         REG_UFS_SYS1CLK_1US                 = 0xC0,
  45         REG_UFS_TX_SYMBOL_CLK_NS_US         = 0xC4,
  46         REG_UFS_LOCAL_PORT_ID_REG           = 0xC8,
  47         REG_UFS_PA_ERR_CODE                 = 0xCC,
  48         REG_UFS_RETRY_TIMER_REG             = 0xD0,
  49         REG_UFS_PA_LINK_STARTUP_TIMER       = 0xD8,
  50         REG_UFS_CFG1                        = 0xDC,
  51         REG_UFS_CFG2                        = 0xE0,
  52         REG_UFS_HW_VERSION                  = 0xE4,
  53 
  54         UFS_TEST_BUS                            = 0xE8,
  55         UFS_TEST_BUS_CTRL_0                     = 0xEC,
  56         UFS_TEST_BUS_CTRL_1                     = 0xF0,
  57         UFS_TEST_BUS_CTRL_2                     = 0xF4,
  58         UFS_UNIPRO_CFG                          = 0xF8,
  59 
  60         /*
  61          * QCOM UFS host controller vendor specific registers
  62          * added in HW Version 3.0.0
  63          */
  64         UFS_AH8_CFG                             = 0xFC,
  65 };
  66 
  67 /* QCOM UFS host controller vendor specific debug registers */
  68 enum {
  69         UFS_DBG_RD_REG_UAWM                     = 0x100,
  70         UFS_DBG_RD_REG_UARM                     = 0x200,
  71         UFS_DBG_RD_REG_TXUC                     = 0x300,
  72         UFS_DBG_RD_REG_RXUC                     = 0x400,
  73         UFS_DBG_RD_REG_DFC                      = 0x500,
  74         UFS_DBG_RD_REG_TRLUT                    = 0x600,
  75         UFS_DBG_RD_REG_TMRLUT                   = 0x700,
  76         UFS_UFS_DBG_RD_REG_OCSC                 = 0x800,
  77 
  78         UFS_UFS_DBG_RD_DESC_RAM                 = 0x1500,
  79         UFS_UFS_DBG_RD_PRDT_RAM                 = 0x1700,
  80         UFS_UFS_DBG_RD_RESP_RAM                 = 0x1800,
  81         UFS_UFS_DBG_RD_EDTL_RAM                 = 0x1900,
  82 };
  83 
  84 #define UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(x)      (0x000 + x)
  85 #define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x)      (0x400 + x)
  86 
  87 /* bit definitions for REG_UFS_CFG1 register */
  88 #define QUNIPRO_SEL             0x1
  89 #define UTP_DBG_RAMS_EN         0x20000
  90 #define TEST_BUS_EN             BIT(18)
  91 #define TEST_BUS_SEL            GENMASK(22, 19)
  92 #define UFS_REG_TEST_BUS_EN     BIT(30)
  93 
  94 /* bit definitions for REG_UFS_CFG2 register */
  95 #define UAWM_HW_CGC_EN          (1 << 0)
  96 #define UARM_HW_CGC_EN          (1 << 1)
  97 #define TXUC_HW_CGC_EN          (1 << 2)
  98 #define RXUC_HW_CGC_EN          (1 << 3)
  99 #define DFC_HW_CGC_EN           (1 << 4)
 100 #define TRLUT_HW_CGC_EN         (1 << 5)
 101 #define TMRLUT_HW_CGC_EN        (1 << 6)
 102 #define OCSC_HW_CGC_EN          (1 << 7)
 103 
 104 /* bit definition for UFS_UFS_TEST_BUS_CTRL_n */
 105 #define TEST_BUS_SUB_SEL_MASK   0x1F  /* All XXX_SEL fields are 5 bits wide */
 106 
 107 #define REG_UFS_CFG2_CGC_EN_ALL (UAWM_HW_CGC_EN | UARM_HW_CGC_EN |\
 108                                  TXUC_HW_CGC_EN | RXUC_HW_CGC_EN |\
 109                                  DFC_HW_CGC_EN | TRLUT_HW_CGC_EN |\
 110                                  TMRLUT_HW_CGC_EN | OCSC_HW_CGC_EN)
 111 
 112 /* bit offset */
 113 enum {
 114         OFFSET_UFS_PHY_SOFT_RESET           = 1,
 115         OFFSET_CLK_NS_REG                   = 10,
 116 };
 117 
 118 /* bit masks */
 119 enum {
 120         MASK_UFS_PHY_SOFT_RESET             = 0x2,
 121         MASK_TX_SYMBOL_CLK_1US_REG          = 0x3FF,
 122         MASK_CLK_NS_REG                     = 0xFFFC00,
 123 };
 124 
 125 /* QCOM UFS debug print bit mask */
 126 #define UFS_QCOM_DBG_PRINT_REGS_EN      BIT(0)
 127 #define UFS_QCOM_DBG_PRINT_ICE_REGS_EN  BIT(1)
 128 #define UFS_QCOM_DBG_PRINT_TEST_BUS_EN  BIT(2)
 129 
 130 #define UFS_QCOM_DBG_PRINT_ALL  \
 131         (UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_ICE_REGS_EN | \
 132          UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
 133 
 134 /* QUniPro Vendor specific attributes */
 135 #define PA_VS_CONFIG_REG1       0x9000
 136 #define DME_VS_CORE_CLK_CTRL    0xD002
 137 /* bit and mask definitions for DME_VS_CORE_CLK_CTRL attribute */
 138 #define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT                BIT(8)
 139 #define DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK       0xFF
 140 
 141 static inline void
 142 ufs_qcom_get_controller_revision(struct ufs_hba *hba,
 143                                  u8 *major, u16 *minor, u16 *step)
 144 {
 145         u32 ver = ufshcd_readl(hba, REG_UFS_HW_VERSION);
 146 
 147         *major = (ver & UFS_HW_VER_MAJOR_MASK) >> UFS_HW_VER_MAJOR_SHFT;
 148         *minor = (ver & UFS_HW_VER_MINOR_MASK) >> UFS_HW_VER_MINOR_SHFT;
 149         *step = (ver & UFS_HW_VER_STEP_MASK) >> UFS_HW_VER_STEP_SHFT;
 150 };
 151 
 152 static inline void ufs_qcom_assert_reset(struct ufs_hba *hba)
 153 {
 154         ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET,
 155                         1 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
 156 
 157         /*
 158          * Make sure assertion of ufs phy reset is written to
 159          * register before returning
 160          */
 161         mb();
 162 }
 163 
 164 static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba)
 165 {
 166         ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET,
 167                         0 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
 168 
 169         /*
 170          * Make sure de-assertion of ufs phy reset is written to
 171          * register before returning
 172          */
 173         mb();
 174 }
 175 
 176 struct ufs_qcom_bus_vote {
 177         uint32_t client_handle;
 178         uint32_t curr_vote;
 179         int min_bw_vote;
 180         int max_bw_vote;
 181         int saved_vote;
 182         bool is_max_bw_needed;
 183         struct device_attribute max_bus_bw;
 184 };
 185 
 186 /* Host controller hardware version: major.minor.step */
 187 struct ufs_hw_version {
 188         u16 step;
 189         u16 minor;
 190         u8 major;
 191 };
 192 
 193 struct ufs_qcom_testbus {
 194         u8 select_major;
 195         u8 select_minor;
 196 };
 197 
 198 struct gpio_desc;
 199 
 200 struct ufs_qcom_host {
 201         /*
 202          * Set this capability if host controller supports the QUniPro mode
 203          * and if driver wants the Host controller to operate in QUniPro mode.
 204          * Note: By default this capability will be kept enabled if host
 205          * controller supports the QUniPro mode.
 206          */
 207         #define UFS_QCOM_CAP_QUNIPRO    0x1
 208 
 209         /*
 210          * Set this capability if host controller can retain the secure
 211          * configuration even after UFS controller core power collapse.
 212          */
 213         #define UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE  0x2
 214         u32 caps;
 215 
 216         struct phy *generic_phy;
 217         struct ufs_hba *hba;
 218         struct ufs_qcom_bus_vote bus_vote;
 219         struct ufs_pa_layer_attr dev_req_params;
 220         struct clk *rx_l0_sync_clk;
 221         struct clk *tx_l0_sync_clk;
 222         struct clk *rx_l1_sync_clk;
 223         struct clk *tx_l1_sync_clk;
 224         bool is_lane_clks_enabled;
 225 
 226         void __iomem *dev_ref_clk_ctrl_mmio;
 227         bool is_dev_ref_clk_enabled;
 228         struct ufs_hw_version hw_ver;
 229 
 230         u32 dev_ref_clk_en_mask;
 231 
 232         /* Bitmask for enabling debug prints */
 233         u32 dbg_print_en;
 234         struct ufs_qcom_testbus testbus;
 235 
 236         struct reset_controller_dev rcdev;
 237 
 238         struct gpio_desc *device_reset;
 239 };
 240 
 241 static inline u32
 242 ufs_qcom_get_debug_reg_offset(struct ufs_qcom_host *host, u32 reg)
 243 {
 244         if (host->hw_ver.major <= 0x02)
 245                 return UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(reg);
 246 
 247         return UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(reg);
 248 };
 249 
 250 #define ufs_qcom_is_link_off(hba) ufshcd_is_link_off(hba)
 251 #define ufs_qcom_is_link_active(hba) ufshcd_is_link_active(hba)
 252 #define ufs_qcom_is_link_hibern8(hba) ufshcd_is_link_hibern8(hba)
 253 
 254 int ufs_qcom_testbus_config(struct ufs_qcom_host *host);
 255 
 256 static inline bool ufs_qcom_cap_qunipro(struct ufs_qcom_host *host)
 257 {
 258         if (host->caps & UFS_QCOM_CAP_QUNIPRO)
 259                 return true;
 260         else
 261                 return false;
 262 }
 263 
 264 #endif /* UFS_QCOM_H_ */
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