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36 #ifndef _UFSHCI_H
37 #define _UFSHCI_H
38
39 enum {
40 TASK_REQ_UPIU_SIZE_DWORDS = 8,
41 TASK_RSP_UPIU_SIZE_DWORDS = 8,
42 ALIGNED_UPIU_SIZE = 512,
43 };
44
45
46 enum {
47 REG_CONTROLLER_CAPABILITIES = 0x00,
48 REG_UFS_VERSION = 0x08,
49 REG_CONTROLLER_DEV_ID = 0x10,
50 REG_CONTROLLER_PROD_ID = 0x14,
51 REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18,
52 REG_INTERRUPT_STATUS = 0x20,
53 REG_INTERRUPT_ENABLE = 0x24,
54 REG_CONTROLLER_STATUS = 0x30,
55 REG_CONTROLLER_ENABLE = 0x34,
56 REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
57 REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
58 REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
59 REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
60 REG_UIC_ERROR_CODE_DME = 0x48,
61 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
62 REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
63 REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
64 REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
65 REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
66 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
67 REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
68 REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
69 REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
70 REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
71 REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
72 REG_UIC_COMMAND = 0x90,
73 REG_UIC_COMMAND_ARG_1 = 0x94,
74 REG_UIC_COMMAND_ARG_2 = 0x98,
75 REG_UIC_COMMAND_ARG_3 = 0x9C,
76
77 UFSHCI_REG_SPACE_SIZE = 0xA0,
78
79 REG_UFS_CCAP = 0x100,
80 REG_UFS_CRYPTOCAP = 0x104,
81
82 UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400,
83 };
84
85
86 enum {
87 MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F,
88 MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
89 MASK_AUTO_HIBERN8_SUPPORT = 0x00800000,
90 MASK_64_ADDRESSING_SUPPORT = 0x01000000,
91 MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
92 MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
93 };
94
95 #define UFS_MASK(mask, offset) ((mask) << (offset))
96
97
98 #define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0)
99 #define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16)
100
101
102 enum {
103 UFSHCI_VERSION_10 = 0x00010000,
104 UFSHCI_VERSION_11 = 0x00010100,
105 UFSHCI_VERSION_20 = 0x00000200,
106 UFSHCI_VERSION_21 = 0x00000210,
107 };
108
109
110
111
112
113 #define DEVICE_CLASS UFS_MASK(0xFFFF, 0)
114 #define DEVICE_ID UFS_MASK(0xFF, 24)
115
116
117
118
119
120 #define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0)
121 #define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16)
122
123
124 #define UFSHCI_AHIBERN8_TIMER_MASK GENMASK(9, 0)
125 #define UFSHCI_AHIBERN8_SCALE_MASK GENMASK(12, 10)
126 #define UFSHCI_AHIBERN8_SCALE_FACTOR 10
127 #define UFSHCI_AHIBERN8_MAX (1023 * 100000)
128
129
130
131
132 #define UTP_TRANSFER_REQ_COMPL 0x1
133 #define UIC_DME_END_PT_RESET 0x2
134 #define UIC_ERROR 0x4
135 #define UIC_TEST_MODE 0x8
136 #define UIC_POWER_MODE 0x10
137 #define UIC_HIBERNATE_EXIT 0x20
138 #define UIC_HIBERNATE_ENTER 0x40
139 #define UIC_LINK_LOST 0x80
140 #define UIC_LINK_STARTUP 0x100
141 #define UTP_TASK_REQ_COMPL 0x200
142 #define UIC_COMMAND_COMPL 0x400
143 #define DEVICE_FATAL_ERROR 0x800
144 #define CONTROLLER_FATAL_ERROR 0x10000
145 #define SYSTEM_BUS_FATAL_ERROR 0x20000
146
147 #define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER |\
148 UIC_HIBERNATE_EXIT)
149
150 #define UFSHCD_UIC_PWR_MASK (UFSHCD_UIC_HIBERN8_MASK |\
151 UIC_POWER_MODE)
152
153 #define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK)
154
155 #define UFSHCD_ERROR_MASK (UIC_ERROR |\
156 DEVICE_FATAL_ERROR |\
157 CONTROLLER_FATAL_ERROR |\
158 SYSTEM_BUS_FATAL_ERROR)
159
160 #define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\
161 CONTROLLER_FATAL_ERROR |\
162 SYSTEM_BUS_FATAL_ERROR)
163
164
165 #define DEVICE_PRESENT 0x1
166 #define UTP_TRANSFER_REQ_LIST_READY 0x2
167 #define UTP_TASK_REQ_LIST_READY 0x4
168 #define UIC_COMMAND_READY 0x8
169 #define HOST_ERROR_INDICATOR 0x10
170 #define DEVICE_ERROR_INDICATOR 0x20
171 #define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
172
173 #define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\
174 UTP_TASK_REQ_LIST_READY |\
175 UIC_COMMAND_READY)
176
177 enum {
178 PWR_OK = 0x0,
179 PWR_LOCAL = 0x01,
180 PWR_REMOTE = 0x02,
181 PWR_BUSY = 0x03,
182 PWR_ERROR_CAP = 0x04,
183 PWR_FATAL_ERROR = 0x05,
184 };
185
186
187 #define CONTROLLER_ENABLE 0x1
188 #define CONTROLLER_DISABLE 0x0
189 #define CRYPTO_GENERAL_ENABLE 0x2
190
191
192 #define UIC_PHY_ADAPTER_LAYER_ERROR 0x80000000
193 #define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F
194 #define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK 0xF
195
196
197 #define UIC_DATA_LINK_LAYER_ERROR 0x80000000
198 #define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0x7FFF
199 #define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP 0x2
200 #define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP 0x4
201 #define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP 0x8
202 #define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF 0x20
203 #define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000
204 #define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001
205 #define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002
206
207
208 #define UIC_NETWORK_LAYER_ERROR 0x80000000
209 #define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7
210 #define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE 0x1
211 #define UIC_NETWORK_BAD_DEVICEID_ENC 0x2
212 #define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING 0x4
213
214
215 #define UIC_TRANSPORT_LAYER_ERROR 0x80000000
216 #define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F
217 #define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE 0x1
218 #define UIC_TRANSPORT_UNKNOWN_CPORTID 0x2
219 #define UIC_TRANSPORT_NO_CONNECTION_RX 0x4
220 #define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING 0x8
221 #define UIC_TRANSPORT_BAD_TC 0x10
222 #define UIC_TRANSPORT_E2E_CREDIT_OVERFOW 0x20
223 #define UIC_TRANSPORT_SAFETY_VALUE_DROPPING 0x40
224
225
226 #define UIC_DME_ERROR 0x80000000
227 #define UIC_DME_ERROR_CODE_MASK 0x1
228
229
230 #define INT_AGGR_TIMEOUT_VAL_MASK 0xFF
231 #define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8)
232 #define INT_AGGR_COUNTER_AND_TIMER_RESET 0x10000
233 #define INT_AGGR_STATUS_BIT 0x100000
234 #define INT_AGGR_PARAM_WRITE 0x1000000
235 #define INT_AGGR_ENABLE 0x80000000
236
237
238 #define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1
239
240
241 #define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1
242
243
244 #define COMMAND_OPCODE_MASK 0xFF
245 #define GEN_SELECTOR_INDEX_MASK 0xFFFF
246
247 #define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
248 #define RESET_LEVEL 0xFF
249
250 #define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
251 #define CONFIG_RESULT_CODE_MASK 0xFF
252 #define GENERIC_ERROR_CODE_MASK 0xFF
253
254
255 #define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
256 #define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
257
258 #define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
259 ((sel) & 0xFFFF))
260 #define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
261 #define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
262 #define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
263
264
265 enum link_status {
266 UFSHCD_LINK_IS_DOWN = 1,
267 UFSHCD_LINK_IS_UP = 2,
268 };
269
270
271 enum uic_cmd_dme {
272 UIC_CMD_DME_GET = 0x01,
273 UIC_CMD_DME_SET = 0x02,
274 UIC_CMD_DME_PEER_GET = 0x03,
275 UIC_CMD_DME_PEER_SET = 0x04,
276 UIC_CMD_DME_POWERON = 0x10,
277 UIC_CMD_DME_POWEROFF = 0x11,
278 UIC_CMD_DME_ENABLE = 0x12,
279 UIC_CMD_DME_RESET = 0x14,
280 UIC_CMD_DME_END_PT_RST = 0x15,
281 UIC_CMD_DME_LINK_STARTUP = 0x16,
282 UIC_CMD_DME_HIBER_ENTER = 0x17,
283 UIC_CMD_DME_HIBER_EXIT = 0x18,
284 UIC_CMD_DME_TEST_MODE = 0x1A,
285 };
286
287
288 enum {
289 UIC_CMD_RESULT_SUCCESS = 0x00,
290 UIC_CMD_RESULT_INVALID_ATTR = 0x01,
291 UIC_CMD_RESULT_FAILURE = 0x01,
292 UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
293 UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
294 UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
295 UIC_CMD_RESULT_BAD_INDEX = 0x05,
296 UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
297 UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
298 UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
299 UIC_CMD_RESULT_BUSY = 0x09,
300 UIC_CMD_RESULT_DME_FAILURE = 0x0A,
301 };
302
303 #define MASK_UIC_COMMAND_RESULT 0xFF
304
305 #define INT_AGGR_COUNTER_THLD_VAL(c) (((c) & 0x1F) << 8)
306 #define INT_AGGR_TIMEOUT_VAL(t) (((t) & 0xFF) << 0)
307
308
309 enum {
310
311 INTERRUPT_MASK_ALL_VER_10 = 0x30FFF,
312 INTERRUPT_MASK_RW_VER_10 = 0x30000,
313
314
315 INTERRUPT_MASK_ALL_VER_11 = 0x31FFF,
316
317
318 INTERRUPT_MASK_ALL_VER_21 = 0x71FFF,
319 };
320
321
322
323
324
325
326 enum {
327 UTP_CMD_TYPE_SCSI = 0x0,
328 UTP_CMD_TYPE_UFS = 0x1,
329 UTP_CMD_TYPE_DEV_MANAGE = 0x2,
330 };
331
332
333 enum {
334 UTP_CMD_TYPE_UFS_STORAGE = 0x1,
335 };
336
337 enum {
338 UTP_SCSI_COMMAND = 0x00000000,
339 UTP_NATIVE_UFS_COMMAND = 0x10000000,
340 UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
341 UTP_REQ_DESC_INT_CMD = 0x01000000,
342 };
343
344
345 enum {
346 UTP_NO_DATA_TRANSFER = 0x00000000,
347 UTP_HOST_TO_DEVICE = 0x02000000,
348 UTP_DEVICE_TO_HOST = 0x04000000,
349 };
350
351
352 enum {
353 OCS_SUCCESS = 0x0,
354 OCS_INVALID_CMD_TABLE_ATTR = 0x1,
355 OCS_INVALID_PRDT_ATTR = 0x2,
356 OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
357 OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
358 OCS_PEER_COMM_FAILURE = 0x5,
359 OCS_ABORTED = 0x6,
360 OCS_FATAL_ERROR = 0x7,
361 OCS_INVALID_COMMAND_STATUS = 0x0F,
362 MASK_OCS = 0x0F,
363 };
364
365
366 #define PRDT_DATA_BYTE_COUNT_MAX (256 * 1024)
367
368 #define PRDT_DATA_BYTE_COUNT_PAD 4
369
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371
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374
375
376
377 struct ufshcd_sg_entry {
378 __le32 base_addr;
379 __le32 upper_addr;
380 __le32 reserved;
381 __le32 size;
382 };
383
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386
387
388
389
390 struct utp_transfer_cmd_desc {
391 u8 command_upiu[ALIGNED_UPIU_SIZE];
392 u8 response_upiu[ALIGNED_UPIU_SIZE];
393 struct ufshcd_sg_entry prd_table[SG_ALL];
394 };
395
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401
402
403 struct request_desc_header {
404 __le32 dword_0;
405 __le32 dword_1;
406 __le32 dword_2;
407 __le32 dword_3;
408 };
409
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417
418
419
420 struct utp_transfer_req_desc {
421
422
423 struct request_desc_header header;
424
425
426 __le32 command_desc_base_addr_lo;
427 __le32 command_desc_base_addr_hi;
428
429
430 __le16 response_upiu_length;
431 __le16 response_upiu_offset;
432
433
434 __le16 prd_table_length;
435 __le16 prd_table_offset;
436 };
437
438
439
440
441 struct utp_task_req_desc {
442
443 struct request_desc_header header;
444
445
446 struct utp_upiu_header req_header;
447 __be32 input_param1;
448 __be32 input_param2;
449 __be32 input_param3;
450 __be32 __reserved1[2];
451
452
453 struct utp_upiu_header rsp_header;
454 __be32 output_param1;
455 __be32 output_param2;
456 __be32 __reserved2[3];
457 };
458
459 #endif