1 /*
2 * Core definitions and data structures shareable across OS platforms.
3 *
4 * Copyright (c) 1994-2002 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
26 *
27 * NO WARRANTY
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
39 *
40 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.h#109 $
41 *
42 * $FreeBSD$
43 */
44
45 #ifndef _AIC79XX_H_
46 #define _AIC79XX_H_
47
48 /* Register Definitions */
49 #include "aic79xx_reg.h"
50
51 /************************* Forward Declarations *******************************/
52 struct ahd_platform_data;
53 struct scb_platform_data;
54
55 /****************************** Useful Macros *********************************/
56 #ifndef TRUE
57 #define TRUE 1
58 #endif
59 #ifndef FALSE
60 #define FALSE 0
61 #endif
62
63 #define ALL_CHANNELS '\0'
64 #define ALL_TARGETS_MASK 0xFFFF
65 #define INITIATOR_WILDCARD (~0)
66 #define SCB_LIST_NULL 0xFF00
67 #define SCB_LIST_NULL_LE (ahd_htole16(SCB_LIST_NULL))
68 #define QOUTFIFO_ENTRY_VALID 0x80
69 #define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL)
70
71 #define SCSIID_TARGET(ahd, scsiid) \
72 (((scsiid) & TID) >> TID_SHIFT)
73 #define SCSIID_OUR_ID(scsiid) \
74 ((scsiid) & OID)
75 #define SCSIID_CHANNEL(ahd, scsiid) ('A')
76 #define SCB_IS_SCSIBUS_B(ahd, scb) (0)
77 #define SCB_GET_OUR_ID(scb) \
78 SCSIID_OUR_ID((scb)->hscb->scsiid)
79 #define SCB_GET_TARGET(ahd, scb) \
80 SCSIID_TARGET((ahd), (scb)->hscb->scsiid)
81 #define SCB_GET_CHANNEL(ahd, scb) \
82 SCSIID_CHANNEL(ahd, (scb)->hscb->scsiid)
83 #define SCB_GET_LUN(scb) \
84 ((scb)->hscb->lun)
85 #define SCB_GET_TARGET_OFFSET(ahd, scb) \
86 SCB_GET_TARGET(ahd, scb)
87 #define SCB_GET_TARGET_MASK(ahd, scb) \
88 (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb)))
89 #ifdef AHD_DEBUG
90 #define SCB_IS_SILENT(scb) \
91 ((ahd_debug & AHD_SHOW_MASKED_ERRORS) == 0 \
92 && (((scb)->flags & SCB_SILENT) != 0))
93 #else
94 #define SCB_IS_SILENT(scb) \
95 (((scb)->flags & SCB_SILENT) != 0)
96 #endif
97 /*
98 * TCLs have the following format: TTTTLLLLLLLL
99 */
100 #define TCL_TARGET_OFFSET(tcl) \
101 ((((tcl) >> 4) & TID) >> 4)
102 #define TCL_LUN(tcl) \
103 (tcl & (AHD_NUM_LUNS - 1))
104 #define BUILD_TCL(scsiid, lun) \
105 ((lun) | (((scsiid) & TID) << 4))
106 #define BUILD_TCL_RAW(target, channel, lun) \
107 ((lun) | ((target) << 8))
108
109 #define SCB_GET_TAG(scb) \
110 ahd_le16toh(scb->hscb->tag)
111
112 #ifndef AHD_TARGET_MODE
113 #undef AHD_TMODE_ENABLE
114 #define AHD_TMODE_ENABLE 0
115 #endif
116
117 #define AHD_BUILD_COL_IDX(target, lun) \
118 ((((u8)lun) << 4) | target)
119
120 #define AHD_GET_SCB_COL_IDX(ahd, scb) \
121 ((SCB_GET_LUN(scb) << 4) | SCB_GET_TARGET(ahd, scb))
122
123 #define AHD_SET_SCB_COL_IDX(scb, col_idx) \
124 do { \
125 (scb)->hscb->scsiid = ((col_idx) << TID_SHIFT) & TID; \
126 (scb)->hscb->lun = ((col_idx) >> 4) & (AHD_NUM_LUNS_NONPKT-1); \
127 } while (0)
128
129 #define AHD_COPY_SCB_COL_IDX(dst, src) \
130 do { \
131 dst->hscb->scsiid = src->hscb->scsiid; \
132 dst->hscb->lun = src->hscb->lun; \
133 } while (0)
134
135 #define AHD_NEVER_COL_IDX 0xFFFF
136
137 /**************************** Driver Constants ********************************/
138 /*
139 * The maximum number of supported targets.
140 */
141 #define AHD_NUM_TARGETS 16
142
143 /*
144 * The maximum number of supported luns.
145 * The identify message only supports 64 luns in non-packetized transfers.
146 * You can have 2^64 luns when information unit transfers are enabled,
147 * but until we see a need to support that many, we support 256.
148 */
149 #define AHD_NUM_LUNS_NONPKT 64
150 #define AHD_NUM_LUNS 256
151
152 /*
153 * The maximum transfer per S/G segment.
154 */
155 #define AHD_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */
156
157 /*
158 * The maximum amount of SCB storage in hardware on a controller.
159 * This value represents an upper bound. Due to software design,
160 * we may not be able to use this number.
161 */
162 #define AHD_SCB_MAX 512
163
164 /*
165 * The maximum number of concurrent transactions supported per driver instance.
166 * Sequencer Control Blocks (SCBs) store per-transaction information.
167 */
168 #define AHD_MAX_QUEUE AHD_SCB_MAX
169
170 /*
171 * Define the size of our QIN and QOUT FIFOs. They must be a power of 2
172 * in size and accommodate as many transactions as can be queued concurrently.
173 */
174 #define AHD_QIN_SIZE AHD_MAX_QUEUE
175 #define AHD_QOUT_SIZE AHD_MAX_QUEUE
176
177 #define AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1))
178 /*
179 * The maximum amount of SCB storage we allocate in host memory.
180 */
181 #define AHD_SCB_MAX_ALLOC AHD_MAX_QUEUE
182
183 /*
184 * Ring Buffer of incoming target commands.
185 * We allocate 256 to simplify the logic in the sequencer
186 * by using the natural wrap point of an 8bit counter.
187 */
188 #define AHD_TMODE_CMDS 256
189
190 /* Reset line assertion time in us */
191 #define AHD_BUSRESET_DELAY 25
192
193 /******************* Chip Characteristics/Operating Settings *****************/
194 /*
195 * Chip Type
196 * The chip order is from least sophisticated to most sophisticated.
197 */
198 typedef enum {
199 AHD_NONE = 0x0000,
200 AHD_CHIPID_MASK = 0x00FF,
201 AHD_AIC7901 = 0x0001,
202 AHD_AIC7902 = 0x0002,
203 AHD_AIC7901A = 0x0003,
204 AHD_PCI = 0x0100, /* Bus type PCI */
205 AHD_PCIX = 0x0200, /* Bus type PCIX */
206 AHD_BUS_MASK = 0x0F00
207 } ahd_chip;
208
209 /*
210 * Features available in each chip type.
211 */
212 typedef enum {
213 AHD_FENONE = 0x00000,
214 AHD_WIDE = 0x00001,/* Wide Channel */
215 AHD_AIC79XXB_SLOWCRC = 0x00002,/* SLOWCRC bit should be set */
216 AHD_MULTI_FUNC = 0x00100,/* Multi-Function/Channel Device */
217 AHD_TARGETMODE = 0x01000,/* Has tested target mode support */
218 AHD_MULTIROLE = 0x02000,/* Space for two roles at a time */
219 AHD_RTI = 0x04000,/* Retained Training Support */
220 AHD_NEW_IOCELL_OPTS = 0x08000,/* More Signal knobs in the IOCELL */
221 AHD_NEW_DFCNTRL_OPTS = 0x10000,/* SCSIENWRDIS bit */
222 AHD_FAST_CDB_DELIVERY = 0x20000,/* CDB acks released to Output Sync */
223 AHD_REMOVABLE = 0x00000,/* Hot-Swap supported - None so far*/
224 AHD_AIC7901_FE = AHD_FENONE,
225 AHD_AIC7901A_FE = AHD_FENONE,
226 AHD_AIC7902_FE = AHD_MULTI_FUNC
227 } ahd_feature;
228
229 /*
230 * Bugs in the silicon that we work around in software.
231 */
232 typedef enum {
233 AHD_BUGNONE = 0x0000,
234 /*
235 * Rev A hardware fails to update LAST/CURR/NEXTSCB
236 * correctly in certain packetized selection cases.
237 */
238 AHD_SENT_SCB_UPDATE_BUG = 0x0001,
239 /* The wrong SCB is accessed to check the abort pending bit. */
240 AHD_ABORT_LQI_BUG = 0x0002,
241 /* Packetized bitbucket crosses packet boundaries. */
242 AHD_PKT_BITBUCKET_BUG = 0x0004,
243 /* The selection timer runs twice as long as its setting. */
244 AHD_LONG_SETIMO_BUG = 0x0008,
245 /* The Non-LQ CRC error status is delayed until phase change. */
246 AHD_NLQICRC_DELAYED_BUG = 0x0010,
247 /* The chip must be reset for all outgoing bus resets. */
248 AHD_SCSIRST_BUG = 0x0020,
249 /* Some PCIX fields must be saved and restored across chip reset. */
250 AHD_PCIX_CHIPRST_BUG = 0x0040,
251 /* MMAPIO is not functional in PCI-X mode. */
252 AHD_PCIX_MMAPIO_BUG = 0x0080,
253 /* Reads to SCBRAM fail to reset the discard timer. */
254 AHD_PCIX_SCBRAM_RD_BUG = 0x0100,
255 /* Bug workarounds that can be disabled on non-PCIX busses. */
256 AHD_PCIX_BUG_MASK = AHD_PCIX_CHIPRST_BUG
257 | AHD_PCIX_MMAPIO_BUG
258 | AHD_PCIX_SCBRAM_RD_BUG,
259 /*
260 * LQOSTOP0 status set even for forced selections with ATN
261 * to perform non-packetized message delivery.
262 */
263 AHD_LQO_ATNO_BUG = 0x0200,
264 /* FIFO auto-flush does not always trigger. */
265 AHD_AUTOFLUSH_BUG = 0x0400,
266 /* The CLRLQO registers are not self-clearing. */
267 AHD_CLRLQO_AUTOCLR_BUG = 0x0800,
268 /* The PACKETIZED status bit refers to the previous connection. */
269 AHD_PKTIZED_STATUS_BUG = 0x1000,
270 /* "Short Luns" are not placed into outgoing LQ packets correctly. */
271 AHD_PKT_LUN_BUG = 0x2000,
272 /*
273 * Only the FIFO allocated to the non-packetized connection may
274 * be in use during a non-packetzied connection.
275 */
276 AHD_NONPACKFIFO_BUG = 0x4000,
277 /*
278 * Writing to a DFF SCBPTR register may fail if concurent with
279 * a hardware write to the other DFF SCBPTR register. This is
280 * not currently a concern in our sequencer since all chips with
281 * this bug have the AHD_NONPACKFIFO_BUG and all writes of concern
282 * occur in non-packetized connections.
283 */
284 AHD_MDFF_WSCBPTR_BUG = 0x8000,
285 /* SGHADDR updates are slow. */
286 AHD_REG_SLOW_SETTLE_BUG = 0x10000,
287 /*
288 * Changing the MODE_PTR coincident with an interrupt that
289 * switches to a different mode will cause the interrupt to
290 * be in the mode written outside of interrupt context.
291 */
292 AHD_SET_MODE_BUG = 0x20000,
293 /* Non-packetized busfree revision does not work. */
294 AHD_BUSFREEREV_BUG = 0x40000,
295 /*
296 * Paced transfers are indicated with a non-standard PPR
297 * option bit in the neg table, 160MHz is indicated by
298 * sync factor 0x7, and the offset if off by a factor of 2.
299 */
300 AHD_PACED_NEGTABLE_BUG = 0x80000,
301 /* LQOOVERRUN false positives. */
302 AHD_LQOOVERRUN_BUG = 0x100000,
303 /*
304 * Controller write to INTSTAT will lose to a host
305 * write to CLRINT.
306 */
307 AHD_INTCOLLISION_BUG = 0x200000,
308 /*
309 * The GEM318 violates the SCSI spec by not waiting
310 * the mandated bus settle delay between phase changes
311 * in some situations. Some aic79xx chip revs. are more
312 * strict in this regard and will treat REQ assertions
313 * that fall within the bus settle delay window as
314 * glitches. This flag tells the firmware to tolerate
315 * early REQ assertions.
316 */
317 AHD_EARLY_REQ_BUG = 0x400000,
318 /*
319 * The LED does not stay on long enough in packetized modes.
320 */
321 AHD_FAINT_LED_BUG = 0x800000
322 } ahd_bug;
323
324 /*
325 * Configuration specific settings.
326 * The driver determines these settings by probing the
327 * chip/controller's configuration.
328 */
329 typedef enum {
330 AHD_FNONE = 0x00000,
331 AHD_BOOT_CHANNEL = 0x00001,/* We were set as the boot channel. */
332 AHD_USEDEFAULTS = 0x00004,/*
333 * For cards without an seeprom
334 * or a BIOS to initialize the chip's
335 * SRAM, we use the default target
336 * settings.
337 */
338 AHD_SEQUENCER_DEBUG = 0x00008,
339 AHD_RESET_BUS_A = 0x00010,
340 AHD_EXTENDED_TRANS_A = 0x00020,
341 AHD_TERM_ENB_A = 0x00040,
342 AHD_SPCHK_ENB_A = 0x00080,
343 AHD_STPWLEVEL_A = 0x00100,
344 AHD_INITIATORROLE = 0x00200,/*
345 * Allow initiator operations on
346 * this controller.
347 */
348 AHD_TARGETROLE = 0x00400,/*
349 * Allow target operations on this
350 * controller.
351 */
352 AHD_RESOURCE_SHORTAGE = 0x00800,
353 AHD_TQINFIFO_BLOCKED = 0x01000,/* Blocked waiting for ATIOs */
354 AHD_INT50_SPEEDFLEX = 0x02000,/*
355 * Internal 50pin connector
356 * sits behind an aic3860
357 */
358 AHD_BIOS_ENABLED = 0x04000,
359 AHD_ALL_INTERRUPTS = 0x08000,
360 AHD_39BIT_ADDRESSING = 0x10000,/* Use 39 bit addressing scheme. */
361 AHD_64BIT_ADDRESSING = 0x20000,/* Use 64 bit addressing scheme. */
362 AHD_CURRENT_SENSING = 0x40000,
363 AHD_SCB_CONFIG_USED = 0x80000,/* No SEEPROM but SCB had info. */
364 AHD_HP_BOARD = 0x100000,
365 AHD_BUS_RESET_ACTIVE = 0x200000,
366 AHD_UPDATE_PEND_CMDS = 0x400000,
367 AHD_RUNNING_QOUTFIFO = 0x800000,
368 AHD_HAD_FIRST_SEL = 0x1000000
369 } ahd_flag;
370
371 /************************* Hardware SCB Definition ***************************/
372
373 /*
374 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB
375 * consists of a "hardware SCB" mirroring the fields available on the card
376 * and additional information the kernel stores for each transaction.
377 *
378 * To minimize space utilization, a portion of the hardware scb stores
379 * different data during different portions of a SCSI transaction.
380 * As initialized by the host driver for the initiator role, this area
381 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After
382 * the cdb has been presented to the target, this area serves to store
383 * residual transfer information and the SCSI status byte.
384 * For the target role, the contents of this area do not change, but
385 * still serve a different purpose than for the initiator role. See
386 * struct target_data for details.
387 */
388
389 /*
390 * Status information embedded in the shared poriton of
391 * an SCB after passing the cdb to the target. The kernel
392 * driver will only read this data for transactions that
393 * complete abnormally.
394 */
395 struct initiator_status {
396 uint32_t residual_datacnt; /* Residual in the current S/G seg */
397 uint32_t residual_sgptr; /* The next S/G for this transfer */
398 uint8_t scsi_status; /* Standard SCSI status byte */
399 };
400
401 struct target_status {
402 uint32_t residual_datacnt; /* Residual in the current S/G seg */
403 uint32_t residual_sgptr; /* The next S/G for this transfer */
404 uint8_t scsi_status; /* SCSI status to give to initiator */
405 uint8_t target_phases; /* Bitmap of phases to execute */
406 uint8_t data_phase; /* Data-In or Data-Out */
407 uint8_t initiator_tag; /* Initiator's transaction tag */
408 };
409
410 /*
411 * Initiator mode SCB shared data area.
412 * If the embedded CDB is 12 bytes or less, we embed
413 * the sense buffer address in the SCB. This allows
414 * us to retrieve sense information without interrupting
415 * the host in packetized mode.
416 */
417 typedef uint32_t sense_addr_t;
418 #define MAX_CDB_LEN 16
419 #define MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t))
420 union initiator_data {
421 struct {
422 uint64_t cdbptr;
423 uint8_t cdblen;
424 } cdb_from_host;
425 uint8_t cdb[MAX_CDB_LEN];
426 struct {
427 uint8_t cdb[MAX_CDB_LEN_WITH_SENSE_ADDR];
428 sense_addr_t sense_addr;
429 } cdb_plus_saddr;
430 };
431
432 /*
433 * Target mode version of the shared data SCB segment.
434 */
435 struct target_data {
436 uint32_t spare[2];
437 uint8_t scsi_status; /* SCSI status to give to initiator */
438 uint8_t target_phases; /* Bitmap of phases to execute */
439 uint8_t data_phase; /* Data-In or Data-Out */
440 uint8_t initiator_tag; /* Initiator's transaction tag */
441 };
442
443 struct hardware_scb {
444 /*0*/ union {
445 union initiator_data idata;
446 struct target_data tdata;
447 struct initiator_status istatus;
448 struct target_status tstatus;
449 } shared_data;
450 /*
451 * A word about residuals.
452 * The scb is presented to the sequencer with the dataptr and datacnt
453 * fields initialized to the contents of the first S/G element to
454 * transfer. The sgptr field is initialized to the bus address for
455 * the S/G element that follows the first in the in core S/G array
456 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid
457 * S/G entry for this transfer (single S/G element transfer with the
458 * first elements address and length preloaded in the dataptr/datacnt
459 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL.
460 * The SG_FULL_RESID flag ensures that the residual will be correctly
461 * noted even if no data transfers occur. Once the data phase is entered,
462 * the residual sgptr and datacnt are loaded from the sgptr and the
463 * datacnt fields. After each S/G element's dataptr and length are
464 * loaded into the hardware, the residual sgptr is advanced. After
465 * each S/G element is expired, its datacnt field is checked to see
466 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the
467 * residual sg ptr and the transfer is considered complete. If the
468 * sequencer determines that there is a residual in the tranfer, or
469 * there is non-zero status, it will set the SG_STATUS_VALID flag in
470 * sgptr and dma the scb back into host memory. To sumarize:
471 *
472 * Sequencer:
473 * o A residual has occurred if SG_FULL_RESID is set in sgptr,
474 * or residual_sgptr does not have SG_LIST_NULL set.
475 *
476 * o We are transferring the last segment if residual_datacnt has
477 * the SG_LAST_SEG flag set.
478 *
479 * Host:
480 * o A residual can only have occurred if a completed scb has the
481 * SG_STATUS_VALID flag set. Inspection of the SCSI status field,
482 * the residual_datacnt, and the residual_sgptr field will tell
483 * for sure.
484 *
485 * o residual_sgptr and sgptr refer to the "next" sg entry
486 * and so may point beyond the last valid sg entry for the
487 * transfer.
488 */
489 #define SG_PTR_MASK 0xFFFFFFF8
490 /*16*/ uint16_t tag; /* Reused by Sequencer. */
491 /*18*/ uint8_t control; /* See SCB_CONTROL in aic79xx.reg for details */
492 /*19*/ uint8_t scsiid; /*
493 * Selection out Id
494 * Our Id (bits 0-3) Their ID (bits 4-7)
495 */
496 /*20*/ uint8_t lun;
497 /*21*/ uint8_t task_attribute;
498 /*22*/ uint8_t cdb_len;
499 /*23*/ uint8_t task_management;
500 /*24*/ uint64_t dataptr;
501 /*32*/ uint32_t datacnt; /* Byte 3 is spare. */
502 /*36*/ uint32_t sgptr;
503 /*40*/ uint32_t hscb_busaddr;
504 /*44*/ uint32_t next_hscb_busaddr;
505 /********** Long lun field only downloaded for full 8 byte lun support ********/
506 /*48*/ uint8_t pkt_long_lun[8];
507 /******* Fields below are not Downloaded (Sequencer may use for scratch) ******/
508 /*56*/ uint8_t spare[8];
509 };
510
511 /************************ Kernel SCB Definitions ******************************/
512 /*
513 * Some fields of the SCB are OS dependent. Here we collect the
514 * definitions for elements that all OS platforms need to include
515 * in there SCB definition.
516 */
517
518 /*
519 * Definition of a scatter/gather element as transferred to the controller.
520 * The aic7xxx chips only support a 24bit length. We use the top byte of
521 * the length to store additional address bits and a flag to indicate
522 * that a given segment terminates the transfer. This gives us an
523 * addressable range of 512GB on machines with 64bit PCI or with chips
524 * that can support dual address cycles on 32bit PCI busses.
525 */
526 struct ahd_dma_seg {
527 uint32_t addr;
528 uint32_t len;
529 #define AHD_DMA_LAST_SEG 0x80000000
530 #define AHD_SG_HIGH_ADDR_MASK 0x7F000000
531 #define AHD_SG_LEN_MASK 0x00FFFFFF
532 };
533
534 struct ahd_dma64_seg {
535 uint64_t addr;
536 uint32_t len;
537 uint32_t pad;
538 };
539
540 struct map_node {
541 bus_dmamap_t dmamap;
542 dma_addr_t physaddr;
543 uint8_t *vaddr;
544 SLIST_ENTRY(map_node) links;
545 };
546
547 /*
548 * The current state of this SCB.
549 */
550 typedef enum {
551 SCB_FLAG_NONE = 0x00000,
552 SCB_TRANSMISSION_ERROR = 0x00001,/*
553 * We detected a parity or CRC
554 * error that has effected the
555 * payload of the command. This
556 * flag is checked when normal
557 * status is returned to catch
558 * the case of a target not
559 * responding to our attempt
560 * to report the error.
561 */
562 SCB_OTHERTCL_TIMEOUT = 0x00002,/*
563 * Another device was active
564 * during the first timeout for
565 * this SCB so we gave ourselves
566 * an additional timeout period
567 * in case it was hogging the
568 * bus.
569 */
570 SCB_DEVICE_RESET = 0x00004,
571 SCB_SENSE = 0x00008,
572 SCB_CDB32_PTR = 0x00010,
573 SCB_RECOVERY_SCB = 0x00020,
574 SCB_AUTO_NEGOTIATE = 0x00040,/* Negotiate to achieve goal. */
575 SCB_NEGOTIATE = 0x00080,/* Negotiation forced for command. */
576 SCB_ABORT = 0x00100,
577 SCB_ACTIVE = 0x00200,
578 SCB_TARGET_IMMEDIATE = 0x00400,
579 SCB_PACKETIZED = 0x00800,
580 SCB_EXPECT_PPR_BUSFREE = 0x01000,
581 SCB_PKT_SENSE = 0x02000,
582 SCB_EXTERNAL_RESET = 0x04000,/* Device was reset externally */
583 SCB_ON_COL_LIST = 0x08000,
584 SCB_SILENT = 0x10000 /*
585 * Be quiet about transmission type
586 * errors. They are expected and we
587 * don't want to upset the user. This
588 * flag is typically used during DV.
589 */
590 } scb_flag;
591
592 struct scb {
593 struct hardware_scb *hscb;
594 union {
595 SLIST_ENTRY(scb) sle;
596 LIST_ENTRY(scb) le;
597 TAILQ_ENTRY(scb) tqe;
598 } links;
599 union {
600 SLIST_ENTRY(scb) sle;
601 LIST_ENTRY(scb) le;
602 TAILQ_ENTRY(scb) tqe;
603 } links2;
604 #define pending_links links2.le
605 #define collision_links links2.le
606 struct scb *col_scb;
607 ahd_io_ctx_t io_ctx;
608 struct ahd_softc *ahd_softc;
609 scb_flag flags;
610 struct scb_platform_data *platform_data;
611 struct map_node *hscb_map;
612 struct map_node *sg_map;
613 struct map_node *sense_map;
614 void *sg_list;
615 uint8_t *sense_data;
616 dma_addr_t sg_list_busaddr;
617 dma_addr_t sense_busaddr;
618 u_int sg_count;/* How full ahd_dma_seg is */
619 #define AHD_MAX_LQ_CRC_ERRORS 5
620 u_int crc_retry_count;
621 };
622
623 TAILQ_HEAD(scb_tailq, scb);
624 BSD_LIST_HEAD(scb_list, scb);
625
626 struct scb_data {
627 /*
628 * TAILQ of lists of free SCBs grouped by device
629 * collision domains.
630 */
631 struct scb_tailq free_scbs;
632
633 /*
634 * Per-device lists of SCBs whose tag ID would collide
635 * with an already active tag on the device.
636 */
637 struct scb_list free_scb_lists[AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT];
638
639 /*
640 * SCBs that will not collide with any active device.
641 */
642 struct scb_list any_dev_free_scb_list;
643
644 /*
645 * Mapping from tag to SCB.
646 */
647 struct scb *scbindex[AHD_SCB_MAX];
648
649 /*
650 * "Bus" addresses of our data structures.
651 */
652 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */
653 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */
654 bus_dma_tag_t sense_dmat; /* dmat for our sense buffers */
655 SLIST_HEAD(, map_node) hscb_maps;
656 SLIST_HEAD(, map_node) sg_maps;
657 SLIST_HEAD(, map_node) sense_maps;
658 int scbs_left; /* unallocated scbs in head map_node */
659 int sgs_left; /* unallocated sgs in head map_node */
660 int sense_left; /* unallocated sense in head map_node */
661 uint16_t numscbs;
662 uint16_t maxhscbs; /* Number of SCBs on the card */
663 uint8_t init_level; /*
664 * How far we've initialized
665 * this structure.
666 */
667 };
668
669 /************************ Target Mode Definitions *****************************/
670
671 /*
672 * Connection descriptor for select-in requests in target mode.
673 */
674 struct target_cmd {
675 uint8_t scsiid; /* Our ID and the initiator's ID */
676 uint8_t identify; /* Identify message */
677 uint8_t bytes[22]; /*
678 * Bytes contains any additional message
679 * bytes terminated by 0xFF. The remainder
680 * is the cdb to execute.
681 */
682 uint8_t cmd_valid; /*
683 * When a command is complete, the firmware
684 * will set cmd_valid to all bits set.
685 * After the host has seen the command,
686 * the bits are cleared. This allows us
687 * to just peek at host memory to determine
688 * if more work is complete. cmd_valid is on
689 * an 8 byte boundary to simplify setting
690 * it on aic7880 hardware which only has
691 * limited direct access to the DMA FIFO.
692 */
693 uint8_t pad[7];
694 };
695
696 /*
697 * Number of events we can buffer up if we run out
698 * of immediate notify ccbs.
699 */
700 #define AHD_TMODE_EVENT_BUFFER_SIZE 8
701 struct ahd_tmode_event {
702 uint8_t initiator_id;
703 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */
704 #define EVENT_TYPE_BUS_RESET 0xFF
705 uint8_t event_arg;
706 };
707
708 /*
709 * Per enabled lun target mode state.
710 * As this state is directly influenced by the host OS'es target mode
711 * environment, we let the OS module define it. Forward declare the
712 * structure here so we can store arrays of them, etc. in OS neutral
713 * data structures.
714 */
715 #ifdef AHD_TARGET_MODE
716 struct ahd_tmode_lstate {
717 struct cam_path *path;
718 struct ccb_hdr_slist accept_tios;
719 struct ccb_hdr_slist immed_notifies;
720 struct ahd_tmode_event event_buffer[AHD_TMODE_EVENT_BUFFER_SIZE];
721 uint8_t event_r_idx;
722 uint8_t event_w_idx;
723 };
724 #else
725 struct ahd_tmode_lstate;
726 #endif
727
728 /******************** Transfer Negotiation Datastructures *********************/
729 #define AHD_TRANS_CUR 0x01 /* Modify current neogtiation status */
730 #define AHD_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */
731 #define AHD_TRANS_GOAL 0x04 /* Modify negotiation goal */
732 #define AHD_TRANS_USER 0x08 /* Modify user negotiation settings */
733 #define AHD_PERIOD_10MHz 0x19
734
735 #define AHD_WIDTH_UNKNOWN 0xFF
736 #define AHD_PERIOD_UNKNOWN 0xFF
737 #define AHD_OFFSET_UNKNOWN 0xFF
738 #define AHD_PPR_OPTS_UNKNOWN 0xFF
739
740 /*
741 * Transfer Negotiation Information.
742 */
743 struct ahd_transinfo {
744 uint8_t protocol_version; /* SCSI Revision level */
745 uint8_t transport_version; /* SPI Revision level */
746 uint8_t width; /* Bus width */
747 uint8_t period; /* Sync rate factor */
748 uint8_t offset; /* Sync offset */
749 uint8_t ppr_options; /* Parallel Protocol Request options */
750 };
751
752 /*
753 * Per-initiator current, goal and user transfer negotiation information. */
754 struct ahd_initiator_tinfo {
755 struct ahd_transinfo curr;
756 struct ahd_transinfo goal;
757 struct ahd_transinfo user;
758 };
759
760 /*
761 * Per enabled target ID state.
762 * Pointers to lun target state as well as sync/wide negotiation information
763 * for each initiator<->target mapping. For the initiator role we pretend
764 * that we are the target and the targets are the initiators since the
765 * negotiation is the same regardless of role.
766 */
767 struct ahd_tmode_tstate {
768 struct ahd_tmode_lstate* enabled_luns[AHD_NUM_LUNS];
769 struct ahd_initiator_tinfo transinfo[AHD_NUM_TARGETS];
770
771 /*
772 * Per initiator state bitmasks.
773 */
774 uint16_t auto_negotiate;/* Auto Negotiation Required */
775 uint16_t discenable; /* Disconnection allowed */
776 uint16_t tagenable; /* Tagged Queuing allowed */
777 };
778
779 /*
780 * Points of interest along the negotiated transfer scale.
781 */
782 #define AHD_SYNCRATE_160 0x8
783 #define AHD_SYNCRATE_PACED 0x8
784 #define AHD_SYNCRATE_DT 0x9
785 #define AHD_SYNCRATE_ULTRA2 0xa
786 #define AHD_SYNCRATE_ULTRA 0xc
787 #define AHD_SYNCRATE_FAST 0x19
788 #define AHD_SYNCRATE_MIN_DT AHD_SYNCRATE_FAST
789 #define AHD_SYNCRATE_SYNC 0x32
790 #define AHD_SYNCRATE_MIN 0x60
791 #define AHD_SYNCRATE_ASYNC 0xFF
792 #define AHD_SYNCRATE_MAX AHD_SYNCRATE_160
793
794 /* Safe and valid period for async negotiations. */
795 #define AHD_ASYNC_XFER_PERIOD 0x44
796
797 /*
798 * In RevA, the synctable uses a 120MHz rate for the period
799 * factor 8 and 160MHz for the period factor 7. The 120MHz
800 * rate never made it into the official SCSI spec, so we must
801 * compensate when setting the negotiation table for Rev A
802 * parts.
803 */
804 #define AHD_SYNCRATE_REVA_120 0x8
805 #define AHD_SYNCRATE_REVA_160 0x7
806
807 /***************************** Lookup Tables **********************************/
808 /*
809 * Phase -> name and message out response
810 * to parity errors in each phase table.
811 */
812 struct ahd_phase_table_entry {
813 uint8_t phase;
814 uint8_t mesg_out; /* Message response to parity errors */
815 const char *phasemsg;
816 };
817
818 /************************** Serial EEPROM Format ******************************/
819
820 struct seeprom_config {
821 /*
822 * Per SCSI ID Configuration Flags
823 */
824 uint16_t device_flags[16]; /* words 0-15 */
825 #define CFXFER 0x003F /* synchronous transfer rate */
826 #define CFXFER_ASYNC 0x3F
827 #define CFQAS 0x0040 /* Negotiate QAS */
828 #define CFPACKETIZED 0x0080 /* Negotiate Packetized Transfers */
829 #define CFSTART 0x0100 /* send start unit SCSI command */
830 #define CFINCBIOS 0x0200 /* include in BIOS scan */
831 #define CFDISC 0x0400 /* enable disconnection */
832 #define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */
833 #define CFWIDEB 0x1000 /* wide bus device */
834 #define CFHOSTMANAGED 0x8000 /* Managed by a RAID controller */
835
836 /*
837 * BIOS Control Bits
838 */
839 uint16_t bios_control; /* word 16 */
840 #define CFSUPREM 0x0001 /* support all removeable drives */
841 #define CFSUPREMB 0x0002 /* support removeable boot drives */
842 #define CFBIOSSTATE 0x000C /* BIOS Action State */
843 #define CFBS_DISABLED 0x00
844 #define CFBS_ENABLED 0x04
845 #define CFBS_DISABLED_SCAN 0x08
846 #define CFENABLEDV 0x0010 /* Perform Domain Validation */
847 #define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */
848 #define CFSPARITY 0x0040 /* SCSI parity */
849 #define CFEXTEND 0x0080 /* extended translation enabled */
850 #define CFBOOTCD 0x0100 /* Support Bootable CD-ROM */
851 #define CFMSG_LEVEL 0x0600 /* BIOS Message Level */
852 #define CFMSG_VERBOSE 0x0000
853 #define CFMSG_SILENT 0x0200
854 #define CFMSG_DIAG 0x0400
855 #define CFRESETB 0x0800 /* reset SCSI bus at boot */
856 /* UNUSED 0xf000 */
857
858 /*
859 * Host Adapter Control Bits
860 */
861 uint16_t adapter_control; /* word 17 */
862 #define CFAUTOTERM 0x0001 /* Perform Auto termination */
863 #define CFSTERM 0x0002 /* SCSI low byte termination */
864 #define CFWSTERM 0x0004 /* SCSI high byte termination */
865 #define CFSEAUTOTERM 0x0008 /* Ultra2 Perform secondary Auto Term*/
866 #define CFSELOWTERM 0x0010 /* Ultra2 secondary low term */
867 #define CFSEHIGHTERM 0x0020 /* Ultra2 secondary high term */
868 #define CFSTPWLEVEL 0x0040 /* Termination level control */
869 #define CFBIOSAUTOTERM 0x0080 /* Perform Auto termination */
870 #define CFTERM_MENU 0x0100 /* BIOS displays termination menu */
871 #define CFCLUSTERENB 0x8000 /* Cluster Enable */
872
873 /*
874 * Bus Release Time, Host Adapter ID
875 */
876 uint16_t brtime_id; /* word 18 */
877 #define CFSCSIID 0x000f /* host adapter SCSI ID */
878 /* UNUSED 0x00f0 */
879 #define CFBRTIME 0xff00 /* bus release time/PCI Latency Time */
880
881 /*
882 * Maximum targets
883 */
884 uint16_t max_targets; /* word 19 */
885 #define CFMAXTARG 0x00ff /* maximum targets */
886 #define CFBOOTLUN 0x0f00 /* Lun to boot from */
887 #define CFBOOTID 0xf000 /* Target to boot from */
888 uint16_t res_1[10]; /* words 20-29 */
889 uint16_t signature; /* BIOS Signature */
890 #define CFSIGNATURE 0x400
891 uint16_t checksum; /* word 31 */
892 };
893
894 /*
895 * Vital Product Data used during POST and by the BIOS.
896 */
897 struct vpd_config {
898 uint8_t bios_flags;
899 #define VPDMASTERBIOS 0x0001
900 #define VPDBOOTHOST 0x0002
901 uint8_t reserved_1[21];
902 uint8_t resource_type;
903 uint8_t resource_len[2];
904 uint8_t resource_data[8];
905 uint8_t vpd_tag;
906 uint16_t vpd_len;
907 uint8_t vpd_keyword[2];
908 uint8_t length;
909 uint8_t revision;
910 uint8_t device_flags;
911 uint8_t termination_menus[2];
912 uint8_t fifo_threshold;
913 uint8_t end_tag;
914 uint8_t vpd_checksum;
915 uint16_t default_target_flags;
916 uint16_t default_bios_flags;
917 uint16_t default_ctrl_flags;
918 uint8_t default_irq;
919 uint8_t pci_lattime;
920 uint8_t max_target;
921 uint8_t boot_lun;
922 uint16_t signature;
923 uint8_t reserved_2;
924 uint8_t checksum;
925 uint8_t reserved_3[4];
926 };
927
928 /****************************** Flexport Logic ********************************/
929 #define FLXADDR_TERMCTL 0x0
930 #define FLX_TERMCTL_ENSECHIGH 0x8
931 #define FLX_TERMCTL_ENSECLOW 0x4
932 #define FLX_TERMCTL_ENPRIHIGH 0x2
933 #define FLX_TERMCTL_ENPRILOW 0x1
934 #define FLXADDR_ROMSTAT_CURSENSECTL 0x1
935 #define FLX_ROMSTAT_SEECFG 0xF0
936 #define FLX_ROMSTAT_EECFG 0x0F
937 #define FLX_ROMSTAT_SEE_93C66 0x00
938 #define FLX_ROMSTAT_SEE_NONE 0xF0
939 #define FLX_ROMSTAT_EE_512x8 0x0
940 #define FLX_ROMSTAT_EE_1MBx8 0x1
941 #define FLX_ROMSTAT_EE_2MBx8 0x2
942 #define FLX_ROMSTAT_EE_4MBx8 0x3
943 #define FLX_ROMSTAT_EE_16MBx8 0x4
944 #define CURSENSE_ENB 0x1
945 #define FLXADDR_FLEXSTAT 0x2
946 #define FLX_FSTAT_BUSY 0x1
947 #define FLXADDR_CURRENT_STAT 0x4
948 #define FLX_CSTAT_SEC_HIGH 0xC0
949 #define FLX_CSTAT_SEC_LOW 0x30
950 #define FLX_CSTAT_PRI_HIGH 0x0C
951 #define FLX_CSTAT_PRI_LOW 0x03
952 #define FLX_CSTAT_MASK 0x03
953 #define FLX_CSTAT_SHIFT 2
954 #define FLX_CSTAT_OKAY 0x0
955 #define FLX_CSTAT_OVER 0x1
956 #define FLX_CSTAT_UNDER 0x2
957 #define FLX_CSTAT_INVALID 0x3
958
959 int ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf,
960 u_int start_addr, u_int count, int bstream);
961
962 int ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf,
963 u_int start_addr, u_int count);
964 int ahd_verify_cksum(struct seeprom_config *sc);
965 int ahd_acquire_seeprom(struct ahd_softc *ahd);
966 void ahd_release_seeprom(struct ahd_softc *ahd);
967
968 /**************************** Message Buffer *********************************/
969 typedef enum {
970 MSG_FLAG_NONE = 0x00,
971 MSG_FLAG_EXPECT_PPR_BUSFREE = 0x01,
972 MSG_FLAG_IU_REQ_CHANGED = 0x02,
973 MSG_FLAG_EXPECT_IDE_BUSFREE = 0x04,
974 MSG_FLAG_EXPECT_QASREJ_BUSFREE = 0x08,
975 MSG_FLAG_PACKETIZED = 0x10
976 } ahd_msg_flags;
977
978 typedef enum {
979 MSG_TYPE_NONE = 0x00,
980 MSG_TYPE_INITIATOR_MSGOUT = 0x01,
981 MSG_TYPE_INITIATOR_MSGIN = 0x02,
982 MSG_TYPE_TARGET_MSGOUT = 0x03,
983 MSG_TYPE_TARGET_MSGIN = 0x04
984 } ahd_msg_type;
985
986 typedef enum {
987 MSGLOOP_IN_PROG,
988 MSGLOOP_MSGCOMPLETE,
989 MSGLOOP_TERMINATED
990 } msg_loop_stat;
991
992 /*********************** Software Configuration Structure *********************/
993 struct ahd_suspend_channel_state {
994 uint8_t scsiseq;
995 uint8_t sxfrctl0;
996 uint8_t sxfrctl1;
997 uint8_t simode0;
998 uint8_t simode1;
999 uint8_t seltimer;
1000 uint8_t seqctl;
1001 };
1002
1003 struct ahd_suspend_pci_state {
1004 uint32_t devconfig;
1005 uint8_t command;
1006 uint8_t csize_lattime;
1007 };
1008
1009 struct ahd_suspend_state {
1010 struct ahd_suspend_channel_state channel[2];
1011 struct ahd_suspend_pci_state pci_state;
1012 uint8_t optionmode;
1013 uint8_t dscommand0;
1014 uint8_t dspcistatus;
1015 /* hsmailbox */
1016 uint8_t crccontrol1;
1017 uint8_t scbbaddr;
1018 /* Host and sequencer SCB counts */
1019 uint8_t dff_thrsh;
1020 uint8_t *scratch_ram;
1021 uint8_t *btt;
1022 };
1023
1024 typedef void (*ahd_bus_intr_t)(struct ahd_softc *);
1025
1026 typedef enum {
1027 AHD_MODE_DFF0,
1028 AHD_MODE_DFF1,
1029 AHD_MODE_CCHAN,
1030 AHD_MODE_SCSI,
1031 AHD_MODE_CFG,
1032 AHD_MODE_UNKNOWN
1033 } ahd_mode;
1034
1035 #define AHD_MK_MSK(x) (0x01 << (x))
1036 #define AHD_MODE_DFF0_MSK AHD_MK_MSK(AHD_MODE_DFF0)
1037 #define AHD_MODE_DFF1_MSK AHD_MK_MSK(AHD_MODE_DFF1)
1038 #define AHD_MODE_CCHAN_MSK AHD_MK_MSK(AHD_MODE_CCHAN)
1039 #define AHD_MODE_SCSI_MSK AHD_MK_MSK(AHD_MODE_SCSI)
1040 #define AHD_MODE_CFG_MSK AHD_MK_MSK(AHD_MODE_CFG)
1041 #define AHD_MODE_UNKNOWN_MSK AHD_MK_MSK(AHD_MODE_UNKNOWN)
1042 #define AHD_MODE_ANY_MSK (~0)
1043
1044 typedef uint8_t ahd_mode_state;
1045
1046 struct ahd_completion
1047 {
1048 uint16_t tag;
1049 uint8_t sg_status;
1050 uint8_t valid_tag;
1051 };
1052
1053 struct ahd_softc {
1054 bus_space_tag_t tags[2];
1055 bus_space_handle_t bshs[2];
1056 struct scb_data scb_data;
1057
1058 struct hardware_scb *next_queued_hscb;
1059 struct map_node *next_queued_hscb_map;
1060
1061 /*
1062 * SCBs that have been sent to the controller
1063 */
1064 BSD_LIST_HEAD(, scb) pending_scbs;
1065
1066 /*
1067 * Current register window mode information.
1068 */
1069 ahd_mode dst_mode;
1070 ahd_mode src_mode;
1071
1072 /*
1073 * Saved register window mode information
1074 * used for restore on next unpause.
1075 */
1076 ahd_mode saved_dst_mode;
1077 ahd_mode saved_src_mode;
1078
1079 /*
1080 * Platform specific data.
1081 */
1082 struct ahd_platform_data *platform_data;
1083
1084 /*
1085 * Platform specific device information.
1086 */
1087 ahd_dev_softc_t dev_softc;
1088
1089 /*
1090 * Bus specific device information.
1091 */
1092 ahd_bus_intr_t bus_intr;
1093
1094 /*
1095 * Target mode related state kept on a per enabled lun basis.
1096 * Targets that are not enabled will have null entries.
1097 * As an initiator, we keep one target entry for our initiator
1098 * ID to store our sync/wide transfer settings.
1099 */
1100 struct ahd_tmode_tstate *enabled_targets[AHD_NUM_TARGETS];
1101
1102 /*
1103 * The black hole device responsible for handling requests for
1104 * disabled luns on enabled targets.
1105 */
1106 struct ahd_tmode_lstate *black_hole;
1107
1108 /*
1109 * Device instance currently on the bus awaiting a continue TIO
1110 * for a command that was not given the disconnect priveledge.
1111 */
1112 struct ahd_tmode_lstate *pending_device;
1113
1114 /*
1115 * Timer handles for timer driven callbacks.
1116 */
1117 struct timer_list stat_timer;
1118
1119 /*
1120 * Statistics.
1121 */
1122 #define AHD_STAT_UPDATE_US 250000 /* 250ms */
1123 #define AHD_STAT_BUCKETS 4
1124 u_int cmdcmplt_bucket;
1125 uint32_t cmdcmplt_counts[AHD_STAT_BUCKETS];
1126 uint32_t cmdcmplt_total;
1127
1128 /*
1129 * Card characteristics
1130 */
1131 ahd_chip chip;
1132 ahd_feature features;
1133 ahd_bug bugs;
1134 ahd_flag flags;
1135 struct seeprom_config *seep_config;
1136
1137 /* Command Queues */
1138 struct ahd_completion *qoutfifo;
1139 uint16_t qoutfifonext;
1140 uint16_t qoutfifonext_valid_tag;
1141 uint16_t qinfifonext;
1142 uint16_t qinfifo[AHD_SCB_MAX];
1143
1144 /*
1145 * Our qfreeze count. The sequencer compares
1146 * this value with its own counter to determine
1147 * whether to allow selections to occur.
1148 */
1149 uint16_t qfreeze_cnt;
1150
1151 /* Values to store in the SEQCTL register for pause and unpause */
1152 uint8_t unpause;
1153 uint8_t pause;
1154
1155 /* Critical Section Data */
1156 struct cs *critical_sections;
1157 u_int num_critical_sections;
1158
1159 /* Buffer for handling packetized bitbucket. */
1160 uint8_t *overrun_buf;
1161
1162 /* Links for chaining softcs */
1163 TAILQ_ENTRY(ahd_softc) links;
1164
1165 /* Channel Names ('A', 'B', etc.) */
1166 char channel;
1167
1168 /* Initiator Bus ID */
1169 uint8_t our_id;
1170
1171 /*
1172 * Target incoming command FIFO.
1173 */
1174 struct target_cmd *targetcmds;
1175 uint8_t tqinfifonext;
1176
1177 /*
1178 * Cached verson of the hs_mailbox so we can avoid
1179 * pausing the sequencer during mailbox updates.
1180 */
1181 uint8_t hs_mailbox;
1182
1183 /*
1184 * Incoming and outgoing message handling.
1185 */
1186 uint8_t send_msg_perror;
1187 ahd_msg_flags msg_flags;
1188 ahd_msg_type msg_type;
1189 uint8_t msgout_buf[12];/* Message we are sending */
1190 uint8_t msgin_buf[12];/* Message we are receiving */
1191 u_int msgout_len; /* Length of message to send */
1192 u_int msgout_index; /* Current index in msgout */
1193 u_int msgin_index; /* Current index in msgin */
1194
1195 /*
1196 * Mapping information for data structures shared
1197 * between the sequencer and kernel.
1198 */
1199 bus_dma_tag_t parent_dmat;
1200 bus_dma_tag_t shared_data_dmat;
1201 struct map_node shared_data_map;
1202
1203 /* Information saved through suspend/resume cycles */
1204 struct ahd_suspend_state suspend_state;
1205
1206 /* Number of enabled target mode device on this card */
1207 u_int enabled_luns;
1208
1209 /* Initialization level of this data structure */
1210 u_int init_level;
1211
1212 /* PCI cacheline size. */
1213 u_int pci_cachesize;
1214
1215 /* IO Cell Parameters */
1216 uint8_t iocell_opts[AHD_NUM_PER_DEV_ANNEXCOLS];
1217
1218 u_int stack_size;
1219 uint16_t *saved_stack;
1220
1221 /* Per-Unit descriptive information */
1222 const char *description;
1223 const char *bus_description;
1224 char *name;
1225 int unit;
1226
1227 /* Selection Timer settings */
1228 int seltime;
1229
1230 /*
1231 * Interrupt coalescing settings.
1232 */
1233 #define AHD_INT_COALESCING_TIMER_DEFAULT 250 /*us*/
1234 #define AHD_INT_COALESCING_MAXCMDS_DEFAULT 10
1235 #define AHD_INT_COALESCING_MAXCMDS_MAX 127
1236 #define AHD_INT_COALESCING_MINCMDS_DEFAULT 5
1237 #define AHD_INT_COALESCING_MINCMDS_MAX 127
1238 #define AHD_INT_COALESCING_THRESHOLD_DEFAULT 2000
1239 #define AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT 1000
1240 u_int int_coalescing_timer;
1241 u_int int_coalescing_maxcmds;
1242 u_int int_coalescing_mincmds;
1243 u_int int_coalescing_threshold;
1244 u_int int_coalescing_stop_threshold;
1245
1246 uint16_t user_discenable;/* Disconnection allowed */
1247 uint16_t user_tagenable;/* Tagged Queuing allowed */
1248 };
1249
1250 /*************************** IO Cell Configuration ****************************/
1251 #define AHD_PRECOMP_SLEW_INDEX \
1252 (AHD_ANNEXCOL_PRECOMP_SLEW - AHD_ANNEXCOL_PER_DEV0)
1253
1254 #define AHD_AMPLITUDE_INDEX \
1255 (AHD_ANNEXCOL_AMPLITUDE - AHD_ANNEXCOL_PER_DEV0)
1256
1257 #define AHD_SET_SLEWRATE(ahd, new_slew) \
1258 do { \
1259 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_SLEWRATE_MASK; \
1260 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \
1261 (((new_slew) << AHD_SLEWRATE_SHIFT) & AHD_SLEWRATE_MASK); \
1262 } while (0)
1263
1264 #define AHD_SET_PRECOMP(ahd, new_pcomp) \
1265 do { \
1266 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; \
1267 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \
1268 (((new_pcomp) << AHD_PRECOMP_SHIFT) & AHD_PRECOMP_MASK); \
1269 } while (0)
1270
1271 #define AHD_SET_AMPLITUDE(ahd, new_amp) \
1272 do { \
1273 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] &= ~AHD_AMPLITUDE_MASK; \
1274 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] |= \
1275 (((new_amp) << AHD_AMPLITUDE_SHIFT) & AHD_AMPLITUDE_MASK); \
1276 } while (0)
1277
1278 /************************ Active Device Information ***************************/
1279 typedef enum {
1280 ROLE_UNKNOWN,
1281 ROLE_INITIATOR,
1282 ROLE_TARGET
1283 } role_t;
1284
1285 struct ahd_devinfo {
1286 int our_scsiid;
1287 int target_offset;
1288 uint16_t target_mask;
1289 u_int target;
1290 u_int lun;
1291 char channel;
1292 role_t role; /*
1293 * Only guaranteed to be correct if not
1294 * in the busfree state.
1295 */
1296 };
1297
1298 /****************************** PCI Structures ********************************/
1299 #define AHD_PCI_IOADDR0 PCIR_BAR(0) /* I/O BAR*/
1300 #define AHD_PCI_MEMADDR PCIR_BAR(1) /* Memory BAR */
1301 #define AHD_PCI_IOADDR1 PCIR_BAR(3) /* Second I/O BAR */
1302
1303 typedef int (ahd_device_setup_t)(struct ahd_softc *);
1304
1305 struct ahd_pci_identity {
1306 uint64_t full_id;
1307 uint64_t id_mask;
1308 const char *name;
1309 ahd_device_setup_t *setup;
1310 };
1311
1312 /***************************** VL/EISA Declarations ***************************/
1313 struct aic7770_identity {
1314 uint32_t full_id;
1315 uint32_t id_mask;
1316 const char *name;
1317 ahd_device_setup_t *setup;
1318 };
1319 extern struct aic7770_identity aic7770_ident_table [];
1320 extern const int ahd_num_aic7770_devs;
1321
1322 #define AHD_EISA_SLOT_OFFSET 0xc00
1323 #define AHD_EISA_IOSIZE 0x100
1324
1325 /*************************** Function Declarations ****************************/
1326 /******************************************************************************/
1327
1328 /***************************** PCI Front End *********************************/
1329 const struct ahd_pci_identity *ahd_find_pci_device(ahd_dev_softc_t);
1330 int ahd_pci_config(struct ahd_softc *,
1331 const struct ahd_pci_identity *);
1332 int ahd_pci_test_register_access(struct ahd_softc *);
1333 #ifdef CONFIG_PM
1334 void ahd_pci_suspend(struct ahd_softc *);
1335 void ahd_pci_resume(struct ahd_softc *);
1336 #endif
1337
1338 /************************** SCB and SCB queue management **********************/
1339 void ahd_qinfifo_requeue_tail(struct ahd_softc *ahd,
1340 struct scb *scb);
1341
1342 /****************************** Initialization ********************************/
1343 struct ahd_softc *ahd_alloc(void *platform_arg, char *name);
1344 int ahd_softc_init(struct ahd_softc *);
1345 void ahd_controller_info(struct ahd_softc *ahd, char *buf);
1346 int ahd_init(struct ahd_softc *ahd);
1347 #ifdef CONFIG_PM
1348 int ahd_suspend(struct ahd_softc *ahd);
1349 void ahd_resume(struct ahd_softc *ahd);
1350 #endif
1351 int ahd_default_config(struct ahd_softc *ahd);
1352 int ahd_parse_vpddata(struct ahd_softc *ahd,
1353 struct vpd_config *vpd);
1354 int ahd_parse_cfgdata(struct ahd_softc *ahd,
1355 struct seeprom_config *sc);
1356 void ahd_intr_enable(struct ahd_softc *ahd, int enable);
1357 void ahd_pause_and_flushwork(struct ahd_softc *ahd);
1358 void ahd_set_unit(struct ahd_softc *, int);
1359 void ahd_set_name(struct ahd_softc *, char *);
1360 struct scb *ahd_get_scb(struct ahd_softc *ahd, u_int col_idx);
1361 void ahd_free_scb(struct ahd_softc *ahd, struct scb *scb);
1362 void ahd_free(struct ahd_softc *ahd);
1363 int ahd_reset(struct ahd_softc *ahd, int reinit);
1364 int ahd_write_flexport(struct ahd_softc *ahd,
1365 u_int addr, u_int value);
1366 int ahd_read_flexport(struct ahd_softc *ahd, u_int addr,
1367 uint8_t *value);
1368
1369 /***************************** Error Recovery *********************************/
1370 typedef enum {
1371 SEARCH_COMPLETE,
1372 SEARCH_COUNT,
1373 SEARCH_REMOVE,
1374 SEARCH_PRINT
1375 } ahd_search_action;
1376 int ahd_search_qinfifo(struct ahd_softc *ahd, int target,
1377 char channel, int lun, u_int tag,
1378 role_t role, uint32_t status,
1379 ahd_search_action action);
1380 int ahd_search_disc_list(struct ahd_softc *ahd, int target,
1381 char channel, int lun, u_int tag,
1382 int stop_on_first, int remove,
1383 int save_state);
1384 int ahd_reset_channel(struct ahd_softc *ahd, char channel,
1385 int initiate_reset);
1386 /*************************** Utility Functions ********************************/
1387 void ahd_compile_devinfo(struct ahd_devinfo *devinfo,
1388 u_int our_id, u_int target,
1389 u_int lun, char channel,
1390 role_t role);
1391 /************************** Transfer Negotiation ******************************/
1392 void ahd_find_syncrate(struct ahd_softc *ahd, u_int *period,
1393 u_int *ppr_options, u_int maxsync);
1394 /*
1395 * Negotiation types. These are used to qualify if we should renegotiate
1396 * even if our goal and current transport parameters are identical.
1397 */
1398 typedef enum {
1399 AHD_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */
1400 AHD_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */
1401 AHD_NEG_ALWAYS /* Renegotiat even if goal is async. */
1402 } ahd_neg_type;
1403 int ahd_update_neg_request(struct ahd_softc*,
1404 struct ahd_devinfo*,
1405 struct ahd_tmode_tstate*,
1406 struct ahd_initiator_tinfo*,
1407 ahd_neg_type);
1408 void ahd_set_width(struct ahd_softc *ahd,
1409 struct ahd_devinfo *devinfo,
1410 u_int width, u_int type, int paused);
1411 void ahd_set_syncrate(struct ahd_softc *ahd,
1412 struct ahd_devinfo *devinfo,
1413 u_int period, u_int offset,
1414 u_int ppr_options,
1415 u_int type, int paused);
1416 typedef enum {
1417 AHD_QUEUE_NONE,
1418 AHD_QUEUE_BASIC,
1419 AHD_QUEUE_TAGGED
1420 } ahd_queue_alg;
1421
1422 /**************************** Target Mode *************************************/
1423 #ifdef AHD_TARGET_MODE
1424 void ahd_send_lstate_events(struct ahd_softc *,
1425 struct ahd_tmode_lstate *);
1426 void ahd_handle_en_lun(struct ahd_softc *ahd,
1427 struct cam_sim *sim, union ccb *ccb);
1428 cam_status ahd_find_tmode_devs(struct ahd_softc *ahd,
1429 struct cam_sim *sim, union ccb *ccb,
1430 struct ahd_tmode_tstate **tstate,
1431 struct ahd_tmode_lstate **lstate,
1432 int notfound_failure);
1433 #ifndef AHD_TMODE_ENABLE
1434 #define AHD_TMODE_ENABLE 0
1435 #endif
1436 #endif
1437 /******************************* Debug ***************************************/
1438 #ifdef AHD_DEBUG
1439 extern uint32_t ahd_debug;
1440 #define AHD_SHOW_MISC 0x00001
1441 #define AHD_SHOW_SENSE 0x00002
1442 #define AHD_SHOW_RECOVERY 0x00004
1443 #define AHD_DUMP_SEEPROM 0x00008
1444 #define AHD_SHOW_TERMCTL 0x00010
1445 #define AHD_SHOW_MEMORY 0x00020
1446 #define AHD_SHOW_MESSAGES 0x00040
1447 #define AHD_SHOW_MODEPTR 0x00080
1448 #define AHD_SHOW_SELTO 0x00100
1449 #define AHD_SHOW_FIFOS 0x00200
1450 #define AHD_SHOW_QFULL 0x00400
1451 #define AHD_SHOW_DV 0x00800
1452 #define AHD_SHOW_MASKED_ERRORS 0x01000
1453 #define AHD_SHOW_QUEUE 0x02000
1454 #define AHD_SHOW_TQIN 0x04000
1455 #define AHD_SHOW_SG 0x08000
1456 #define AHD_SHOW_INT_COALESCING 0x10000
1457 #define AHD_DEBUG_SEQUENCER 0x20000
1458 #endif
1459 void ahd_print_devinfo(struct ahd_softc *ahd,
1460 struct ahd_devinfo *devinfo);
1461 void ahd_dump_card_state(struct ahd_softc *ahd);
1462 int ahd_print_register(const ahd_reg_parse_entry_t *table,
1463 u_int num_entries,
1464 const char *name,
1465 u_int address,
1466 u_int value,
1467 u_int *cur_column,
1468 u_int wrap_point);
1469 #endif /* _AIC79XX_H_ */